Module Definition
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Module : alert_handler_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_alert_handler_reg_0.1/rtl/alert_handler_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_wrap.u_reg 99.17 100.00 96.67 100.00 100.00

Line Coverage for Module : alert_handler_reg_top
Line No.TotalCoveredPercent
TOTAL22282228100.00
ALWAYS7544100.00
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CONT_ASSIGN1706411100.00
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CONT_ASSIGN1709011100.00
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CONT_ASSIGN1749011100.00
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CONT_ASSIGN1751011100.00
CONT_ASSIGN1751111100.00
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CONT_ASSIGN1751511100.00
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CONT_ASSIGN1751811100.00
CONT_ASSIGN1751911100.00
CONT_ASSIGN1752011100.00
CONT_ASSIGN1752211100.00
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CONT_ASSIGN1752611100.00
CONT_ASSIGN1752811100.00
CONT_ASSIGN1753011100.00
CONT_ASSIGN1753211100.00
CONT_ASSIGN1753411100.00
CONT_ASSIGN1753611100.00
CONT_ASSIGN1753811100.00
CONT_ASSIGN1754011100.00
CONT_ASSIGN1754111100.00
CONT_ASSIGN1754311100.00
CONT_ASSIGN1754411100.00
CONT_ASSIGN1754511100.00
CONT_ASSIGN1754711100.00
CONT_ASSIGN1754811100.00
CONT_ASSIGN1754911100.00
CONT_ASSIGN1755011100.00
CONT_ASSIGN1755211100.00
CONT_ASSIGN1755311100.00
CONT_ASSIGN1755411100.00
CONT_ASSIGN1755611100.00
CONT_ASSIGN1755711100.00
CONT_ASSIGN1755811100.00
CONT_ASSIGN1756011100.00
CONT_ASSIGN1756111100.00
CONT_ASSIGN1756211100.00
CONT_ASSIGN1756411100.00
CONT_ASSIGN1756511100.00
CONT_ASSIGN1756611100.00
CONT_ASSIGN1756811100.00
CONT_ASSIGN1756911100.00
CONT_ASSIGN1757011100.00
CONT_ASSIGN1757211100.00
CONT_ASSIGN1757311100.00
CONT_ASSIGN1757411100.00
CONT_ASSIGN1757611100.00
CONT_ASSIGN1757711100.00
CONT_ASSIGN1757811100.00
ALWAYS17582351351100.00
ALWAYS17937397397100.00
ALWAYS1939533100.00
ALWAYS1940333100.00
CONT_ASSIGN1941111100.00
CONT_ASSIGN1941411100.00
CONT_ASSIGN1963411100.00
CONT_ASSIGN1985611100.00
CONT_ASSIGN1986411100.00
CONT_ASSIGN1986511100.00

Click here to see the source line report.

Cond Coverage for Module : alert_handler_reg_top
TotalCoveredPercent
Conditions4802464296.67
Logical4802464296.67
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
65-9122100.00
9163-15665100.00
15666-15837100.00
15838-15927100.00
15927100.00
15927100.00
15927-1637699.49
16379-1663093.99
16631-1684389.25
16846-1707090.42
17073-1736196.60
17364-1941190.45

Branch Coverage for Module : alert_handler_reg_top
Line No.TotalCoveredPercent
Branches 360 360 100.00
TERNARY 15923 2 2 100.00
IF 75 3 3 100.00
CASE 17938 351 351 100.00
IF 19395 2 2 100.00
IF 19403 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_alert_handler_reg_0.1/rtl/alert_handler_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_alert_handler_reg_0.1/rtl/alert_handler_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 15923 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T13,T21,T22
0 Covered T13,T21,T22


LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 77 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T13,T21,T22
0 1 Covered T23,T165,T162
0 0 Covered T13,T21,T22


LineNo. Expression -1-: 17938 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T13,T21,T22
addr_hit[1] Covered T13,T21,T22
addr_hit[2] Covered T13,T21,T22
addr_hit[3] Covered T13,T21,T22
addr_hit[4] Covered T13,T21,T22
addr_hit[5] Covered T13,T21,T22
addr_hit[6] Covered T13,T21,T22
addr_hit[7] Covered T13,T21,T22
addr_hit[8] Covered T13,T21,T22
addr_hit[9] Covered T13,T21,T22
addr_hit[10] Covered T13,T21,T22
addr_hit[11] Covered T13,T21,T22
addr_hit[12] Covered T13,T21,T22
addr_hit[13] Covered T13,T21,T22
addr_hit[14] Covered T13,T21,T22
addr_hit[15] Covered T13,T21,T22
addr_hit[16] Covered T13,T21,T22
addr_hit[17] Covered T13,T21,T22
addr_hit[18] Covered T13,T21,T22
addr_hit[19] Covered T13,T21,T22
addr_hit[20] Covered T13,T21,T22
addr_hit[21] Covered T13,T21,T22
addr_hit[22] Covered T13,T21,T22
addr_hit[23] Covered T13,T21,T22
addr_hit[24] Covered T13,T21,T22
addr_hit[25] Covered T13,T21,T22
addr_hit[26] Covered T13,T21,T22
addr_hit[27] Covered T13,T21,T22
addr_hit[28] Covered T13,T21,T22
addr_hit[29] Covered T13,T21,T22
addr_hit[30] Covered T13,T21,T22
addr_hit[31] Covered T13,T21,T22
addr_hit[32] Covered T13,T21,T22
addr_hit[33] Covered T13,T21,T22
addr_hit[34] Covered T13,T21,T22
addr_hit[35] Covered T13,T21,T22
addr_hit[36] Covered T13,T21,T22
addr_hit[37] Covered T13,T21,T22
addr_hit[38] Covered T13,T21,T22
addr_hit[39] Covered T13,T21,T22
addr_hit[40] Covered T13,T21,T22
addr_hit[41] Covered T13,T21,T22
addr_hit[42] Covered T13,T21,T22
addr_hit[43] Covered T13,T21,T22
addr_hit[44] Covered T13,T21,T22
addr_hit[45] Covered T13,T21,T22
addr_hit[46] Covered T13,T21,T22
addr_hit[47] Covered T13,T21,T22
addr_hit[48] Covered T13,T21,T22
addr_hit[49] Covered T13,T21,T22
addr_hit[50] Covered T13,T21,T22
addr_hit[51] Covered T13,T21,T22
addr_hit[52] Covered T13,T21,T22
addr_hit[53] Covered T13,T21,T22
addr_hit[54] Covered T13,T21,T22
addr_hit[55] Covered T13,T21,T22
addr_hit[56] Covered T13,T21,T22
addr_hit[57] Covered T13,T21,T22
addr_hit[58] Covered T13,T21,T22
addr_hit[59] Covered T13,T21,T22
addr_hit[60] Covered T13,T21,T22
addr_hit[61] Covered T13,T21,T22
addr_hit[62] Covered T13,T21,T22
addr_hit[63] Covered T13,T21,T22
addr_hit[64] Covered T13,T21,T22
addr_hit[65] Covered T13,T21,T22
addr_hit[66] Covered T13,T21,T22
addr_hit[67] Covered T13,T21,T22
addr_hit[68] Covered T13,T21,T22
addr_hit[69] Covered T13,T21,T22
addr_hit[70] Covered T13,T21,T22
addr_hit[71] Covered T13,T21,T22
addr_hit[72] Covered T13,T21,T22
addr_hit[73] Covered T13,T21,T22
addr_hit[74] Covered T13,T21,T22
addr_hit[75] Covered T13,T21,T22
addr_hit[76] Covered T13,T21,T22
addr_hit[77] Covered T13,T21,T22
addr_hit[78] Covered T13,T21,T22
addr_hit[79] Covered T13,T21,T22
addr_hit[80] Covered T13,T21,T22
addr_hit[81] Covered T13,T21,T22
addr_hit[82] Covered T13,T21,T22
addr_hit[83] Covered T13,T21,T22
addr_hit[84] Covered T13,T21,T22
addr_hit[85] Covered T13,T21,T22
addr_hit[86] Covered T13,T21,T22
addr_hit[87] Covered T13,T21,T22
addr_hit[88] Covered T13,T21,T22
addr_hit[89] Covered T13,T21,T22
addr_hit[90] Covered T13,T21,T22
addr_hit[91] Covered T13,T21,T22
addr_hit[92] Covered T13,T21,T22
addr_hit[93] Covered T13,T21,T22
addr_hit[94] Covered T13,T21,T22
addr_hit[95] Covered T13,T21,T22
addr_hit[96] Covered T13,T21,T22
addr_hit[97] Covered T13,T21,T22
addr_hit[98] Covered T13,T21,T22
addr_hit[99] Covered T13,T21,T22
addr_hit[100] Covered T13,T21,T22
addr_hit[101] Covered T13,T21,T22
addr_hit[102] Covered T13,T21,T22
addr_hit[103] Covered T13,T21,T22
addr_hit[104] Covered T13,T21,T22
addr_hit[105] Covered T13,T21,T22
addr_hit[106] Covered T13,T21,T22
addr_hit[107] Covered T13,T21,T22
addr_hit[108] Covered T13,T21,T22
addr_hit[109] Covered T13,T21,T22
addr_hit[110] Covered T13,T21,T22
addr_hit[111] Covered T13,T21,T22
addr_hit[112] Covered T13,T21,T22
addr_hit[113] Covered T13,T21,T22
addr_hit[114] Covered T13,T21,T22
addr_hit[115] Covered T13,T21,T22
addr_hit[116] Covered T13,T21,T22
addr_hit[117] Covered T13,T21,T22
addr_hit[118] Covered T13,T21,T22
addr_hit[119] Covered T13,T21,T22
addr_hit[120] Covered T13,T21,T22
addr_hit[121] Covered T13,T21,T22
addr_hit[122] Covered T13,T21,T22
addr_hit[123] Covered T13,T21,T22
addr_hit[124] Covered T13,T21,T22
addr_hit[125] Covered T13,T21,T22
addr_hit[126] Covered T13,T21,T22
addr_hit[127] Covered T13,T21,T22
addr_hit[128] Covered T13,T21,T22
addr_hit[129] Covered T13,T21,T22
addr_hit[130] Covered T13,T21,T22
addr_hit[131] Covered T13,T21,T22
addr_hit[132] Covered T13,T21,T22
addr_hit[133] Covered T13,T21,T22
addr_hit[134] Covered T13,T21,T22
addr_hit[135] Covered T13,T21,T22
addr_hit[136] Covered T13,T21,T22
addr_hit[137] Covered T13,T21,T22
addr_hit[138] Covered T13,T21,T22
addr_hit[139] Covered T13,T21,T22
addr_hit[140] Covered T13,T21,T22
addr_hit[141] Covered T13,T21,T22
addr_hit[142] Covered T13,T21,T22
addr_hit[143] Covered T13,T21,T22
addr_hit[144] Covered T13,T21,T22
addr_hit[145] Covered T13,T21,T22
addr_hit[146] Covered T13,T21,T22
addr_hit[147] Covered T13,T21,T22
addr_hit[148] Covered T13,T21,T22
addr_hit[149] Covered T13,T21,T22
addr_hit[150] Covered T13,T21,T22
addr_hit[151] Covered T13,T21,T22
addr_hit[152] Covered T13,T21,T22
addr_hit[153] Covered T13,T21,T22
addr_hit[154] Covered T13,T21,T22
addr_hit[155] Covered T13,T21,T22
addr_hit[156] Covered T13,T21,T22
addr_hit[157] Covered T13,T21,T22
addr_hit[158] Covered T13,T21,T22
addr_hit[159] Covered T13,T21,T22
addr_hit[160] Covered T13,T21,T22
addr_hit[161] Covered T13,T21,T22
addr_hit[162] Covered T13,T21,T22
addr_hit[163] Covered T13,T21,T22
addr_hit[164] Covered T13,T21,T22
addr_hit[165] Covered T13,T21,T22
addr_hit[166] Covered T13,T21,T22
addr_hit[167] Covered T13,T21,T22
addr_hit[168] Covered T13,T21,T22
addr_hit[169] Covered T13,T21,T22
addr_hit[170] Covered T13,T21,T22
addr_hit[171] Covered T13,T21,T22
addr_hit[172] Covered T13,T21,T22
addr_hit[173] Covered T13,T21,T22
addr_hit[174] Covered T13,T21,T22
addr_hit[175] Covered T13,T21,T22
addr_hit[176] Covered T13,T21,T22
addr_hit[177] Covered T13,T21,T22
addr_hit[178] Covered T13,T21,T22
addr_hit[179] Covered T13,T21,T22
addr_hit[180] Covered T13,T21,T22
addr_hit[181] Covered T13,T21,T22
addr_hit[182] Covered T13,T21,T22
addr_hit[183] Covered T13,T21,T22
addr_hit[184] Covered T13,T21,T22
addr_hit[185] Covered T13,T21,T22
addr_hit[186] Covered T13,T21,T22
addr_hit[187] Covered T13,T21,T22
addr_hit[188] Covered T13,T21,T22
addr_hit[189] Covered T13,T21,T22
addr_hit[190] Covered T13,T21,T22
addr_hit[191] Covered T13,T21,T22
addr_hit[192] Covered T13,T21,T22
addr_hit[193] Covered T13,T21,T22
addr_hit[194] Covered T13,T21,T22
addr_hit[195] Covered T13,T21,T22
addr_hit[196] Covered T13,T21,T22
addr_hit[197] Covered T13,T21,T22
addr_hit[198] Covered T13,T21,T22
addr_hit[199] Covered T13,T21,T22
addr_hit[200] Covered T13,T21,T22
addr_hit[201] Covered T13,T21,T22
addr_hit[202] Covered T13,T21,T22
addr_hit[203] Covered T13,T21,T22
addr_hit[204] Covered T13,T21,T22
addr_hit[205] Covered T13,T21,T22
addr_hit[206] Covered T13,T21,T22
addr_hit[207] Covered T13,T21,T22
addr_hit[208] Covered T13,T21,T22
addr_hit[209] Covered T13,T21,T22
addr_hit[210] Covered T13,T21,T22
addr_hit[211] Covered T13,T21,T22
addr_hit[212] Covered T13,T21,T22
addr_hit[213] Covered T13,T21,T22
addr_hit[214] Covered T13,T21,T22
addr_hit[215] Covered T13,T21,T22
addr_hit[216] Covered T13,T21,T22
addr_hit[217] Covered T13,T21,T22
addr_hit[218] Covered T13,T21,T22
addr_hit[219] Covered T13,T21,T22
addr_hit[220] Covered T13,T21,T22
addr_hit[221] Covered T13,T21,T22
addr_hit[222] Covered T13,T21,T22
addr_hit[223] Covered T13,T21,T22
addr_hit[224] Covered T13,T21,T22
addr_hit[225] Covered T13,T21,T22
addr_hit[226] Covered T13,T21,T22
addr_hit[227] Covered T13,T21,T22
addr_hit[228] Covered T13,T21,T22
addr_hit[229] Covered T13,T21,T22
addr_hit[230] Covered T13,T21,T22
addr_hit[231] Covered T13,T21,T22
addr_hit[232] Covered T13,T21,T22
addr_hit[233] Covered T13,T21,T22
addr_hit[234] Covered T13,T21,T22
addr_hit[235] Covered T13,T21,T22
addr_hit[236] Covered T13,T21,T22
addr_hit[237] Covered T13,T21,T22
addr_hit[238] Covered T13,T21,T22
addr_hit[239] Covered T13,T21,T22
addr_hit[240] Covered T13,T21,T22
addr_hit[241] Covered T13,T21,T22
addr_hit[242] Covered T13,T21,T22
addr_hit[243] Covered T13,T21,T22
addr_hit[244] Covered T13,T21,T22
addr_hit[245] Covered T13,T21,T22
addr_hit[246] Covered T13,T21,T22
addr_hit[247] Covered T13,T21,T22
addr_hit[248] Covered T13,T21,T22
addr_hit[249] Covered T13,T21,T22
addr_hit[250] Covered T13,T21,T22
addr_hit[251] Covered T13,T21,T22
addr_hit[252] Covered T13,T21,T22
addr_hit[253] Covered T13,T21,T22
addr_hit[254] Covered T13,T21,T22
addr_hit[255] Covered T13,T21,T22
addr_hit[256] Covered T13,T21,T22
addr_hit[257] Covered T13,T21,T22
addr_hit[258] Covered T13,T21,T22
addr_hit[259] Covered T13,T21,T22
addr_hit[260] Covered T13,T21,T22
addr_hit[261] Covered T13,T21,T22
addr_hit[262] Covered T13,T21,T22
addr_hit[263] Covered T13,T21,T22
addr_hit[264] Covered T13,T21,T22
addr_hit[265] Covered T13,T21,T22
addr_hit[266] Covered T13,T21,T22
addr_hit[267] Covered T13,T21,T22
addr_hit[268] Covered T13,T21,T22
addr_hit[269] Covered T13,T21,T22
addr_hit[270] Covered T13,T21,T22
addr_hit[271] Covered T13,T21,T22
addr_hit[272] Covered T13,T21,T22
addr_hit[273] Covered T13,T21,T22
addr_hit[274] Covered T13,T21,T22
addr_hit[275] Covered T13,T21,T22
addr_hit[276] Covered T13,T21,T22
addr_hit[277] Covered T13,T21,T22
addr_hit[278] Covered T13,T21,T22
addr_hit[279] Covered T13,T21,T22
addr_hit[280] Covered T13,T21,T22
addr_hit[281] Covered T13,T21,T22
addr_hit[282] Covered T13,T21,T22
addr_hit[283] Covered T13,T21,T22
addr_hit[284] Covered T13,T21,T22
addr_hit[285] Covered T13,T21,T22
addr_hit[286] Covered T13,T21,T22
addr_hit[287] Covered T13,T21,T22
addr_hit[288] Covered T13,T21,T22
addr_hit[289] Covered T13,T21,T22
addr_hit[290] Covered T13,T21,T22
addr_hit[291] Covered T13,T21,T22
addr_hit[292] Covered T13,T21,T22
addr_hit[293] Covered T13,T21,T22
addr_hit[294] Covered T13,T21,T22
addr_hit[295] Covered T13,T21,T22
addr_hit[296] Covered T13,T21,T22
addr_hit[297] Covered T13,T21,T22
addr_hit[298] Covered T13,T21,T22
addr_hit[299] Covered T13,T21,T22
addr_hit[300] Covered T13,T21,T22
addr_hit[301] Covered T13,T21,T22
addr_hit[302] Covered T13,T21,T22
addr_hit[303] Covered T13,T21,T22
addr_hit[304] Covered T13,T21,T22
addr_hit[305] Covered T13,T21,T22
addr_hit[306] Covered T13,T21,T22
addr_hit[307] Covered T13,T21,T22
addr_hit[308] Covered T13,T21,T22
addr_hit[309] Covered T13,T21,T22
addr_hit[310] Covered T13,T21,T22
addr_hit[311] Covered T13,T21,T22
addr_hit[312] Covered T13,T21,T22
addr_hit[313] Covered T13,T21,T22
addr_hit[314] Covered T13,T21,T22
addr_hit[315] Covered T13,T21,T22
addr_hit[316] Covered T13,T21,T22
addr_hit[317] Covered T13,T21,T22
addr_hit[318] Covered T13,T21,T22
addr_hit[319] Covered T13,T21,T22
addr_hit[320] Covered T13,T21,T22
addr_hit[321] Covered T13,T21,T22
addr_hit[322] Covered T13,T21,T22
addr_hit[323] Covered T13,T21,T22
addr_hit[324] Covered T13,T21,T22
addr_hit[325] Covered T13,T21,T22
addr_hit[326] Covered T13,T21,T22
addr_hit[327] Covered T13,T21,T22
addr_hit[328] Covered T13,T21,T22
addr_hit[329] Covered T13,T21,T22
addr_hit[330] Covered T13,T21,T22
addr_hit[331] Covered T13,T21,T22
addr_hit[332] Covered T13,T21,T22
addr_hit[333] Covered T13,T21,T22
addr_hit[334] Covered T13,T21,T22
addr_hit[335] Covered T13,T21,T22
addr_hit[336] Covered T13,T21,T22
addr_hit[337] Covered T13,T21,T22
addr_hit[338] Covered T13,T21,T22
addr_hit[339] Covered T13,T21,T22
addr_hit[340] Covered T13,T21,T22
addr_hit[341] Covered T13,T21,T22
addr_hit[342] Covered T13,T21,T22
addr_hit[343] Covered T13,T21,T22
addr_hit[344] Covered T13,T21,T22
addr_hit[345] Covered T13,T21,T22
addr_hit[346] Covered T13,T21,T22
addr_hit[347] Covered T13,T21,T22
addr_hit[348] Covered T13,T21,T22
addr_hit[349] Covered T13,T21,T22
default Covered T13,T21,T22


LineNo. Expression -1-: 19395 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T13,T21,T22
0 Covered T13,T21,T22


LineNo. Expression -1-: 19403 if ((!rst_shadowed_ni))

Branches:
-1-StatusTests
1 Covered T13,T21,T22
0 Covered T13,T21,T22


Assert Coverage for Module : alert_handler_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 788927788 99224405 0 0
reAfterRv 788927788 99224365 0 0
rePulse 788927788 14892548 0 0
wePulse 788927788 84331817 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 788927788 99224405 0 0
T13 270105 54479 0 0
T21 17083 8027 0 0
T22 193 22 0 0
T23 29153 13559 0 0
T24 5464 709 0 0
T25 2937 1363 0 0
T26 6307 688 0 0
T27 4064 129 0 0
T28 9099 1348 0 0
T29 10051 618 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 788927788 99224365 0 0
T13 270105 54479 0 0
T21 17083 8027 0 0
T22 193 22 0 0
T23 29153 13559 0 0
T24 5464 709 0 0
T25 2937 1363 0 0
T26 6307 688 0 0
T27 4064 129 0 0
T28 9099 1348 0 0
T29 10051 618 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 788927788 14892548 0 0
T13 270105 53603 0 0
T21 17083 3570 0 0
T22 193 11 0 0
T23 29153 5535 0 0
T24 5464 699 0 0
T25 2937 563 0 0
T26 6307 288 0 0
T27 4064 2 0 0
T28 9099 548 0 0
T29 10051 10 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 788927788 84331817 0 0
T13 270105 876 0 0
T21 17083 4457 0 0
T22 193 11 0 0
T23 29153 8024 0 0
T24 5464 10 0 0
T25 2937 800 0 0
T26 6307 400 0 0
T27 4064 127 0 0
T28 9099 800 0 0
T29 10051 608 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%