Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T30
1	1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T31,T32
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T14,T31,T33
1	1	1	Covered	T1,T31,T33

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T31,T33
0	1	Covered	T31,T33,T34
1	0	Covered	T34,T35,T36

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T31,T33
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T34,T35,T36

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T31,T33
1	0	Covered	T37
1	1	Covered	T31,T33,T34

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T8,T7

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T14

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T19

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T4,T5,T16

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T5,T8,T19

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T4,T5

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T18

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T13
IdleSt	175	Covered	T13
Phase0St	146	Covered	T13
Phase1St	192	Covered	T13
Phase2St	209	Covered	T13
Phase3St	227	Covered	T13
TerminalSt	243	Covered	T13
TimeoutSt	153	Covered	T13

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	278	Covered	T13
IdleSt->Phase0St	146	Covered	T13
IdleSt->TimeoutSt	153	Covered	T13
Phase0St->FsmErrorSt	278	Not Covered
Phase0St->IdleSt	188	Covered	T13
Phase0St->Phase1St	192	Covered	T13
Phase1St->FsmErrorSt	278	Not Covered
Phase1St->IdleSt	205	Covered	T13
Phase1St->Phase2St	209	Covered	T13
Phase2St->FsmErrorSt	278	Not Covered
Phase2St->IdleSt	223	Covered	T13
Phase2St->Phase3St	227	Covered	T13
Phase3St->FsmErrorSt	278	Not Covered
Phase3St->IdleSt	239	Covered	T13
Phase3St->TerminalSt	243	Covered	T13
TerminalSt->FsmErrorSt	278	Not Covered
TerminalSt->IdleSt	255	Covered	T13
TimeoutSt->FsmErrorSt	278	Not Covered
TimeoutSt->IdleSt	175	Covered	T13
TimeoutSt->Phase0St	166	Covered	T13

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T31,T33
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T31,T33,T34
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T31,T33
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T33,T34
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T36,T38,T39
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T36,T40,T39
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T41,T42,T39
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T43,T44,T45
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1266	0	0
CheckAccumTrig0_A	2147483647	2603	0	0
CheckAccumTrig1_A	2147483647	129	0	0
CheckClr_A	2147483647	1265	0	0
CheckEn_A	2147483647	1333267987	0	0
CheckPhase0_A	2147483647	3019	0	0
CheckPhase1_A	2147483647	2961	0	0
CheckPhase2_A	2147483647	2904	0	0
CheckPhase3_A	2147483647	2847	0	0
CheckTimeout0_A	2147483647	3606	0	0
CheckTimeoutSt1_A	2147483647	496499	0	0
CheckTimeoutSt2_A	2147483647	3159	0	0
CheckTimeoutStTrig_A	2147483647	318	0	0
ErrorStAllEscAsserted_A	2147483647	6289	0	0
ErrorStIsTerminal_A	2147483647	5209	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1266	0	0
T10	137560	331	0	0
T11	89592	127	0	0
T12	0	268	0	0
T46	0	261	0	0
T47	0	279	0	0
T48	686484	0	0	0
T49	2463844	0	0	0
T50	6224	0	0	0
T51	2200648	0	0	0
T52	106800	0	0	0
T53	2866668	0	0	0
T54	312168	0	0	0
T55	109700	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2603	0	0
T1	60818	1	0	0
T2	606686	4	0	0
T3	449667	1	0	0
T4	3886136	1	0	0
T5	939576	4	0	0
T6	269940	4	0	0
T7	1496660	4	0	0
T8	2393180	2	0	0
T14	1030854	3	0	0
T16	0	8	0	0
T17	0	2	0	0
T18	62868	1	0	0
T19	1962048	2	0	0
T20	1397632	2	0	0
T31	1274	0	0	0
T43	0	4	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	129	0	0
T9	666087	0	0	0
T34	636679	1	0	0
T35	71099	1	0	0
T36	1447768	2	0	0
T39	0	1	0	0
T53	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	3	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	5	0	0
T67	0	1	0	0
T68	0	2	0	0
T69	0	2	0	0
T70	0	3	0	0
T71	0	1	0	0
T72	0	4	0	0
T73	0	2	0	0
T74	0	4	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	0	0	0
T78	51445	0	0	0
T79	9124	0	0	0
T80	27585	0	0	0
T81	214115	0	0	0
T82	3202	0	0	0
T83	90992	0	0	0
T84	1008330	0	0	0
T85	15276	0	0	0
T86	1241140	0	0	0
T87	197664	0	0	0
T88	220028	0	0	0
T89	39048	0	0	0
T90	132224	0	0	0
T91	132845	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1265	0	0
T2	303343	2	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	134970	0	0	0
T7	748330	0	0	0
T8	1196590	1	0	0
T9	666087	0	0	0
T14	687236	0	0	0
T16	0	2	0	0
T18	15717	0	0	0
T19	981024	0	0	0
T20	698816	0	0	0
T31	0	1	0	0
T34	636679	1	0	0
T36	0	11	0	0
T38	0	6	0	0
T41	0	1	0	0
T43	0	2	0	0
T56	0	1	0	0
T59	0	1	0	0
T60	0	4	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	0	0	0
T78	51445	0	0	0
T79	9124	0	0	0
T80	27585	0	0	0
T81	214115	2	0	0
T82	3202	0	0	0
T85	0	1	0	0
T92	0	3	0	0
T93	0	5	0	0
T94	0	1	0	0
T95	0	3	0	0
T96	0	2	0	0
T97	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1333267987	0	0
T1	243272	145698	0	0
T2	1213372	607782	0	0
T3	599556	309585	0	0
T4	3886136	1891693	0	0
T5	939576	265872	0	0
T7	1496660	380076	0	0
T8	2393180	1834227	0	0
T18	62868	49201	0	0
T19	1962048	992890	0	0
T20	1397632	719653	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3019	0	0
T1	60818	1	0	0
T2	606686	4	0	0
T3	449667	1	0	0
T4	3886136	1	0	0
T5	939576	4	0	0
T6	269940	4	0	0
T7	1496660	4	0	0
T8	2393180	2	0	0
T14	1030854	3	0	0
T16	0	8	0	0
T17	0	2	0	0
T18	62868	1	0	0
T19	1962048	2	0	0
T20	1397632	2	0	0
T31	1274	1	0	0
T43	0	4	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2961	0	0
T1	60818	1	0	0
T2	606686	4	0	0
T3	449667	1	0	0
T4	3886136	1	0	0
T5	939576	4	0	0
T6	269940	4	0	0
T7	1496660	4	0	0
T8	2393180	2	0	0
T14	1030854	3	0	0
T16	0	8	0	0
T17	0	2	0	0
T18	62868	1	0	0
T19	1962048	2	0	0
T20	1397632	2	0	0
T31	1274	1	0	0
T43	0	4	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2904	0	0
T1	60818	1	0	0
T2	606686	4	0	0
T3	449667	1	0	0
T4	3886136	1	0	0
T5	939576	4	0	0
T6	269940	4	0	0
T7	1496660	4	0	0
T8	2393180	2	0	0
T14	1030854	3	0	0
T16	0	8	0	0
T17	0	2	0	0
T18	62868	1	0	0
T19	1962048	2	0	0
T20	1397632	2	0	0
T31	1274	1	0	0
T43	0	4	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2847	0	0
T1	60818	1	0	0
T2	606686	4	0	0
T3	449667	1	0	0
T4	3886136	1	0	0
T5	939576	4	0	0
T6	269940	4	0	0
T7	1496660	4	0	0
T8	2393180	2	0	0
T14	1030854	3	0	0
T16	0	8	0	0
T17	0	2	0	0
T18	62868	1	0	0
T19	1962048	2	0	0
T20	1397632	2	0	0
T31	1274	1	0	0
T43	0	3	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3606	0	0
T1	60818	1	0	0
T2	303343	0	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	0	0	0
T7	374165	0	0	0
T8	598295	0	0	0
T15	162005	0	0	0
T16	254279	0	0	0
T17	538054	0	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	0	0	0
T31	1274	1	0	0
T32	19531	0	0	0
T33	240282	13	0	0
T34	1273358	54	0	0
T35	0	5	0	0
T36	0	30	0	0
T43	174908	0	0	0
T60	0	5	0	0
T75	100068	0	0	0
T76	198975	0	0	0
T77	0	5	0	0
T78	0	9	0	0
T80	0	11	0	0
T81	0	1	0	0
T85	0	1	0	0
T92	0	35	0	0
T93	0	64	0	0
T95	0	3	0	0
T98	0	2	0	0
T99	34594	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	496499	0	0
T1	60818	36	0	0
T2	303343	0	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	0	0	0
T7	374165	0	0	0
T8	598295	0	0	0
T15	162005	0	0	0
T16	254279	0	0	0
T17	538054	0	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	0	0	0
T31	1274	40	0	0
T32	19531	0	0	0
T33	240282	1878	0	0
T34	1273358	12944	0	0
T35	0	880	0	0
T36	0	4116	0	0
T43	174908	0	0	0
T60	0	725	0	0
T75	100068	0	0	0
T76	198975	0	0	0
T77	0	1111	0	0
T78	0	1174	0	0
T80	0	712	0	0
T81	0	29	0	0
T85	0	169	0	0
T92	0	7514	0	0
T93	0	7711	0	0
T95	0	614	0	0
T98	0	257	0	0
T99	34594	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3159	0	0
T1	60818	1	0	0
T2	303343	0	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	0	0	0
T7	374165	0	0	0
T8	598295	0	0	0
T9	1332174	0	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	0	0	0
T33	120141	12	0	0
T34	1273358	43	0	0
T35	0	2	0	0
T36	0	26	0	0
T41	0	1	0	0
T60	0	17	0	0
T75	100068	0	0	0
T76	397950	0	0	0
T77	241634	2	0	0
T78	102890	8	0	0
T79	18248	0	0	0
T80	27585	10	0	0
T81	214115	1	0	0
T82	3202	0	0	0
T85	0	1	0	0
T92	0	30	0	0
T93	0	61	0	0
T95	0	45	0	0
T96	0	4	0	0
T98	0	2	0	0
T100	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	318	0	0
T9	1998261	0	0	0
T15	162005	0	0	0
T16	254279	0	0	0
T17	538054	0	0	0
T31	1274	1	0	0
T32	19531	0	0	0
T33	240282	1	0	0
T34	2546716	8	0	0
T35	0	1	0	0
T36	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	174908	0	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	0	4	0	0
T63	0	2	0	0
T75	200136	0	0	0
T76	596925	0	0	0
T77	362451	1	0	0
T78	154335	1	0	0
T79	27372	0	0	0
T80	55170	1	0	0
T81	428230	0	0	0
T82	6404	0	0	0
T92	0	5	0	0
T93	0	3	0	0
T99	34594	0	0	0
T100	0	1	0	0
T101	0	3	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6289	0	0
T10	137560	1462	0	0
T11	89592	695	0	0
T12	0	1417	0	0
T46	0	1366	0	0
T47	0	1349	0	0
T48	686484	0	0	0
T49	2463844	0	0	0
T50	6224	0	0	0
T51	2200648	0	0	0
T52	106800	0	0	0
T53	2866668	0	0	0
T54	312168	0	0	0
T55	109700	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5209	0	0
T10	137560	1222	0	0
T11	89592	575	0	0
T12	0	1177	0	0
T46	0	1126	0	0
T47	0	1109	0	0
T48	686484	0	0	0
T49	2463844	0	0	0
T50	6224	0	0	0
T51	2200648	0	0	0
T52	106800	0	0	0
T53	2866668	0	0	0
T54	312168	0	0	0
T55	109700	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	243272	242904	0	0
T2	1213372	1213052	0	0
T3	599556	599528	0	0
T4	3886136	3885808	0	0
T5	939576	939544	0	0
T7	1496660	1496620	0	0
T8	2393180	2392812	0	0
T18	62868	62660	0	0
T19	1962048	1961676	0	0
T20	1397632	1397396	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T5,T8
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T8

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T31,T33,T43
1	0	1	Covered	T4,T5,T8
1	1	0	Covered	T56,T34,T78
1	1	1	Covered	T33,T34,T78

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T78
0	1	Covered	T34,T80,T92
1	0	Covered	T35,T36,T62

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T33,T34,T78
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T35,T36,T62

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T78
1	0	Not Covered
1	1	Covered	T34,T80,T92

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T7,T14

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T8,T7
1	Covered	T5,T6,T17

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T43,T34,T75

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T8,T7
1	Covered	T4,T43,T58

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T5,T7,T14

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T5,T8

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T8,T16

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T6,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T13
IdleSt	175	Covered	T13
Phase0St	146	Covered	T13
Phase1St	192	Covered	T13
Phase2St	209	Covered	T13
Phase3St	227	Covered	T13
TerminalSt	243	Covered	T13
TimeoutSt	153	Covered	T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T13
IdleSt->Phase0St	146	Covered	T13
IdleSt->TimeoutSt	153	Covered	T13
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T13
Phase0St->Phase1St	192	Covered	T13
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T13
Phase1St->Phase2St	209	Covered	T13
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T13
Phase2St->Phase3St	227	Covered	T13
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T13
Phase3St->TerminalSt	243	Covered	T13
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T13
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T13
TimeoutSt->Phase0St	166	Covered	T13

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T33,T34,T78
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T34,T80,T92
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T33,T34,T78
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T33,T34,T78
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T36,T49,T105
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T5,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T5,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T40,T106,T104
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T5,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T5,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T42,T102,T107
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T5,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T5,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T43,T62,T63
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T5,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T5,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T16,T43
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	764383546	343	0	0
CheckAccumTrig0_A	764383546	577	0	0
CheckAccumTrig1_A	764383546	28	0	0
CheckClr_A	764383546	285	0	0
CheckEn_A	763938422	358510148	0	0
CheckPhase0_A	764383546	672	0	0
CheckPhase1_A	764383546	660	0	0
CheckPhase2_A	764383546	647	0	0
CheckPhase3_A	764383546	635	0	0
CheckTimeout0_A	764383546	931	0	0
CheckTimeoutSt1_A	764383546	130345	0	0
CheckTimeoutSt2_A	764383546	829	0	0
CheckTimeoutStTrig_A	764383546	74	0	0
ErrorStAllEscAsserted_A	764383546	1549	0	0
ErrorStIsTerminal_A	764383546	1279	0	0
u_state_regs_A	764383546	764198071	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	343	0	0
T10	34390	86	0	0
T11	22398	32	0	0
T12	0	62	0	0
T46	0	96	0	0
T47	0	67	0	0
T48	171621	0	0	0
T49	615961	0	0	0
T50	1556	0	0	0
T51	550162	0	0	0
T52	26700	0	0	0
T53	716667	0	0	0
T54	78042	0	0	0
T55	27425	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	577	0	0
T4	971534	1	0	0
T5	234894	1	0	0
T6	134970	1	0	0
T7	374165	1	0	0
T8	598295	1	0	0
T14	343618	1	0	0
T16	0	3	0	0
T17	0	1	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	0	0	0
T31	1274	0	0	0
T43	0	3	0	0
T56	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	28	0	0
T35	71099	1	0	0
T36	723884	1	0	0
T53	0	1	0	0
T62	0	2	0	0
T66	0	3	0	0
T69	0	1	0	0
T70	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T83	45496	0	0	0
T84	504165	0	0	0
T85	7638	0	0	0
T86	620570	0	0	0
T87	98832	0	0	0
T88	110014	0	0	0
T89	19524	0	0	0
T90	66112	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	285	0	0
T6	134970	0	0	0
T7	374165	0	0	0
T8	598295	1	0	0
T14	343618	0	0	0
T15	162005	0	0	0
T16	254279	2	0	0
T19	490512	0	0	0
T20	349408	0	0	0
T31	1274	0	0	0
T35	0	2	0	0
T36	0	3	0	0
T43	0	2	0	0
T60	0	1	0	0
T77	0	1	0	0
T81	0	1	0	0
T92	0	1	0	0
T95	0	1	0	0
T99	34594	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763938422	358510148	0	0
T1	60818	60725	0	0
T2	303343	297361	0	0
T3	149889	9443	0	0
T4	971534	9885	0	0
T5	234894	8969	0	0
T7	374165	2143	0	0
T8	598295	481007	0	0
T18	15717	15664	0	0
T19	490512	463135	0	0
T20	349408	336106	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	672	0	0
T4	971534	1	0	0
T5	234894	1	0	0
T6	134970	1	0	0
T7	374165	1	0	0
T8	598295	1	0	0
T14	343618	1	0	0
T16	0	3	0	0
T17	0	1	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	0	0	0
T31	1274	0	0	0
T43	0	3	0	0
T56	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	660	0	0
T4	971534	1	0	0
T5	234894	1	0	0
T6	134970	1	0	0
T7	374165	1	0	0
T8	598295	1	0	0
T14	343618	1	0	0
T16	0	3	0	0
T17	0	1	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	0	0	0
T31	1274	0	0	0
T43	0	3	0	0
T56	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	647	0	0
T4	971534	1	0	0
T5	234894	1	0	0
T6	134970	1	0	0
T7	374165	1	0	0
T8	598295	1	0	0
T14	343618	1	0	0
T16	0	3	0	0
T17	0	1	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	0	0	0
T31	1274	0	0	0
T43	0	3	0	0
T56	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	635	0	0
T4	971534	1	0	0
T5	234894	1	0	0
T6	134970	1	0	0
T7	374165	1	0	0
T8	598295	1	0	0
T14	343618	1	0	0
T16	0	3	0	0
T17	0	1	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	0	0	0
T31	1274	0	0	0
T43	0	2	0	0
T56	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	931	0	0
T9	666087	0	0	0
T17	269027	0	0	0
T33	120141	10	0	0
T34	636679	14	0	0
T35	0	4	0	0
T36	0	7	0	0
T43	87454	0	0	0
T60	0	2	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	0	0	0
T78	51445	5	0	0
T79	9124	0	0	0
T80	0	3	0	0
T92	0	31	0	0
T93	0	55	0	0
T95	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	130345	0	0
T9	666087	0	0	0
T17	269027	0	0	0
T33	120141	1474	0	0
T34	636679	3231	0	0
T35	0	409	0	0
T36	0	1111	0	0
T43	87454	0	0	0
T60	0	407	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	0	0	0
T78	51445	690	0	0
T79	9124	0	0	0
T80	0	187	0	0
T92	0	7094	0	0
T93	0	5952	0	0
T95	0	224	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	829	0	0
T9	666087	0	0	0
T17	269027	0	0	0
T33	120141	10	0	0
T34	636679	12	0	0
T35	0	2	0	0
T36	0	4	0	0
T43	87454	0	0	0
T60	0	1	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	0	0	0
T78	51445	5	0	0
T79	9124	0	0	0
T80	0	2	0	0
T92	0	28	0	0
T93	0	55	0	0
T95	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	74	0	0
T9	666087	0	0	0
T34	636679	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T42	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	0	0	0
T78	51445	0	0	0
T79	9124	0	0	0
T80	27585	1	0	0
T81	214115	0	0	0
T82	3202	0	0	0
T92	0	3	0	0
T101	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	1549	0	0
T10	34390	358	0	0
T11	22398	204	0	0
T12	0	359	0	0
T46	0	311	0	0
T47	0	317	0	0
T48	171621	0	0	0
T49	615961	0	0	0
T50	1556	0	0	0
T51	550162	0	0	0
T52	26700	0	0	0
T53	716667	0	0	0
T54	78042	0	0	0
T55	27425	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	1279	0	0
T10	34390	298	0	0
T11	22398	174	0	0
T12	0	299	0	0
T46	0	251	0	0
T47	0	257	0	0
T48	171621	0	0	0
T49	615961	0	0	0
T50	1556	0	0	0
T51	550162	0	0	0
T52	26700	0	0	0
T53	716667	0	0	0
T54	78042	0	0	0
T55	27425	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	764198071	0	0
T1	60818	60726	0	0
T2	303343	303263	0	0
T3	149889	149882	0	0
T4	971534	971452	0	0
T5	234894	234886	0	0
T7	374165	374155	0	0
T8	598295	598203	0	0
T18	15717	15665	0	0
T19	490512	490419	0	0
T20	349408	349349	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T18,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T18,T5

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T18,T5

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T33,T56
1	0	1	Covered	T2,T3,T18
1	1	0	Covered	T14,T33,T56
1	1	1	Covered	T33,T34,T77

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T77
0	1	Covered	T34,T77,T35
1	0	Covered	T77,T95,T108

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T33,T34,T77
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T77,T95,T108

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T77
1	0	Not Covered
1	1	Covered	T34,T77,T35

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T19
1	Covered	T18,T6,T16

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T18,T5
1	Covered	T109,T34,T77

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T18,T5
1	Covered	T58,T34,T81

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T18,T6,T16
1	Covered	T3,T5,T19

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T18,T5

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T19,T7,T56

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T5,T19,T7

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T18,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T13
IdleSt	175	Covered	T13
Phase0St	146	Covered	T13
Phase1St	192	Covered	T13
Phase2St	209	Covered	T13
Phase3St	227	Covered	T13
TerminalSt	243	Covered	T13
TimeoutSt	153	Covered	T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T13
IdleSt->Phase0St	146	Covered	T13
IdleSt->TimeoutSt	153	Covered	T13
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T13
Phase0St->Phase1St	192	Covered	T13
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T13
Phase1St->Phase2St	209	Covered	T13
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T13
Phase2St->Phase3St	227	Covered	T13
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T13
Phase3St->TerminalSt	243	Covered	T13
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T13
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T13
TimeoutSt->Phase0St	166	Covered	T13

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T33,T34,T77
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T34,T77,T35
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T33,T34,T77
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T33,T34,T78
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T110,T111,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T18,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T18,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T39,T100,T113
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T18,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T18,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T114,T115,T116
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T18,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T18,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T102,T117,T118
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T18,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T18,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T16,T34
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T18,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	764383546	304	0	0
CheckAccumTrig0_A	764383546	535	0	0
CheckAccumTrig1_A	764383546	19	0	0
CheckClr_A	764383546	261	0	0
CheckEn_A	763938422	378194220	0	0
CheckPhase0_A	764383546	626	0	0
CheckPhase1_A	764383546	617	0	0
CheckPhase2_A	764383546	604	0	0
CheckPhase3_A	764383546	591	0	0
CheckTimeout0_A	764383546	762	0	0
CheckTimeoutSt1_A	764383546	102966	0	0
CheckTimeoutSt2_A	764383546	664	0	0
CheckTimeoutStTrig_A	764383546	79	0	0
ErrorStAllEscAsserted_A	764383546	1646	0	0
ErrorStIsTerminal_A	764383546	1376	0	0
u_state_regs_A	764383546	764198071	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	304	0	0
T10	34390	82	0	0
T11	22398	39	0	0
T12	0	77	0	0
T46	0	47	0	0
T47	0	59	0	0
T48	171621	0	0	0
T49	615961	0	0	0
T50	1556	0	0	0
T51	550162	0	0	0
T52	26700	0	0	0
T53	716667	0	0	0
T54	78042	0	0	0
T55	27425	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	535	0	0
T3	149889	1	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	134970	1	0	0
T7	374165	1	0	0
T8	598295	0	0	0
T14	343618	0	0	0
T16	0	3	0	0
T18	15717	1	0	0
T19	490512	1	0	0
T20	349408	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	19	0	0
T9	666087	0	0	0
T35	71099	0	0	0
T77	120817	1	0	0
T78	51445	0	0	0
T79	9124	0	0	0
T80	27585	0	0	0
T81	214115	0	0	0
T82	3202	0	0	0
T92	312076	0	0	0
T95	104072	2	0	0
T108	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	261	0	0
T6	134970	0	0	0
T7	374165	1	0	0
T14	343618	0	0	0
T15	162005	0	0	0
T16	254279	2	0	0
T20	349408	0	0	0
T31	1274	0	0	0
T32	19531	0	0	0
T33	120141	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	0	3	0	0
T41	0	2	0	0
T92	0	1	0	0
T95	0	6	0	0
T99	34594	0	0	0
T100	0	2	0	0
T124	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763938422	378194220	0	0
T1	60818	56329	0	0
T2	303343	292006	0	0
T3	149889	599	0	0
T4	971534	971451	0	0
T5	234894	8754	0	0
T7	374165	373694	0	0
T8	598295	598202	0	0
T18	15717	2209	0	0
T19	490512	48213	0	0
T20	349408	327821	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	626	0	0
T3	149889	1	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	134970	1	0	0
T7	374165	1	0	0
T8	598295	0	0	0
T14	343618	0	0	0
T16	0	3	0	0
T18	15717	1	0	0
T19	490512	1	0	0
T20	349408	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	617	0	0
T3	149889	1	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	134970	1	0	0
T7	374165	1	0	0
T8	598295	0	0	0
T14	343618	0	0	0
T16	0	3	0	0
T18	15717	1	0	0
T19	490512	1	0	0
T20	349408	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	604	0	0
T3	149889	1	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	134970	1	0	0
T7	374165	1	0	0
T8	598295	0	0	0
T14	343618	0	0	0
T16	0	3	0	0
T18	15717	1	0	0
T19	490512	1	0	0
T20	349408	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	591	0	0
T3	149889	1	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	134970	1	0	0
T7	374165	1	0	0
T8	598295	0	0	0
T14	343618	0	0	0
T16	0	3	0	0
T18	15717	1	0	0
T19	490512	1	0	0
T20	349408	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	762	0	0
T9	666087	0	0	0
T17	269027	0	0	0
T33	120141	1	0	0
T34	636679	3	0	0
T35	0	1	0	0
T36	0	17	0	0
T43	87454	0	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	2	0	0
T78	51445	3	0	0
T79	9124	0	0	0
T80	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T98	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	102966	0	0
T9	666087	0	0	0
T17	269027	0	0	0
T33	120141	146	0	0
T34	636679	690	0	0
T35	0	471	0	0
T36	0	2390	0	0
T43	87454	0	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	544	0	0
T78	51445	400	0	0
T79	9124	0	0	0
T80	0	47	0	0
T92	0	237	0	0
T93	0	118	0	0
T98	0	140	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	664	0	0
T9	666087	0	0	0
T17	269027	0	0	0
T33	120141	1	0	0
T34	636679	1	0	0
T36	0	17	0	0
T41	0	1	0	0
T43	87454	0	0	0
T60	0	14	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	0	0	0
T78	51445	3	0	0
T79	9124	0	0	0
T80	0	1	0	0
T92	0	1	0	0
T95	0	42	0	0
T98	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	79	0	0
T9	666087	0	0	0
T34	636679	2	0	0
T35	0	1	0	0
T66	0	1	0	0
T72	0	2	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	1	0	0
T78	51445	0	0	0
T79	9124	0	0	0
T80	27585	0	0	0
T81	214115	0	0	0
T82	3202	0	0	0
T93	0	1	0	0
T100	0	2	0	0
T101	0	1	0	0
T102	0	1	0	0
T125	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	1646	0	0
T10	34390	393	0	0
T11	22398	161	0	0
T12	0	359	0	0
T46	0	378	0	0
T47	0	355	0	0
T48	171621	0	0	0
T49	615961	0	0	0
T50	1556	0	0	0
T51	550162	0	0	0
T52	26700	0	0	0
T53	716667	0	0	0
T54	78042	0	0	0
T55	27425	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	1376	0	0
T10	34390	333	0	0
T11	22398	131	0	0
T12	0	299	0	0
T46	0	318	0	0
T47	0	295	0	0
T48	171621	0	0	0
T49	615961	0	0	0
T50	1556	0	0	0
T51	550162	0	0	0
T52	26700	0	0	0
T53	716667	0	0	0
T54	78042	0	0	0
T55	27425	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	764198071	0	0
T1	60818	60726	0	0
T2	303343	303263	0	0
T3	149889	149882	0	0
T4	971534	971452	0	0
T5	234894	234886	0	0
T7	374165	374155	0	0
T8	598295	598203	0	0
T18	15717	15665	0	0
T19	490512	490419	0	0
T20	349408	349349	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T30
1	1	1	Covered	T1,T2,T5

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T32,T33
1	0	1	Covered	T2,T4,T8
1	1	0	Covered	T31,T34,T77
1	1	1	Covered	T1,T33,T34

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T33,T34
0	1	Covered	T33,T34,T78
1	0	Covered	T34,T59,T39

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T33,T34
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T34,T59,T39

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T33,T34
1	0	Not Covered
1	1	Covered	T33,T34,T78

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T19
1	Covered	T1,T8,T14

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T33,T58,T34

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T8
1	Covered	T2,T19,T7

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T5,T16,T34

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T8,T19,T7

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T5,T8

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T5

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T7,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T13
IdleSt	175	Covered	T13
Phase0St	146	Covered	T13
Phase1St	192	Covered	T13
Phase2St	209	Covered	T13
Phase3St	227	Covered	T13
TerminalSt	243	Covered	T13
TimeoutSt	153	Covered	T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T13
IdleSt->Phase0St	146	Covered	T13
IdleSt->TimeoutSt	153	Covered	T13
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T13
Phase0St->Phase1St	192	Covered	T13
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T13
Phase1St->Phase2St	209	Covered	T13
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T13
Phase2St->Phase3St	227	Covered	T13
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T13
Phase3St->TerminalSt	243	Covered	T13
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T13
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T13
TimeoutSt->Phase0St	166	Covered	T13

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T33,T34
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T33,T34,T78
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T33,T34
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T33,T34
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T39,T126,T127
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T36,T128,T129
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T101,T67,T130
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T44,T131,T53
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T34,T81,T92
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	764383546	312	0	0
CheckAccumTrig0_A	764383546	907	0	0
CheckAccumTrig1_A	764383546	51	0	0
CheckClr_A	764383546	415	0	0
CheckEn_A	763938422	244121027	0	0
CheckPhase0_A	764383546	1026	0	0
CheckPhase1_A	764383546	1007	0	0
CheckPhase2_A	764383546	992	0	0
CheckPhase3_A	764383546	976	0	0
CheckTimeout0_A	764383546	811	0	0
CheckTimeoutSt1_A	764383546	109175	0	0
CheckTimeoutSt2_A	764383546	684	0	0
CheckTimeoutStTrig_A	764383546	76	0	0
ErrorStAllEscAsserted_A	764383546	1587	0	0
ErrorStIsTerminal_A	764383546	1317	0	0
u_state_regs_A	764383546	764198071	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	312	0	0
T10	34390	85	0	0
T11	22398	30	0	0
T12	0	64	0	0
T46	0	50	0	0
T47	0	83	0	0
T48	171621	0	0	0
T49	615961	0	0	0
T50	1556	0	0	0
T51	550162	0	0	0
T52	26700	0	0	0
T53	716667	0	0	0
T54	78042	0	0	0
T55	27425	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	907	0	0
T1	60818	1	0	0
T2	303343	1	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	0	1	0	0
T7	374165	1	0	0
T8	598295	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T18	15717	0	0	0
T19	490512	1	0	0
T20	349408	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	51	0	0
T9	666087	0	0	0
T34	636679	1	0	0
T39	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T67	0	1	0	0
T72	0	1	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	0	0	0
T78	51445	0	0	0
T79	9124	0	0	0
T80	27585	0	0	0
T81	214115	0	0	0
T82	3202	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	415	0	0
T9	666087	0	0	0
T34	636679	1	0	0
T36	0	4	0	0
T59	0	1	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	0	0	0
T78	51445	0	0	0
T79	9124	0	0	0
T80	27585	0	0	0
T81	214115	1	0	0
T82	3202	0	0	0
T92	0	2	0	0
T93	0	3	0	0
T94	0	1	0	0
T95	0	2	0	0
T96	0	2	0	0
T97	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763938422	244121027	0	0
T1	60818	9818	0	0
T2	303343	14822	0	0
T3	149889	149882	0	0
T4	971534	900476	0	0
T5	234894	14533	0	0
T7	374165	2112	0	0
T8	598295	156816	0	0
T18	15717	15664	0	0
T19	490512	27009	0	0
T20	349408	28493	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	1026	0	0
T1	60818	1	0	0
T2	303343	1	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	0	1	0	0
T7	374165	1	0	0
T8	598295	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T18	15717	0	0	0
T19	490512	1	0	0
T20	349408	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	1007	0	0
T1	60818	1	0	0
T2	303343	1	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	0	1	0	0
T7	374165	1	0	0
T8	598295	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T18	15717	0	0	0
T19	490512	1	0	0
T20	349408	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	992	0	0
T1	60818	1	0	0
T2	303343	1	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	0	1	0	0
T7	374165	1	0	0
T8	598295	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T18	15717	0	0	0
T19	490512	1	0	0
T20	349408	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	976	0	0
T1	60818	1	0	0
T2	303343	1	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	0	1	0	0
T7	374165	1	0	0
T8	598295	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T18	15717	0	0	0
T19	490512	1	0	0
T20	349408	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	811	0	0
T1	60818	1	0	0
T2	303343	0	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	0	0	0
T7	374165	0	0	0
T8	598295	0	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	0	0	0
T33	0	2	0	0
T34	0	8	0	0
T36	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	6	0	0
T81	0	1	0	0
T85	0	1	0	0
T92	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	109175	0	0
T1	60818	36	0	0
T2	303343	0	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	0	0	0
T7	374165	0	0	0
T8	598295	0	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	0	0	0
T33	0	258	0	0
T34	0	1689	0	0
T36	0	90	0	0
T77	0	131	0	0
T78	0	84	0	0
T80	0	426	0	0
T81	0	29	0	0
T85	0	169	0	0
T92	0	180	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	684	0	0
T1	60818	1	0	0
T2	303343	0	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	0	0	0
T7	374165	0	0	0
T8	598295	0	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	0	0	0
T33	0	1	0	0
T34	0	4	0	0
T36	0	1	0	0
T77	0	1	0	0
T80	0	6	0	0
T81	0	1	0	0
T85	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	76	0	0
T9	666087	0	0	0
T17	269027	0	0	0
T33	120141	1	0	0
T34	636679	3	0	0
T41	0	1	0	0
T43	87454	0	0	0
T60	0	1	0	0
T62	0	2	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	0	0	0
T78	51445	1	0	0
T79	9124	0	0	0
T92	0	1	0	0
T100	0	1	0	0
T102	0	1	0	0
T104	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	1587	0	0
T10	34390	388	0	0
T11	22398	144	0	0
T12	0	330	0	0
T46	0	354	0	0
T47	0	371	0	0
T48	171621	0	0	0
T49	615961	0	0	0
T50	1556	0	0	0
T51	550162	0	0	0
T52	26700	0	0	0
T53	716667	0	0	0
T54	78042	0	0	0
T55	27425	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	1317	0	0
T10	34390	328	0	0
T11	22398	114	0	0
T12	0	270	0	0
T46	0	294	0	0
T47	0	311	0	0
T48	171621	0	0	0
T49	615961	0	0	0
T50	1556	0	0	0
T51	550162	0	0	0
T52	26700	0	0	0
T53	716667	0	0	0
T54	78042	0	0	0
T55	27425	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	764198071	0	0
T1	60818	60726	0	0
T2	303343	303263	0	0
T3	149889	149882	0	0
T4	971534	971452	0	0
T5	234894	234886	0	0
T7	374165	374155	0	0
T8	598295	598203	0	0
T18	15717	15665	0	0
T19	490512	490419	0	0
T20	349408	349349	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T5,T7
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T7

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T7

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T31,T56
1	0	1	Covered	T2,T19,T20
1	1	0	Covered	T33,T34,T77
1	1	1	Covered	T31,T34,T77

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T31,T34,T77
0	1	Covered	T31,T34,T77
1	0	Covered	T36,T60,T64

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T31,T34,T77
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T36,T60,T64

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T34,T77
1	0	Covered	T37
1	1	Covered	T31,T34,T77

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T20
1	Covered	T7,T6,T31

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T7,T20
1	Covered	T2,T14,T16

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T14
1	Covered	T5,T20,T109

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T7
1	Covered	T43,T56,T34

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T5,T6,T17

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T14,T31

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T5,T14

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T5,T7,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T13
IdleSt	175	Covered	T13
Phase0St	146	Covered	T13
Phase1St	192	Covered	T13
Phase2St	209	Covered	T13
Phase3St	227	Covered	T13
TerminalSt	243	Covered	T13
TimeoutSt	153	Covered	T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T13
IdleSt->Phase0St	146	Covered	T13
IdleSt->TimeoutSt	153	Covered	T13
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T13
Phase0St->Phase1St	192	Covered	T13
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T13
Phase1St->Phase2St	209	Covered	T13
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T13
Phase2St->Phase3St	227	Covered	T13
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T13
Phase3St->TerminalSt	243	Covered	T13
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T13
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T13
TimeoutSt->Phase0St	166	Covered	T13

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T31,T34,T77
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T31,T34,T77
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T31,T34,T77
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T34,T77,T80
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T38,T132,T74
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T5,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T5,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T39,T61,T66
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T5,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T5,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T41,T39,T45
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T5,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T5,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T45,T131,T49
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T5,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T5,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T31
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T5,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	764383546	307	0	0
CheckAccumTrig0_A	764383546	584	0	0
CheckAccumTrig1_A	764383546	31	0	0
CheckClr_A	764383546	304	0	0
CheckEn_A	763938422	352442592	0	0
CheckPhase0_A	764383546	695	0	0
CheckPhase1_A	764383546	677	0	0
CheckPhase2_A	764383546	661	0	0
CheckPhase3_A	764383546	645	0	0
CheckTimeout0_A	764383546	1102	0	0
CheckTimeoutSt1_A	764383546	154013	0	0
CheckTimeoutSt2_A	764383546	982	0	0
CheckTimeoutStTrig_A	764383546	89	0	0
ErrorStAllEscAsserted_A	764383546	1507	0	0
ErrorStIsTerminal_A	764383546	1237	0	0
u_state_regs_A	764383546	764198071	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	307	0	0
T10	34390	78	0	0
T11	22398	26	0	0
T12	0	65	0	0
T46	0	68	0	0
T47	0	70	0	0
T48	171621	0	0	0
T49	615961	0	0	0
T50	1556	0	0	0
T51	550162	0	0	0
T52	26700	0	0	0
T53	716667	0	0	0
T54	78042	0	0	0
T55	27425	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	584	0	0
T2	303343	3	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	0	1	0	0
T7	374165	1	0	0
T8	598295	0	0	0
T14	343618	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	1	0	0
T43	0	1	0	0
T56	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	31	0	0
T36	723884	1	0	0
T60	0	1	0	0
T64	0	1	0	0
T66	0	2	0	0
T68	0	2	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0
T74	0	3	0	0
T83	45496	0	0	0
T84	504165	0	0	0
T85	7638	0	0	0
T86	620570	0	0	0
T87	98832	0	0	0
T88	110014	0	0	0
T89	19524	0	0	0
T90	66112	0	0	0
T91	132845	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	304	0	0
T2	303343	2	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T7	374165	0	0	0
T8	598295	0	0	0
T14	343618	0	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	0	0	0
T31	0	1	0	0
T36	0	4	0	0
T38	0	6	0	0
T41	0	1	0	0
T56	0	1	0	0
T60	0	3	0	0
T85	0	1	0	0
T93	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763938422	352442592	0	0
T1	60818	18826	0	0
T2	303343	3593	0	0
T3	149889	149661	0	0
T4	971534	9881	0	0
T5	234894	233616	0	0
T7	374165	2127	0	0
T8	598295	598202	0	0
T18	15717	15664	0	0
T19	490512	454533	0	0
T20	349408	27233	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	695	0	0
T2	303343	3	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	0	1	0	0
T7	374165	1	0	0
T8	598295	0	0	0
T14	343618	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	1	0	0
T31	0	1	0	0
T43	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	677	0	0
T2	303343	3	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	0	1	0	0
T7	374165	1	0	0
T8	598295	0	0	0
T14	343618	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	1	0	0
T31	0	1	0	0
T43	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	661	0	0
T2	303343	3	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	0	1	0	0
T7	374165	1	0	0
T8	598295	0	0	0
T14	343618	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	1	0	0
T31	0	1	0	0
T43	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	645	0	0
T2	303343	3	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	1	0	0
T6	0	1	0	0
T7	374165	1	0	0
T8	598295	0	0	0
T14	343618	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	1	0	0
T31	0	1	0	0
T43	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	1102	0	0
T15	162005	0	0	0
T16	254279	0	0	0
T17	269027	0	0	0
T31	1274	1	0	0
T32	19531	0	0	0
T33	120141	0	0	0
T34	636679	29	0	0
T36	0	5	0	0
T43	87454	0	0	0
T60	0	3	0	0
T75	50034	0	0	0
T77	0	2	0	0
T80	0	1	0	0
T92	0	1	0	0
T93	0	8	0	0
T95	0	2	0	0
T98	0	1	0	0
T99	34594	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	154013	0	0
T15	162005	0	0	0
T16	254279	0	0	0
T17	269027	0	0	0
T31	1274	40	0	0
T32	19531	0	0	0
T33	120141	0	0	0
T34	636679	7334	0	0
T36	0	525	0	0
T43	87454	0	0	0
T60	0	318	0	0
T75	50034	0	0	0
T77	0	436	0	0
T80	0	52	0	0
T92	0	3	0	0
T93	0	1641	0	0
T95	0	390	0	0
T98	0	117	0	0
T99	34594	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	982	0	0
T9	666087	0	0	0
T34	636679	26	0	0
T36	0	4	0	0
T60	0	2	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	1	0	0
T78	51445	0	0	0
T79	9124	0	0	0
T80	27585	1	0	0
T81	214115	0	0	0
T82	3202	0	0	0
T93	0	5	0	0
T95	0	2	0	0
T96	0	4	0	0
T98	0	1	0	0
T100	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	89	0	0
T15	162005	0	0	0
T16	254279	0	0	0
T17	269027	0	0	0
T31	1274	1	0	0
T32	19531	0	0	0
T33	120141	0	0	0
T34	636679	3	0	0
T43	87454	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T75	50034	0	0	0
T77	0	1	0	0
T92	0	1	0	0
T93	0	3	0	0
T99	34594	0	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	1507	0	0
T10	34390	323	0	0
T11	22398	186	0	0
T12	0	369	0	0
T46	0	323	0	0
T47	0	306	0	0
T48	171621	0	0	0
T49	615961	0	0	0
T50	1556	0	0	0
T51	550162	0	0	0
T52	26700	0	0	0
T53	716667	0	0	0
T54	78042	0	0	0
T55	27425	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	1237	0	0
T10	34390	263	0	0
T11	22398	156	0	0
T12	0	309	0	0
T46	0	263	0	0
T47	0	246	0	0
T48	171621	0	0	0
T49	615961	0	0	0
T50	1556	0	0	0
T51	550162	0	0	0
T52	26700	0	0	0
T53	716667	0	0	0
T54	78042	0	0	0
T55	27425	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	764198071	0	0
T1	60818	60726	0	0
T2	303343	303263	0	0
T3	149889	149882	0	0
T4	971534	971452	0	0
T5	234894	234886	0	0
T7	374165	374155	0	0
T8	598295	598203	0	0
T18	15717	15665	0	0
T19	490512	490419	0	0
T20	349408	349349	0	0