Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65699091	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32172738

1

T14

212

T23

448

T24

403

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15054935	1			T14	282		T23	122		T24	409
values[0x0]	40125261	1			T14	212		T23	180		T24	105
values[0x1]	42691633	1			T14	188		T23	738		T24	89

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55762622	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42109207

1

T14

325

T23

880

T24

472

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	302512	1			T23	1		T25	210		T26	3
valid_sources[0x01]	302337	1			T23	4		T24	1		T25	245
valid_sources[0x02]	300194	1			T23	9		T24	4		T25	216
valid_sources[0x03]	579585	1			T23	1		T24	4		T25	196
valid_sources[0x04]	308228	1			T14	4		T23	2		T24	1
valid_sources[0x05]	529336	1			T23	2		T24	2		T25	239
valid_sources[0x06]	297691	1			T23	4		T24	3		T25	207
valid_sources[0x07]	308481	1			T23	2		T24	1		T25	238
valid_sources[0x08]	297521	1			T14	10		T23	5		T24	3
valid_sources[0x09]	299225	1			T23	4		T24	1		T25	213
valid_sources[0x0a]	313105	1			T14	3		T23	2		T24	2
valid_sources[0x0b]	763930	1			T14	2		T23	6		T24	1
valid_sources[0x0c]	306633	1			T14	16		T23	4		T24	4
valid_sources[0x0d]	316309	1			T23	6		T24	2		T25	210
valid_sources[0x0e]	313126	1			T23	5		T24	3		T25	197
valid_sources[0x0f]	303958	1			T23	6		T24	4		T25	225
valid_sources[0x10]	308796	1			T23	7		T24	1		T25	221
valid_sources[0x11]	903234	1			T14	4		T23	4		T24	1
valid_sources[0x12]	643301	1			T14	2		T23	4		T24	2
valid_sources[0x13]	307535	1			T23	4		T24	1		T25	206
valid_sources[0x14]	963464	1			T23	3		T24	1		T25	205
valid_sources[0x15]	291231	1			T23	1		T24	1		T25	191
valid_sources[0x16]	297522	1			T23	1		T24	2		T25	199
valid_sources[0x17]	316745	1			T23	5		T24	2		T25	214
valid_sources[0x18]	320710	1			T23	6		T24	3		T25	207
valid_sources[0x19]	306246	1			T23	7		T24	1		T25	185
valid_sources[0x1a]	301008	1			T23	10		T24	1		T25	210
valid_sources[0x1b]	307781	1			T23	3		T24	2		T25	236
valid_sources[0x1c]	293333	1			T23	2		T24	4		T25	221
valid_sources[0x1d]	333221	1			T23	5		T24	1		T25	216
valid_sources[0x1e]	293066	1			T23	2		T24	5		T25	220
valid_sources[0x1f]	303190	1			T23	4		T25	241		T26	4
valid_sources[0x20]	571025	1			T23	6		T25	227		T26	5
valid_sources[0x21]	313441	1			T14	11		T23	3		T24	3
valid_sources[0x22]	310316	1			T23	3		T25	217		T26	3
valid_sources[0x23]	800250	1			T14	5		T23	2		T25	209
valid_sources[0x24]	549312	1			T23	4		T24	1		T25	226
valid_sources[0x25]	300776	1			T23	3		T25	213		T28	262
valid_sources[0x26]	539216	1			T23	4		T24	4		T25	236
valid_sources[0x27]	291238	1			T14	6		T23	5		T24	3
valid_sources[0x28]	316875	1			T23	4		T24	1		T25	227
valid_sources[0x29]	508378	1			T14	21		T23	3		T25	243
valid_sources[0x2a]	593001	1			T23	7		T24	4		T25	221
valid_sources[0x2b]	301794	1			T23	3		T24	2		T25	216
valid_sources[0x2c]	308076	1			T14	12		T23	1		T24	5
valid_sources[0x2d]	301236	1			T14	13		T23	6		T25	197
valid_sources[0x2e]	402940	1			T23	1		T24	3		T25	231
valid_sources[0x2f]	298710	1			T14	2		T23	4		T24	4
valid_sources[0x30]	309071	1			T23	5		T24	2		T25	210
valid_sources[0x31]	300138	1			T14	2		T23	1		T24	2
valid_sources[0x32]	595094	1			T14	6		T23	3		T24	2
valid_sources[0x33]	298232	1			T14	6		T23	3		T24	2
valid_sources[0x34]	303525	1			T23	1		T24	1		T25	213
valid_sources[0x35]	304121	1			T14	4		T23	5		T24	8
valid_sources[0x36]	296386	1			T23	2		T25	209		T26	1
valid_sources[0x37]	294563	1			T23	4		T24	3		T25	214
valid_sources[0x38]	296307	1			T23	1		T24	1		T25	233
valid_sources[0x39]	295230	1			T23	5		T24	1		T25	210
valid_sources[0x3a]	305870	1			T23	9		T24	3		T25	221
valid_sources[0x3b]	292404	1			T23	4		T24	4		T25	214
valid_sources[0x3c]	300525	1			T23	4		T24	2		T25	231
valid_sources[0x3d]	296673	1			T14	2		T23	4		T24	2
valid_sources[0x3e]	305567	1			T23	1		T24	3		T25	219
valid_sources[0x3f]	307133	1			T14	6		T23	6		T24	3
valid_sources[0x40]	310454	1			T14	2		T23	8		T24	1
valid_sources[0x41]	332986	1			T14	2		T23	1		T24	2
valid_sources[0x42]	307752	1			T23	4		T24	3		T25	232
valid_sources[0x43]	330022	1			T14	2		T23	10		T25	224
valid_sources[0x44]	302382	1			T14	13		T23	4		T24	2
valid_sources[0x45]	297106	1			T14	16		T23	5		T24	3
valid_sources[0x46]	305416	1			T14	3		T23	6		T24	4
valid_sources[0x47]	301817	1			T23	8		T24	3		T25	223
valid_sources[0x48]	504634	1			T23	7		T24	1		T25	244
valid_sources[0x49]	309293	1			T23	4		T24	2		T25	223
valid_sources[0x4a]	621713	1			T23	4		T24	2		T25	251
valid_sources[0x4b]	299564	1			T23	1		T24	2		T25	216
valid_sources[0x4c]	293134	1			T14	33		T23	6		T24	2
valid_sources[0x4d]	896165	1			T14	2		T23	7		T24	4
valid_sources[0x4e]	314745	1			T23	3		T24	3		T25	225
valid_sources[0x4f]	298546	1			T23	5		T24	2		T25	221
valid_sources[0x50]	293790	1			T23	4		T24	5		T25	215
valid_sources[0x51]	302323	1			T23	9		T24	2		T25	225
valid_sources[0x52]	298564	1			T14	4		T23	3		T25	209
valid_sources[0x53]	302955	1			T23	3		T24	1		T25	231
valid_sources[0x54]	298944	1			T23	3		T24	3		T25	189
valid_sources[0x55]	298996	1			T23	2		T24	4		T25	199
valid_sources[0x56]	296811	1			T23	3		T24	5		T25	240
valid_sources[0x57]	317047	1			T14	10		T23	6		T24	1
valid_sources[0x58]	302784	1			T14	5		T23	2		T24	4
valid_sources[0x59]	307042	1			T23	7		T24	3		T25	216
valid_sources[0x5a]	297063	1			T14	4		T23	3		T25	222
valid_sources[0x5b]	300773	1			T23	6		T24	1		T25	214
valid_sources[0x5c]	303575	1			T23	5		T24	2		T25	237
valid_sources[0x5d]	303356	1			T14	3		T23	2		T24	3
valid_sources[0x5e]	307929	1			T23	1		T25	222		T26	6
valid_sources[0x5f]	321009	1			T14	13		T23	1		T24	2
valid_sources[0x60]	308892	1			T23	2		T24	6		T25	221
valid_sources[0x61]	399281	1			T23	7		T24	6		T25	226
valid_sources[0x62]	305218	1			T23	3		T24	3		T25	216
valid_sources[0x63]	975845	1			T23	3		T24	3		T25	216
valid_sources[0x64]	308998	1			T23	3		T24	3		T25	209
valid_sources[0x65]	311790	1			T23	3		T24	4		T25	211
valid_sources[0x66]	304023	1			T14	2		T23	1		T24	4
valid_sources[0x67]	301448	1			T23	3		T24	4		T25	241
valid_sources[0x68]	314417	1			T14	6		T23	6		T24	1
valid_sources[0x69]	301950	1			T14	3		T23	2		T24	3
valid_sources[0x6a]	296089	1			T23	3		T24	2		T25	220
valid_sources[0x6b]	297809	1			T23	5		T24	1		T25	244
valid_sources[0x6c]	789124	1			T14	2		T23	5		T24	4
valid_sources[0x6d]	614566	1			T23	5		T24	2		T25	213
valid_sources[0x6e]	298779	1			T14	2		T23	9		T24	8
valid_sources[0x6f]	291642	1			T23	9		T24	2		T25	238
valid_sources[0x70]	310214	1			T23	6		T24	2		T25	252
valid_sources[0x71]	303829	1			T23	8		T24	2		T25	236
valid_sources[0x72]	541879	1			T23	1		T24	2		T25	205
valid_sources[0x73]	314960	1			T23	5		T24	3		T25	217
valid_sources[0x74]	307373	1			T14	4		T23	5		T24	2
valid_sources[0x75]	343866	1			T23	6		T24	4		T25	202
valid_sources[0x76]	321604	1			T14	1		T23	4		T24	2
valid_sources[0x77]	296369	1			T23	3		T24	3		T25	219
valid_sources[0x78]	299475	1			T14	33		T23	2		T25	202
valid_sources[0x79]	303405	1			T23	5		T24	1		T25	213
valid_sources[0x7a]	299930	1			T23	5		T24	5		T25	205
valid_sources[0x7b]	413439	1			T23	4		T24	2		T25	238
valid_sources[0x7c]	332599	1			T14	6		T23	3		T24	4
valid_sources[0x7d]	298458	1			T14	2		T23	3		T24	6
valid_sources[0x7e]	297946	1			T14	31		T24	3		T25	245
valid_sources[0x7f]	308467	1			T23	4		T24	2		T25	219
valid_sources[0x80]	326108	1			T23	6		T24	2		T25	242

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7534256

1

T14

64

T23

119

T24

212

values[0x0]

all_enables

biggest_size

15497701

1

T14

98

T23

173

T24

105

values[0x1]

all_enables

biggest_size

9140781

1

T14

50

T23

156

T24

86