Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	85.19	100.00	88.89				66.67
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	88.89				66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89	100.00	88.89	100.00			66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T211,T134,T212
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14450	0	0
DisabledNoTrigBkwd_A	2147483647	744745	0	0
DisabledNoTrigFwd_A	2147483647	1601807484	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14450	0	0
T40	173541	0	0	0
T43	969982	0	0	0
T91	403844	0	0	0
T92	33524	0	0	0
T109	2786	0	0	0
T134	3774	758	0	0
T208	22049	0	0	0
T211	4577	857	0	0
T212	0	946	0	0
T213	0	405	0	0
T214	2750	507	0	0
T215	1573	745	0	0
T216	0	868	0	0
T217	0	354	0	0
T218	0	636	0	0
T219	0	393	0	0
T220	0	512	0	0
T221	0	614	0	0
T222	0	1449	0	0
T223	0	1338	0	0
T224	0	383	0	0
T225	0	1337	0	0
T226	0	654	0	0
T227	0	749	0	0
T228	0	618	0	0
T229	0	327	0	0
T230	63929	0	0	0
T231	259209	0	0	0
T232	302490	0	0	0
T233	239399	0	0	0
T234	438813	0	0	0
T235	38851	0	0	0
T236	73381	0	0	0
T237	890509	0	0	0
T238	566360	0	0	0
T239	87871	0	0	0
T240	110106	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	744745	0	0
T1	1298362	5	0	0
T2	276171	90	0	0
T3	2920044	988	0	0
T4	1319212	2071	0	0
T5	432592	2	0	0
T6	184524	218	0	0
T7	0	315	0	0
T8	0	1	0	0
T15	0	28	0	0
T16	0	222	0	0
T17	0	2	0	0
T18	143012	1	0	0
T19	778660	0	0	0
T20	64452	3	0	0
T21	286656	6	0	0
T22	4952	0	0	0
T33	603338	74	0	0
T34	0	33	0	0
T44	0	7	0	0
T57	0	10	0	0
T58	0	40	0	0
T59	0	211	0	0
T60	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1601807484	0	0
T1	2596724	1205199	0	0
T2	368228	278509	0	0
T3	2920044	1654219	0	0
T4	1319212	665996	0	0
T5	432592	224285	0	0
T18	143012	110211	0	0
T19	778660	568742	0	0
T20	64452	51287	0	0
T21	286656	218349	0	0
T22	4952	3554	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	719199704	0	0	0
DisabledNoTrigBkwd_A	719199704	261900	0	0
DisabledNoTrigFwd_A	719199704	353016454	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	261900	0	0
T2	92057	90	0	0
T3	730011	560	0	0
T4	329803	2065	0	0
T5	108148	0	0	0
T15	0	25	0	0
T18	35753	1	0	0
T19	194665	0	0	0
T20	16113	3	0	0
T21	71664	6	0	0
T22	1238	0	0	0
T33	301669	13	0	0
T34	0	3	0	0
T44	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	353016454	0	0
T1	649181	577491	0	0
T2	92057	2611	0	0
T3	730011	262807	0	0
T4	329803	5505	0	0
T5	108148	108138	0	0
T18	35753	3225	0	0
T19	194665	7402	0	0
T20	16113	3110	0	0
T21	71664	3654	0	0
T22	1238	1187	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T214,T217,T225
1	1	Covered	T3,T4,T5

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	719199704	2198	0	0
DisabledNoTrigBkwd_A	719199704	149895	0	0
DisabledNoTrigFwd_A	719199704	424004882	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	2198	0	0
T109	2786	0	0	0
T214	2750	507	0	0
T215	1573	0	0	0
T217	0	354	0	0
T225	0	1337	0	0
T234	438813	0	0	0
T235	38851	0	0	0
T236	73381	0	0	0
T237	890509	0	0	0
T238	566360	0	0	0
T239	87871	0	0	0
T240	110106	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	149895	0	0
T3	730011	304	0	0
T4	329803	6	0	0
T5	108148	1	0	0
T6	184524	218	0	0
T15	0	3	0	0
T16	0	222	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	44	0	0
T34	0	30	0	0
T44	0	4	0	0
T58	0	40	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	424004882	0	0
T1	649181	577482	0	0
T2	92057	91966	0	0
T3	730011	462884	0	0
T4	329803	328633	0	0
T5	108148	3837	0	0
T18	35753	35662	0	0
T19	194665	194577	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	586	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T19
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T211,T213,T215
1	1	Covered	T1,T3,T19

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	719199704	4757	0	0
DisabledNoTrigBkwd_A	719199704	180540	0	0
DisabledNoTrigFwd_A	719199704	410598408	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	4757	0	0
T40	173541	0	0	0
T43	969982	0	0	0
T91	403844	0	0	0
T92	33524	0	0	0
T208	22049	0	0	0
T211	4577	857	0	0
T213	0	405	0	0
T215	0	745	0	0
T218	0	636	0	0
T219	0	393	0	0
T223	0	1338	0	0
T224	0	383	0	0
T230	63929	0	0	0
T231	259209	0	0	0
T232	302490	0	0	0
T233	239399	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	180540	0	0
T1	649181	5	0	0
T2	92057	0	0	0
T3	730011	124	0	0
T4	329803	0	0	0
T5	108148	1	0	0
T7	0	315	0	0
T8	0	1	0	0
T17	0	2	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	0	17	0	0
T57	0	10	0	0
T59	0	211	0	0
T60	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	410598408	0	0
T1	649181	47870	0	0
T2	92057	91966	0	0
T3	730011	587279	0	0
T4	329803	329796	0	0
T5	108148	107994	0	0
T18	35753	35662	0	0
T19	194665	180166	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	1187	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T19,T5
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T134,T212,T216
1	1	Covered	T1,T3,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	719199704	7495	0	0
DisabledNoTrigBkwd_A	719199704	152410	0	0
DisabledNoTrigFwd_A	719199704	414187740	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	7495	0	0
T64	480364	0	0	0
T110	553087	0	0	0
T112	165962	0	0	0
T128	200089	0	0	0
T134	3774	758	0	0
T135	21133	0	0	0
T212	2064	946	0	0
T216	0	868	0	0
T220	0	512	0	0
T221	0	614	0	0
T222	0	1449	0	0
T226	0	654	0	0
T227	0	749	0	0
T228	0	618	0	0
T229	0	327	0	0
T241	472330	0	0	0
T242	29847	0	0	0
T243	950732	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	152410	0	0
T1	649181	6	0	0
T2	92057	0	0	0
T3	730011	410	0	0
T4	329803	1831	0	0
T5	108148	357	0	0
T17	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	0	53	0	0
T35	0	1	0	0
T37	0	4329	0	0
T57	0	7	0	0
T78	0	27	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	414187740	0	0
T1	649181	2356	0	0
T2	92057	91966	0	0
T3	730011	341249	0	0
T4	329803	2062	0	0
T5	108148	4316	0	0
T18	35753	35662	0	0
T19	194665	186597	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	594	0	0