Unified Coverage Report :: Module :: alert_handler_ping_timer

Module : alert_handler_ping_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.46	100.00	97.30		60.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ping_timer	99.46	100.00	97.30		100.00	100.00	100.00

---

Module Instance : tb.dut.u_ping_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.46	100.00	97.30		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.57	100.00	97.44	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_buf_spurious_alert_ping	100.00	100.00
u_prim_buf_spurious_esc_ping	100.00	100.00
u_prim_count_cnt	100.00			100.00
u_prim_count_esc_cnt	100.00			100.00
u_prim_double_lfsr	100.00	100.00	100.00	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_ping_timer

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
ALWAYS	138	4	4	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
ALWAYS	318	37	37	100.00
ALWAYS	413	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	1	1
78	1	1
79	1	1
82	1	1
83	1	1
85	1	1
96	1	1
131	1	1
138	1	1
139	1	1
141	1	1
142	1	1
			MISSING_ELSE
149	1	1
153	1	1
193	1	1
225	1	1
226	1	1
251	1	1
252	1	1
255	1	1
265	1	1
266	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
325	1	1
326	1	1
328	1	1
333	1	1
334	1	1
335	1	1
			MISSING_ELSE
340	1	1
341	1	1
342	1	1
			MISSING_ELSE
351	1	1
352	1	1
353	1	1
354	1	1
355	1	1
356	1	1
			MISSING_ELSE
			MISSING_ELSE
362	1	1
363	1	1
364	1	1
			MISSING_ELSE
371	1	1
372	1	1
373	1	1
374	1	1
375	1	1
376	1	1
377	1	1
			MISSING_ELSE
			MISSING_ELSE
386	1	1
387	1	1
399	1	1
400	1	1
401	1	1
402	1	1
			MISSING_ELSE
413	3	3

---

Cond Coverage for Module : alert_handler_ping_timer

	Total	Covered	Percent
Conditions	37	36	97.30
Logical	37	36	97.30
Non-Logical	0	0
Event	0	0

 LINE       75
 EXPRESSION ((reseed_timer_q > '0) ? ((reseed_timer_q - 1'b1)) : (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       75
 SUB-EXPRESSION (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (reseed_timer_q == '0)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       79
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       96
 EXPRESSION (reseed_en ? edn_data_i[(alert_pkg::LfsrWidth - 1):0] : '0)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (reseed_en || cnt_set)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       131
 EXPRESSION 
 Number  Term
      1  (lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts) ? ((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] - alert_pkg::NAlerts)) : lfsr_state[alert_pkg::PING_CNT_DW+:IdDw])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION ((esc_cnt >= 16'((alert_pkg::N_ESC_SEV - 1))) && esc_cnt_en)
             ----------------------1---------------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       225
 EXPRESSION (cnt == '0)
            -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       226
 EXPRESSION (wait_cnt_set || timeout_cnt_set)
             ------1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       255
 EXPRESSION (wait_cnt_set ? ((wait_cyc & wait_cyc_mask_i)) : ping_timeout_cyc_i)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       352
 EXPRESSION (timer_expired || ((|(alert_ping_ok_i & alert_ping_req_o))) || ((!id_vld)))
             ------1------    --------------------2--------------------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T4,T5
0	0	1	Covered	T5,T6,T7
0	1	0	Covered	T4,T5,T6
1	0	0	Covered	T1,T8,T9

 LINE       372
 EXPRESSION (timer_expired || ((|(esc_ping_ok_i & esc_ping_req_o))))
             ------1------    ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T9,T10

 LINE       399
 EXPRESSION (lfsr_err || cnt_error || esc_cnt_error)
             ----1---    ----2----    ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T11,T12,T13
0	1	0	Covered	T11,T12,T13
1	0	0	Covered	T11,T12,T13

---

FSM Coverage for Module : alert_handler_ping_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	10	6	60.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertPingSt	341	Covered	T14
AlertWaitSt	334	Covered	T14
EscPingSt	363	Covered	T14
EscWaitSt	353	Covered	T14
FsmErrorSt	400	Covered	T14
InitSt	332	Covered	T14

transitions	Line No.	Covered	Tests
AlertPingSt->EscWaitSt	353	Covered	T14
AlertPingSt->FsmErrorSt	400	Not Covered
AlertWaitSt->AlertPingSt	341	Covered	T14
AlertWaitSt->FsmErrorSt	400	Covered	T14
EscPingSt->AlertWaitSt	373	Covered	T14
EscPingSt->FsmErrorSt	400	Not Covered
EscWaitSt->EscPingSt	363	Covered	T14
EscWaitSt->FsmErrorSt	400	Not Covered
InitSt->AlertWaitSt	334	Covered	T14
InitSt->FsmErrorSt	400	Not Covered

---

Branch Coverage for Module : alert_handler_ping_timer

	Line No.	Total	Covered	Percent
Branches		32	32	100.00
TERNARY	75	3	3	100.00
TERNARY	96	2	2	100.00
TERNARY	131	2	2	100.00
TERNARY	255	2	2	100.00
IF	82	2	2	100.00
IF	138	3	3	100.00
CASE	328	14	14	100.00
IF	399	2	2	100.00
IF	413	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((reseed_timer_q > '0)) ? 
-2-:	75	(reseed_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	(reseed_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	131	((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	255	(wait_cnt_set) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	if ((!rst_ni))
-2-:	141	if (cnt_set)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	328	case (state_q)
-2-:	333	if (en_i)
-3-:	340	if (timer_expired)
-4-:	352	if (((timer_expired || (|(alert_ping_ok_i & alert_ping_req_o))) || (!id_vld)))
-5-:	355	if (timer_expired)
-6-:	362	if (timer_expired)
-7-:	372	if ((timer_expired || (|(esc_ping_ok_i & esc_ping_req_o))))
-8-:	376	if (timer_expired)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
InitSt	1	-	-	-	-	-	-	Covered	T1,T4,T5
InitSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
AlertWaitSt	-	1	-	-	-	-	-	Covered	T1,T4,T5
AlertWaitSt	-	0	-	-	-	-	-	Covered	T1,T4,T5
AlertPingSt	-	-	1	1	-	-	-	Covered	T1,T8,T9
AlertPingSt	-	-	1	0	-	-	-	Covered	T4,T5,T6
AlertPingSt	-	-	0	-	-	-	-	Covered	T1,T4,T5
EscWaitSt	-	-	-	-	1	-	-	Covered	T1,T4,T5
EscWaitSt	-	-	-	-	0	-	-	Covered	T1,T4,T5
EscPingSt	-	-	-	-	-	1	1	Covered	T1,T9,T10
EscPingSt	-	-	-	-	-	1	0	Covered	T1,T4,T5
EscPingSt	-	-	-	-	-	0	-	Covered	T1,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	399	if (((lfsr_err || cnt_error) || esc_cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	413	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_ping_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertPingOH_A	719199704	172548	0	0
EscPingOH_A	719199704	116318	0	0
MaxIdDw_A	643	643	0	0
PingOH0_A	719199704	719026279	0	0
WaitCycMaskIsRightAlignedMask_A	719199704	719026279	0	0
WaitCycMaskMin_A	719199704	719026279	0	0
u_state_regs_A	719199704	719026279	0	0

AlertPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	172548	0	0
T1	649181	1250	0	0
T2	92057	0	0	0
T3	730011	0	0	0
T4	329803	317	0	0
T5	108148	20	0	0
T6	0	29	0	0
T7	0	21	0	0
T8	0	316	0	0
T9	0	863	0	0
T15	0	609	0	0
T16	0	15	0	0
T17	0	45	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0

EscPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	116318	0	0
T1	649181	525	0	0
T2	92057	0	0	0
T3	730011	0	0	0
T4	329803	235	0	0
T5	108148	80	0	0
T6	0	140	0	0
T7	0	135	0	0
T8	0	95	0	0
T9	0	663	0	0
T15	0	415	0	0
T16	0	60	0	0
T17	0	175	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0

MaxIdDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643	643	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

PingOH0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	719026279	0	0
T1	649181	649092	0	0
T2	92057	91966	0	0
T3	730011	729321	0	0
T4	329803	329796	0	0
T5	108148	108138	0	0
T18	35753	35662	0	0
T19	194665	194577	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	1187	0	0

WaitCycMaskIsRightAlignedMask_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	719026279	0	0
T1	649181	649092	0	0
T2	92057	91966	0	0
T3	730011	729321	0	0
T4	329803	329796	0	0
T5	108148	108138	0	0
T18	35753	35662	0	0
T19	194665	194577	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	1187	0	0

WaitCycMaskMin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	719026279	0	0
T1	649181	649092	0	0
T2	92057	91966	0	0
T3	730011	729321	0	0
T4	329803	329796	0	0
T5	108148	108138	0	0
T18	35753	35662	0	0
T19	194665	194577	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	1187	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	719026279	0	0
T1	649181	649092	0	0
T2	92057	91966	0	0
T3	730011	729321	0	0
T4	329803	329796	0	0
T5	108148	108138	0	0
T18	35753	35662	0	0
T19	194665	194577	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	1187	0	0

Line Coverage for Instance : tb.dut.u_ping_timer

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
ALWAYS	138	4	4	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
ALWAYS	318	37	37	100.00
ALWAYS	413	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	1	1
78	1	1
79	1	1
82	1	1
83	1	1
85	1	1
96	1	1
131	1	1
138	1	1
139	1	1
141	1	1
142	1	1
			MISSING_ELSE
149	1	1
153	1	1
193	1	1
225	1	1
226	1	1
251	1	1
252	1	1
255	1	1
265	1	1
266	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
325	1	1
326	1	1
328	1	1
333	1	1
334	1	1
335	1	1
			MISSING_ELSE
340	1	1
341	1	1
342	1	1
			MISSING_ELSE
351	1	1
352	1	1
353	1	1
354	1	1
355	1	1
356	1	1
			MISSING_ELSE
			MISSING_ELSE
362	1	1
363	1	1
364	1	1
			MISSING_ELSE
371	1	1
372	1	1
373	1	1
374	1	1
375	1	1
376	1	1
377	1	1
			MISSING_ELSE
			MISSING_ELSE
386	1	1
387	1	1
399	1	1
400	1	1
401	1	1
402	1	1
			MISSING_ELSE
413	3	3

---

Cond Coverage for Instance : tb.dut.u_ping_timer

	Total	Covered	Percent
Conditions	37	36	97.30
Logical	37	36	97.30
Non-Logical	0	0
Event	0	0

 LINE       75
 EXPRESSION ((reseed_timer_q > '0) ? ((reseed_timer_q - 1'b1)) : (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       75
 SUB-EXPRESSION (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (reseed_timer_q == '0)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       79
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       96
 EXPRESSION (reseed_en ? edn_data_i[(alert_pkg::LfsrWidth - 1):0] : '0)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (reseed_en || cnt_set)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       131
 EXPRESSION 
 Number  Term
      1  (lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts) ? ((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] - alert_pkg::NAlerts)) : lfsr_state[alert_pkg::PING_CNT_DW+:IdDw])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION ((esc_cnt >= 16'((alert_pkg::N_ESC_SEV - 1))) && esc_cnt_en)
             ----------------------1---------------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       225
 EXPRESSION (cnt == '0)
            -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       226
 EXPRESSION (wait_cnt_set || timeout_cnt_set)
             ------1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       255
 EXPRESSION (wait_cnt_set ? ((wait_cyc & wait_cyc_mask_i)) : ping_timeout_cyc_i)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       352
 EXPRESSION (timer_expired || ((|(alert_ping_ok_i & alert_ping_req_o))) || ((!id_vld)))
             ------1------    --------------------2--------------------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T4,T5
0	0	1	Covered	T5,T6,T7
0	1	0	Covered	T4,T5,T6
1	0	0	Covered	T1,T8,T9

 LINE       372
 EXPRESSION (timer_expired || ((|(esc_ping_ok_i & esc_ping_req_o))))
             ------1------    ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T9,T10

 LINE       399
 EXPRESSION (lfsr_err || cnt_error || esc_cnt_error)
             ----1---    ----2----    ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T11,T12,T13
0	1	0	Covered	T11,T12,T13
1	0	0	Covered	T11,T12,T13

---

FSM Coverage for Instance : tb.dut.u_ping_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertPingSt	341	Covered	T14
AlertWaitSt	334	Covered	T14
EscPingSt	363	Covered	T14
EscWaitSt	353	Covered	T14
FsmErrorSt	400	Covered	T14
InitSt	332	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
AlertPingSt->EscWaitSt	353	Covered	T14
AlertPingSt->FsmErrorSt	400	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
AlertWaitSt->AlertPingSt	341	Covered	T14
AlertWaitSt->FsmErrorSt	400	Covered	T14
EscPingSt->AlertWaitSt	373	Covered	T14
EscPingSt->FsmErrorSt	400	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
EscWaitSt->EscPingSt	363	Covered	T14
EscWaitSt->FsmErrorSt	400	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
InitSt->AlertWaitSt	334	Covered	T14
InitSt->FsmErrorSt	400	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.

---

Branch Coverage for Instance : tb.dut.u_ping_timer

	Line No.	Total	Covered	Percent
Branches		32	32	100.00
TERNARY	75	3	3	100.00
TERNARY	96	2	2	100.00
TERNARY	131	2	2	100.00
TERNARY	255	2	2	100.00
IF	82	2	2	100.00
IF	138	3	3	100.00
CASE	328	14	14	100.00
IF	399	2	2	100.00
IF	413	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((reseed_timer_q > '0)) ? 
-2-:	75	(reseed_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	(reseed_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	131	((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	255	(wait_cnt_set) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	if ((!rst_ni))
-2-:	141	if (cnt_set)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	328	case (state_q)
-2-:	333	if (en_i)
-3-:	340	if (timer_expired)
-4-:	352	if (((timer_expired || (|(alert_ping_ok_i & alert_ping_req_o))) || (!id_vld)))
-5-:	355	if (timer_expired)
-6-:	362	if (timer_expired)
-7-:	372	if ((timer_expired || (|(esc_ping_ok_i & esc_ping_req_o))))
-8-:	376	if (timer_expired)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
InitSt	1	-	-	-	-	-	-	Covered	T1,T4,T5
InitSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
AlertWaitSt	-	1	-	-	-	-	-	Covered	T1,T4,T5
AlertWaitSt	-	0	-	-	-	-	-	Covered	T1,T4,T5
AlertPingSt	-	-	1	1	-	-	-	Covered	T1,T8,T9
AlertPingSt	-	-	1	0	-	-	-	Covered	T4,T5,T6
AlertPingSt	-	-	0	-	-	-	-	Covered	T1,T4,T5
EscWaitSt	-	-	-	-	1	-	-	Covered	T1,T4,T5
EscWaitSt	-	-	-	-	0	-	-	Covered	T1,T4,T5
EscPingSt	-	-	-	-	-	1	1	Covered	T1,T9,T10
EscPingSt	-	-	-	-	-	1	0	Covered	T1,T4,T5
EscPingSt	-	-	-	-	-	0	-	Covered	T1,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	399	if (((lfsr_err || cnt_error) || esc_cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	413	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_ping_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertPingOH_A	719199704	172548	0	0
EscPingOH_A	719199704	116318	0	0
MaxIdDw_A	643	643	0	0
PingOH0_A	719199704	719026279	0	0
WaitCycMaskIsRightAlignedMask_A	719199704	719026279	0	0
WaitCycMaskMin_A	719199704	719026279	0	0
u_state_regs_A	719199704	719026279	0	0

AlertPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	172548	0	0
T1	649181	1250	0	0
T2	92057	0	0	0
T3	730011	0	0	0
T4	329803	317	0	0
T5	108148	20	0	0
T6	0	29	0	0
T7	0	21	0	0
T8	0	316	0	0
T9	0	863	0	0
T15	0	609	0	0
T16	0	15	0	0
T17	0	45	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0

EscPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	116318	0	0
T1	649181	525	0	0
T2	92057	0	0	0
T3	730011	0	0	0
T4	329803	235	0	0
T5	108148	80	0	0
T6	0	140	0	0
T7	0	135	0	0
T8	0	95	0	0
T9	0	663	0	0
T15	0	415	0	0
T16	0	60	0	0
T17	0	175	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0

MaxIdDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643	643	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

PingOH0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	719026279	0	0
T1	649181	649092	0	0
T2	92057	91966	0	0
T3	730011	729321	0	0
T4	329803	329796	0	0
T5	108148	108138	0	0
T18	35753	35662	0	0
T19	194665	194577	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	1187	0	0

WaitCycMaskIsRightAlignedMask_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	719026279	0	0
T1	649181	649092	0	0
T2	92057	91966	0	0
T3	730011	729321	0	0
T4	329803	329796	0	0
T5	108148	108138	0	0
T18	35753	35662	0	0
T19	194665	194577	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	1187	0	0

WaitCycMaskMin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	719026279	0	0
T1	649181	649092	0	0
T2	92057	91966	0	0
T3	730011	729321	0	0
T4	329803	329796	0	0
T5	108148	108138	0	0
T18	35753	35662	0	0
T19	194665	194577	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	1187	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	719026279	0	0
T1	649181	649092	0	0
T2	92057	91966	0	0
T3	730011	729321	0	0
T4	329803	329796	0	0
T5	108148	108138	0	0
T18	35753	35662	0	0
T19	194665	194577	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	1187	0	0