Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T32
1	1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T20
1	0	1	Covered	T3,T4,T19
1	1	0	Covered	T3,T33,T15
1	1	1	Covered	T3,T33,T15

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T33,T15
0	1	Covered	T33,T34,T35
1	0	Covered	T15,T36,T37

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T33,T15
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T15,T36,T37

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T33,T15
1	0	Covered	T38
1	1	Covered	T33,T34,T35

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T20,T5

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T2,T3,T4

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T3,T4

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T33

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T18,T20

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T20,T21

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Not Covered
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Not Covered
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Not Covered
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Not Covered
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Not Covered
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Not Covered
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T33,T15,T34
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T39,T40,T41
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T39,T42,T43
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T44,T45,T43
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T44,T39
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T18,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1178	0	0
CheckAccumTrig0_A	2147483647	2600	0	0
CheckAccumTrig1_A	2147483647	138	0	0
CheckClr_A	2147483647	1271	0	0
CheckEn_A	2147483647	1236190898	0	0
CheckPhase0_A	2147483647	2992	0	0
CheckPhase1_A	2147483647	2928	0	0
CheckPhase2_A	2147483647	2862	0	0
CheckPhase3_A	2147483647	2796	0	0
CheckTimeout0_A	2147483647	6282	0	0
CheckTimeoutSt1_A	2147483647	585577	0	0
CheckTimeoutSt2_A	2147483647	5846	0	0
CheckTimeoutStTrig_A	2147483647	296	0	0
ErrorStAllEscAsserted_A	2147483647	5771	0	0
ErrorStIsTerminal_A	2147483647	4811	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1178	0	0
T11	152604	280	0	0
T12	0	318	0	0
T13	0	122	0	0
T46	0	284	0	0
T47	0	174	0	0
T48	71308	0	0	0
T49	2159176	0	0	0
T50	62644	0	0	0
T51	28940	0	0	0
T52	1102176	0	0	0
T53	47888	0	0	0
T54	328052	0	0	0
T55	39512	0	0	0
T56	135412	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2600	0	0
T1	1298362	1	0	0
T2	276171	1	0	0
T3	2920044	14	0	0
T4	1319212	2	0	0
T5	432592	2	0	0
T6	184524	1	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	143012	1	0	0
T19	778660	0	0	0
T20	64452	3	0	0
T21	286656	1	0	0
T22	4952	0	0	0
T33	603338	11	0	0
T34	0	1	0	0
T39	0	13	0	0
T44	0	3	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	138	0	0
T15	542022	1	0	0
T34	16175	0	0	0
T36	49226	1	0	0
T37	1765768	1	0	0
T40	0	1	0	0
T49	539794	1	0	0
T60	277106	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	379836	2	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	9153	0	0	0
T78	70203	0	0	0
T79	59118	0	0	0
T80	646864	0	0	0
T81	238066	0	0	0
T82	391268	0	0	0
T83	288640	0	0	0
T84	236744	0	0	0
T85	222324	0	0	0
T86	151456	0	0	0
T87	21413	0	0	0
T88	27591	0	0	0
T89	119045	0	0	0
T90	8083	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1271	0	0
T3	1460022	4	0	0
T4	989409	0	0	0
T5	432592	1	0	0
T6	738096	0	0	0
T17	0	1	0	0
T18	143012	1	0	0
T19	778660	0	0	0
T20	64452	3	0	0
T21	286656	0	0	0
T22	4952	0	0	0
T33	1206676	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	3	0	0
T39	0	17	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	17184	2	0	0
T45	0	11	0	0
T57	16768	1	0	0
T60	0	4	0	0
T62	0	3	0	0
T82	0	2	0	0
T91	0	2	0	0
T92	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1236190898	0	0
T1	2596724	1205197	0	0
T2	368228	278506	0	0
T3	2920044	1643078	0	0
T4	1319212	339403	0	0
T5	432592	224284	0	0
T18	143012	110208	0	0
T19	778660	568739	0	0
T20	64452	51284	0	0
T21	286656	218346	0	0
T22	4952	3552	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2992	0	0
T1	1298362	1	0	0
T2	276171	1	0	0
T3	2920044	14	0	0
T4	1319212	2	0	0
T5	432592	2	0	0
T6	184524	1	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	2	0	0
T18	143012	1	0	0
T19	778660	0	0	0
T20	64452	3	0	0
T21	286656	1	0	0
T22	4952	0	0	0
T33	603338	12	0	0
T34	0	3	0	0
T35	0	2	0	0
T44	0	3	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2928	0	0
T1	1298362	1	0	0
T2	276171	1	0	0
T3	2920044	14	0	0
T4	1319212	2	0	0
T5	432592	2	0	0
T6	184524	1	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	2	0	0
T18	143012	1	0	0
T19	778660	0	0	0
T20	64452	3	0	0
T21	286656	1	0	0
T22	4952	0	0	0
T33	603338	12	0	0
T34	0	3	0	0
T35	0	2	0	0
T44	0	3	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2862	0	0
T1	1298362	1	0	0
T2	276171	1	0	0
T3	2920044	14	0	0
T4	1319212	2	0	0
T5	432592	2	0	0
T6	184524	1	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	0	2	0	0
T18	143012	1	0	0
T19	778660	0	0	0
T20	64452	3	0	0
T21	286656	1	0	0
T22	4952	0	0	0
T33	603338	12	0	0
T34	0	3	0	0
T35	0	2	0	0
T44	0	2	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2796	0	0
T1	1298362	1	0	0
T2	276171	1	0	0
T3	2920044	14	0	0
T4	1319212	2	0	0
T5	432592	2	0	0
T6	184524	1	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	0	2	0	0
T18	143012	1	0	0
T19	778660	0	0	0
T20	64452	2	0	0
T21	286656	1	0	0
T22	4952	0	0	0
T33	603338	12	0	0
T34	0	3	0	0
T35	0	2	0	0
T44	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6282	0	0
T3	2920044	28	0	0
T4	1319212	0	0	0
T5	432592	0	0	0
T6	738096	0	0	0
T15	0	2	0	0
T18	143012	0	0	0
T19	778660	0	0	0
T20	64452	0	0	0
T21	286656	0	0	0
T22	4952	0	0	0
T33	1206676	22	0	0
T34	0	8	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	5	0	0
T49	0	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	4	0	0
T77	0	7	0	0
T81	0	15	0	0
T82	0	18	0	0
T93	0	2	0	0
T94	0	1	0	0
T95	0	2	0	0
T96	0	1	0	0
T97	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	585577	0	0
T3	2920044	2137	0	0
T4	1319212	0	0	0
T5	432592	0	0	0
T6	738096	0	0	0
T15	0	204	0	0
T18	143012	0	0	0
T19	778660	0	0	0
T20	64452	0	0	0
T21	286656	0	0	0
T22	4952	0	0	0
T33	1206676	2441	0	0
T34	0	1987	0	0
T35	0	503	0	0
T37	0	218	0	0
T49	0	111	0	0
T53	0	274	0	0
T54	0	130	0	0
T55	0	255	0	0
T77	0	437	0	0
T81	0	2997	0	0
T82	0	3020	0	0
T93	0	223	0	0
T94	0	106	0	0
T95	0	1085	0	0
T96	0	337	0	0
T97	0	848	0	0
T98	0	86	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5846	0	0
T3	2920044	28	0	0
T4	1319212	0	0	0
T5	432592	0	0	0
T6	738096	0	0	0
T15	0	1	0	0
T18	143012	0	0	0
T19	778660	0	0	0
T20	64452	0	0	0
T21	286656	0	0	0
T22	4952	0	0	0
T33	1206676	20	0	0
T34	0	4	0	0
T35	0	1	0	0
T37	0	3	0	0
T49	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	5	0	0
T62	0	19	0	0
T77	0	6	0	0
T81	0	13	0	0
T82	0	18	0	0
T93	0	2	0	0
T94	0	1	0	0
T95	0	2	0	0
T97	0	2	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	296	0	0
T6	184524	0	0	0
T7	157956	0	0	0
T8	128860	0	0	0
T15	542022	0	0	0
T33	301669	2	0	0
T34	32350	4	0	0
T35	24303	2	0	0
T40	173541	3	0	0
T41	0	5	0	0
T43	969982	0	0	0
T44	8592	0	0	0
T55	0	1	0	0
T57	16768	0	0	0
T58	205605	0	0	0
T59	580397	0	0	0
T62	0	5	0	0
T77	0	1	0	0
T81	119033	2	0	0
T82	195634	0	0	0
T83	144320	0	0	0
T84	236744	0	0	0
T91	403844	5	0	0
T92	33524	1	0	0
T96	0	1	0	0
T97	0	3	0	0
T99	61163	1	0	0
T101	0	3	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	2	0	0
T105	0	2	0	0
T106	0	1	0	0
T107	0	3	0	0
T108	49753	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5771	0	0
T11	152604	1442	0	0
T12	0	1432	0	0
T13	0	723	0	0
T46	0	1450	0	0
T47	0	724	0	0
T48	71308	0	0	0
T49	2159176	0	0	0
T50	62644	0	0	0
T51	28940	0	0	0
T52	1102176	0	0	0
T53	47888	0	0	0
T54	328052	0	0	0
T55	39512	0	0	0
T56	135412	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4811	0	0
T11	152604	1202	0	0
T12	0	1192	0	0
T13	0	603	0	0
T46	0	1210	0	0
T47	0	604	0	0
T48	71308	0	0	0
T49	2159176	0	0	0
T50	62644	0	0	0
T51	28940	0	0	0
T52	1102176	0	0	0
T53	47888	0	0	0
T54	328052	0	0	0
T55	39512	0	0	0
T56	135412	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2596724	2596368	0	0
T2	368228	367864	0	0
T3	2920044	2917284	0	0
T4	1319212	1319184	0	0
T5	432592	432552	0	0
T18	143012	142648	0	0
T19	778660	778308	0	0
T20	64452	64236	0	0
T21	286656	286260	0	0
T22	4952	4748	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T22,T33
1	0	1	Covered	T3,T4,T6
1	1	0	Covered	T3,T33,T15
1	1	1	Covered	T3,T33,T15

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T33,T15
0	1	Covered	T34,T81,T99
1	0	Covered	T15,T37,T49

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T33,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T37,T49

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T33,T15
1	0	Not Covered
1	1	Covered	T34,T81,T99

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T6,T44,T80

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T33
1	Covered	T4,T33,T58

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T33,T34

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T33
1	Covered	T3,T5,T44

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T33,T44,T58

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T44,T16

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T33

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T5,T33

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T34,T37
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T34
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T39,T40,T109
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T39,T105,T110
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T43,T111,T112
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T44,T39,T62
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T33,T34
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	719199704	294	0	0
CheckAccumTrig0_A	719199704	542	0	0
CheckAccumTrig1_A	719199704	29	0	0
CheckClr_A	719199704	265	0	0
CheckEn_A	719042364	336668720	0	0
CheckPhase0_A	719199704	626	0	0
CheckPhase1_A	719199704	611	0	0
CheckPhase2_A	719199704	590	0	0
CheckPhase3_A	719199704	575	0	0
CheckTimeout0_A	719199704	1247	0	0
CheckTimeoutSt1_A	719199704	143434	0	0
CheckTimeoutSt2_A	719199704	1156	0	0
CheckTimeoutStTrig_A	719199704	62	0	0
ErrorStAllEscAsserted_A	719199704	1394	0	0
ErrorStIsTerminal_A	719199704	1154	0	0
u_state_regs_A	719199704	719026279	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	294	0	0
T11	38151	63	0	0
T12	0	91	0	0
T13	0	17	0	0
T46	0	77	0	0
T47	0	46	0	0
T48	17827	0	0	0
T49	539794	0	0	0
T50	15661	0	0	0
T51	7235	0	0	0
T52	275544	0	0	0
T53	11972	0	0	0
T54	82013	0	0	0
T55	9878	0	0	0
T56	33853	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	542	0	0
T3	730011	6	0	0
T4	329803	1	0	0
T5	108148	1	0	0
T6	184524	1	0	0
T16	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	4	0	0
T39	0	13	0	0
T44	0	2	0	0
T58	0	1	0	0
T60	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	29	0	0
T15	542022	1	0	0
T34	16175	0	0	0
T37	882884	1	0	0
T40	0	1	0	0
T49	539794	1	0	0
T64	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T79	29559	0	0	0
T80	323432	0	0	0
T81	119033	0	0	0
T82	195634	0	0	0
T83	144320	0	0	0
T84	236744	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	265	0	0
T3	730011	3	0	0
T4	329803	0	0	0
T5	108148	0	0	0
T6	184524	0	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	1	0	0
T34	0	2	0	0
T39	0	12	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T62	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719042364	336668720	0	0
T1	649181	577481	0	0
T2	92057	91965	0	0
T3	730011	462880	0	0
T4	329803	2040	0	0
T5	108148	3837	0	0
T18	35753	35661	0	0
T19	194665	194576	0	0
T20	16113	16058	0	0
T21	71664	71564	0	0
T22	1238	586	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	626	0	0
T3	730011	6	0	0
T4	329803	1	0	0
T5	108148	1	0	0
T6	184524	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	4	0	0
T34	0	2	0	0
T44	0	2	0	0
T58	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	611	0	0
T3	730011	6	0	0
T4	329803	1	0	0
T5	108148	1	0	0
T6	184524	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	4	0	0
T34	0	2	0	0
T44	0	2	0	0
T58	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	590	0	0
T3	730011	6	0	0
T4	329803	1	0	0
T5	108148	1	0	0
T6	184524	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	4	0	0
T34	0	2	0	0
T44	0	2	0	0
T58	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	575	0	0
T3	730011	6	0	0
T4	329803	1	0	0
T5	108148	1	0	0
T6	184524	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	4	0	0
T34	0	2	0	0
T44	0	1	0	0
T58	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1247	0	0
T3	730011	13	0	0
T4	329803	0	0	0
T5	108148	0	0	0
T6	184524	0	0	0
T15	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	13	0	0
T34	0	4	0	0
T37	0	2	0	0
T49	0	2	0	0
T77	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T93	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	143434	0	0
T3	730011	1110	0	0
T4	329803	0	0	0
T5	108148	0	0	0
T6	184524	0	0	0
T15	0	3	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	1545	0	0
T34	0	832	0	0
T37	0	87	0	0
T49	0	111	0	0
T77	0	98	0	0
T81	0	62	0	0
T82	0	177	0	0
T93	0	223	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1156	0	0
T3	730011	13	0	0
T4	329803	0	0	0
T5	108148	0	0	0
T6	184524	0	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	13	0	0
T34	0	2	0	0
T37	0	1	0	0
T49	0	1	0	0
T55	0	2	0	0
T77	0	1	0	0
T82	0	1	0	0
T93	0	2	0	0
T99	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	62	0	0
T34	16175	2	0	0
T40	173541	1	0	0
T43	969982	0	0	0
T81	119033	1	0	0
T82	195634	0	0	0
T83	144320	0	0	0
T84	236744	0	0	0
T91	403844	2	0	0
T92	33524	1	0	0
T99	61163	1	0	0
T101	0	3	0	0
T102	0	1	0	0
T104	0	1	0	0
T107	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1394	0	0
T11	38151	339	0	0
T12	0	334	0	0
T13	0	180	0	0
T46	0	364	0	0
T47	0	177	0	0
T48	17827	0	0	0
T49	539794	0	0	0
T50	15661	0	0	0
T51	7235	0	0	0
T52	275544	0	0	0
T53	11972	0	0	0
T54	82013	0	0	0
T55	9878	0	0	0
T56	33853	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1154	0	0
T11	38151	279	0	0
T12	0	274	0	0
T13	0	150	0	0
T46	0	304	0	0
T47	0	147	0	0
T48	17827	0	0	0
T49	539794	0	0	0
T50	15661	0	0	0
T51	7235	0	0	0
T52	275544	0	0	0
T53	11972	0	0	0
T54	82013	0	0	0
T55	9878	0	0	0
T56	33853	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	719026279	0	0
T1	649181	649092	0	0
T2	92057	91966	0	0
T3	730011	729321	0	0
T4	329803	329796	0	0
T5	108148	108138	0	0
T18	35753	35662	0	0
T19	194665	194577	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	1187	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T22,T33
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T3,T33,T15
1	1	1	Covered	T3,T33,T15

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T33,T15
0	1	Covered	T33,T34,T77
1	0	Covered	T37,T63,T64

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T33,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T37,T63,T64

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T33,T15
1	0	Not Covered
1	1	Covered	T33,T34,T77

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T5,T33,T57

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T33
1	Covered	T1,T3,T4

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T33,T78,T83

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T5,T35

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T33

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T5,T33,T17

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T33,T34,T77
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T99,T111
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T113,T114,T115
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T55,T100,T116
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T41,T117,T118
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T34
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	719199704	361	0	0
CheckAccumTrig0_A	719199704	555	0	0
CheckAccumTrig1_A	719199704	31	0	0
CheckClr_A	719199704	271	0	0
CheckEn_A	719042364	310366152	0	0
CheckPhase0_A	719199704	649	0	0
CheckPhase1_A	719199704	639	0	0
CheckPhase2_A	719199704	625	0	0
CheckPhase3_A	719199704	617	0	0
CheckTimeout0_A	719199704	1960	0	0
CheckTimeoutSt1_A	719199704	180220	0	0
CheckTimeoutSt2_A	719199704	1853	0	0
CheckTimeoutStTrig_A	719199704	76	0	0
ErrorStAllEscAsserted_A	719199704	1482	0	0
ErrorStIsTerminal_A	719199704	1242	0	0
u_state_regs_A	719199704	719026279	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	361	0	0
T11	38151	51	0	0
T12	0	90	0	0
T13	0	57	0	0
T46	0	107	0	0
T47	0	56	0	0
T48	17827	0	0	0
T49	539794	0	0	0
T50	15661	0	0	0
T51	7235	0	0	0
T52	275544	0	0	0
T53	11972	0	0	0
T54	82013	0	0	0
T55	9878	0	0	0
T56	33853	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	555	0	0
T1	649181	1	0	0
T2	92057	0	0	0
T3	730011	2	0	0
T4	329803	2	0	0
T5	108148	2	0	0
T17	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	0	4	0	0
T35	0	1	0	0
T57	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	31	0	0
T37	882884	1	0	0
T63	379836	1	0	0
T64	0	2	0	0
T69	0	1	0	0
T76	0	3	0	0
T79	29559	0	0	0
T80	323432	0	0	0
T81	119033	0	0	0
T82	195634	0	0	0
T83	144320	0	0	0
T84	236744	0	0	0
T85	222324	0	0	0
T86	151456	0	0	0
T110	0	1	0	0
T118	0	2	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	271	0	0
T4	329803	1	0	0
T5	108148	1	0	0
T6	184524	0	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T44	8592	0	0	0
T55	0	1	0	0
T77	0	1	0	0
T91	0	1	0	0
T99	0	6	0	0
T100	0	1	0	0
T122	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719042364	310366152	0	0
T1	649181	2356	0	0
T2	92057	91965	0	0
T3	730011	341244	0	0
T4	329803	2062	0	0
T5	108148	4316	0	0
T18	35753	35661	0	0
T19	194665	186596	0	0
T20	16113	16058	0	0
T21	71664	71564	0	0
T22	1238	594	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	649	0	0
T1	649181	1	0	0
T2	92057	0	0	0
T3	730011	2	0	0
T4	329803	2	0	0
T5	108148	2	0	0
T17	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	0	5	0	0
T34	0	1	0	0
T35	0	1	0	0
T57	0	1	0	0
T77	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	639	0	0
T1	649181	1	0	0
T2	92057	0	0	0
T3	730011	2	0	0
T4	329803	2	0	0
T5	108148	2	0	0
T17	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	0	5	0	0
T34	0	1	0	0
T35	0	1	0	0
T57	0	1	0	0
T77	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	625	0	0
T1	649181	1	0	0
T2	92057	0	0	0
T3	730011	2	0	0
T4	329803	2	0	0
T5	108148	2	0	0
T17	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	0	5	0	0
T34	0	1	0	0
T35	0	1	0	0
T57	0	1	0	0
T77	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	617	0	0
T1	649181	1	0	0
T2	92057	0	0	0
T3	730011	2	0	0
T4	329803	2	0	0
T5	108148	2	0	0
T17	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	0	5	0	0
T34	0	1	0	0
T35	0	1	0	0
T57	0	1	0	0
T77	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1960	0	0
T3	730011	12	0	0
T4	329803	0	0	0
T5	108148	0	0	0
T6	184524	0	0	0
T15	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	3	0	0
T34	0	4	0	0
T37	0	2	0	0
T55	0	3	0	0
T77	0	2	0	0
T81	0	10	0	0
T82	0	1	0	0
T97	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	180220	0	0
T3	730011	790	0	0
T4	329803	0	0	0
T5	108148	0	0	0
T6	184524	0	0	0
T15	0	201	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	279	0	0
T34	0	1155	0	0
T37	0	79	0	0
T55	0	184	0	0
T77	0	73	0	0
T81	0	2208	0	0
T82	0	206	0	0
T97	0	848	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1853	0	0
T3	730011	12	0	0
T4	329803	0	0	0
T5	108148	0	0	0
T6	184524	0	0	0
T15	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	2	0	0
T34	0	2	0	0
T37	0	1	0	0
T55	0	2	0	0
T77	0	1	0	0
T81	0	10	0	0
T82	0	1	0	0
T97	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	76	0	0
T6	184524	0	0	0
T7	157956	0	0	0
T8	128860	0	0	0
T15	542022	0	0	0
T33	301669	1	0	0
T34	16175	2	0	0
T41	0	1	0	0
T44	8592	0	0	0
T55	0	1	0	0
T57	16768	0	0	0
T58	205605	0	0	0
T62	0	1	0	0
T77	0	1	0	0
T91	0	1	0	0
T97	0	2	0	0
T103	0	1	0	0
T108	49753	0	0	0
T123	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1482	0	0
T11	38151	367	0	0
T12	0	356	0	0
T13	0	201	0	0
T46	0	389	0	0
T47	0	169	0	0
T48	17827	0	0	0
T49	539794	0	0	0
T50	15661	0	0	0
T51	7235	0	0	0
T52	275544	0	0	0
T53	11972	0	0	0
T54	82013	0	0	0
T55	9878	0	0	0
T56	33853	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1242	0	0
T11	38151	307	0	0
T12	0	296	0	0
T13	0	171	0	0
T46	0	329	0	0
T47	0	139	0	0
T48	17827	0	0	0
T49	539794	0	0	0
T50	15661	0	0	0
T51	7235	0	0	0
T52	275544	0	0	0
T53	11972	0	0	0
T54	82013	0	0	0
T55	9878	0	0	0
T56	33853	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	719026279	0	0
T1	649181	649092	0	0
T2	92057	91966	0	0
T3	730011	729321	0	0
T4	329803	329796	0	0
T5	108148	108138	0	0
T18	35753	35662	0	0
T19	194665	194577	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	1187	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T32
1	1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T20
1	0	1	Covered	T3,T19,T44
1	1	0	Covered	T3,T33,T93
1	1	1	Covered	T3,T33,T94

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T33,T94
0	1	Covered	T33,T81,T96
1	0	Covered	T36,T61,T62

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T33,T94
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T36,T61,T62

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T33,T94
1	0	Not Covered
1	1	Covered	T33,T81,T96

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T20,T33

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T20
1	Covered	T2,T3,T18

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T3,T4,T20

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T33,T34,T60

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T18,T20

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T18

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T20,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T94
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T33,T36,T81
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T94
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T94
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T41,T103,T66
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T39,T42,T102
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T44,T45,T107
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T45,T124
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T20,T33
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	719199704	260	0	0
CheckAccumTrig0_A	719199704	934	0	0
CheckAccumTrig1_A	719199704	49	0	0
CheckClr_A	719199704	466	0	0
CheckEn_A	719042364	265695319	0	0
CheckPhase0_A	719199704	1053	0	0
CheckPhase1_A	719199704	1032	0	0
CheckPhase2_A	719199704	1010	0	0
CheckPhase3_A	719199704	981	0	0
CheckTimeout0_A	719199704	1756	0	0
CheckTimeoutSt1_A	719199704	138095	0	0
CheckTimeoutSt2_A	719199704	1621	0	0
CheckTimeoutStTrig_A	719199704	85	0	0
ErrorStAllEscAsserted_A	719199704	1433	0	0
ErrorStIsTerminal_A	719199704	1193	0	0
u_state_regs_A	719199704	719026279	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	260	0	0
T11	38151	81	0	0
T12	0	80	0	0
T13	0	23	0	0
T46	0	45	0	0
T47	0	31	0	0
T48	17827	0	0	0
T49	539794	0	0	0
T50	15661	0	0	0
T51	7235	0	0	0
T52	275544	0	0	0
T53	11972	0	0	0
T54	82013	0	0	0
T55	9878	0	0	0
T56	33853	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	934	0	0
T2	92057	1	0	0
T3	730011	5	0	0
T4	329803	1	0	0
T5	108148	0	0	0
T15	0	1	0	0
T18	35753	1	0	0
T19	194665	0	0	0
T20	16113	3	0	0
T21	71664	1	0	0
T22	1238	0	0	0
T33	301669	4	0	0
T34	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	49	0	0
T36	49226	1	0	0
T37	882884	0	0	0
T60	277106	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T77	9153	0	0	0
T78	70203	0	0	0
T79	29559	0	0	0
T80	323432	0	0	0
T81	119033	0	0	0
T82	195634	0	0	0
T83	144320	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	466	0	0
T5	108148	0	0	0
T6	184524	0	0	0
T18	35753	1	0	0
T19	194665	0	0	0
T20	16113	3	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	1	0	0
T36	0	3	0	0
T39	0	5	0	0
T42	0	2	0	0
T44	8592	1	0	0
T45	0	11	0	0
T57	16768	0	0	0
T60	0	3	0	0
T82	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719042364	265695319	0	0
T1	649181	577490	0	0
T2	92057	2611	0	0
T3	730011	251681	0	0
T4	329803	5505	0	0
T5	108148	108137	0	0
T18	35753	3225	0	0
T19	194665	7402	0	0
T20	16113	3110	0	0
T21	71664	3654	0	0
T22	1238	1186	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1053	0	0
T2	92057	1	0	0
T3	730011	5	0	0
T4	329803	1	0	0
T5	108148	0	0	0
T15	0	1	0	0
T18	35753	1	0	0
T19	194665	0	0	0
T20	16113	3	0	0
T21	71664	1	0	0
T22	1238	0	0	0
T33	301669	5	0	0
T34	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1032	0	0
T2	92057	1	0	0
T3	730011	5	0	0
T4	329803	1	0	0
T5	108148	0	0	0
T15	0	1	0	0
T18	35753	1	0	0
T19	194665	0	0	0
T20	16113	3	0	0
T21	71664	1	0	0
T22	1238	0	0	0
T33	301669	5	0	0
T34	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1010	0	0
T2	92057	1	0	0
T3	730011	5	0	0
T4	329803	1	0	0
T5	108148	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	35753	1	0	0
T19	194665	0	0	0
T20	16113	3	0	0
T21	71664	1	0	0
T22	1238	0	0	0
T33	301669	5	0	0
T34	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	981	0	0
T2	92057	1	0	0
T3	730011	5	0	0
T4	329803	1	0	0
T5	108148	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	35753	1	0	0
T19	194665	0	0	0
T20	16113	2	0	0
T21	71664	1	0	0
T22	1238	0	0	0
T33	301669	5	0	0
T34	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1756	0	0
T3	730011	2	0	0
T4	329803	0	0	0
T5	108148	0	0	0
T6	184524	0	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	3	0	0
T36	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T77	0	2	0	0
T81	0	1	0	0
T82	0	12	0	0
T94	0	1	0	0
T96	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	138095	0	0
T3	730011	157	0	0
T4	329803	0	0	0
T5	108148	0	0	0
T6	184524	0	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	324	0	0
T53	0	137	0	0
T54	0	130	0	0
T77	0	148	0	0
T81	0	150	0	0
T82	0	1955	0	0
T94	0	106	0	0
T96	0	337	0	0
T98	0	86	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1621	0	0
T3	730011	2	0	0
T4	329803	0	0	0
T5	108148	0	0	0
T6	184524	0	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T62	0	19	0	0
T77	0	2	0	0
T82	0	12	0	0
T94	0	1	0	0
T98	0	1	0	0
T100	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	85	0	0
T6	184524	0	0	0
T7	157956	0	0	0
T8	128860	0	0	0
T15	542022	0	0	0
T33	301669	1	0	0
T34	16175	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T44	8592	0	0	0
T57	16768	0	0	0
T58	205605	0	0	0
T62	0	3	0	0
T81	0	1	0	0
T91	0	1	0	0
T96	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T107	0	1	0	0
T108	49753	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1433	0	0
T11	38151	366	0	0
T12	0	355	0	0
T13	0	179	0	0
T46	0	346	0	0
T47	0	187	0	0
T48	17827	0	0	0
T49	539794	0	0	0
T50	15661	0	0	0
T51	7235	0	0	0
T52	275544	0	0	0
T53	11972	0	0	0
T54	82013	0	0	0
T55	9878	0	0	0
T56	33853	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1193	0	0
T11	38151	306	0	0
T12	0	295	0	0
T13	0	149	0	0
T46	0	286	0	0
T47	0	157	0	0
T48	17827	0	0	0
T49	539794	0	0	0
T50	15661	0	0	0
T51	7235	0	0	0
T52	275544	0	0	0
T53	11972	0	0	0
T54	82013	0	0	0
T55	9878	0	0	0
T56	33853	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	719026279	0	0
T1	649181	649092	0	0
T2	92057	91966	0	0
T3	730011	729321	0	0
T4	329803	329796	0	0
T5	108148	108138	0	0
T18	35753	35662	0	0
T19	194665	194577	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	1187	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T33,T57
1	0	1	Covered	T3,T19,T33
1	1	0	Covered	T3,T33,T15
1	1	1	Covered	T3,T33,T35

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T33,T35
0	1	Covered	T35,T97,T62
1	0	Covered	T91,T63,T104

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T33,T35
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T91,T63,T104

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T33,T35
1	0	Covered	T38
1	1	Covered	T35,T97,T62

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T33
1	Covered	T3,T5,T35

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T33,T17,T78

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T33
1	Covered	T1,T3,T33

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T33,T8,T60

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T33,T7

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T57,T35

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T33

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T5,T33

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T35
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T35,T97,T62
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T35
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T33,T35
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T125,T126,T127
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T43,T69,T128
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T103,T106,T129
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T41,T105,T117
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T5,T57
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	719199704	263	0	0
CheckAccumTrig0_A	719199704	569	0	0
CheckAccumTrig1_A	719199704	29	0	0
CheckClr_A	719199704	269	0	0
CheckEn_A	719042364	323460707	0	0
CheckPhase0_A	719199704	664	0	0
CheckPhase1_A	719199704	646	0	0
CheckPhase2_A	719199704	637	0	0
CheckPhase3_A	719199704	623	0	0
CheckTimeout0_A	719199704	1319	0	0
CheckTimeoutSt1_A	719199704	123828	0	0
CheckTimeoutSt2_A	719199704	1216	0	0
CheckTimeoutStTrig_A	719199704	73	0	0
ErrorStAllEscAsserted_A	719199704	1462	0	0
ErrorStIsTerminal_A	719199704	1222	0	0
u_state_regs_A	719199704	719026279	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	263	0	0
T11	38151	85	0	0
T12	0	57	0	0
T13	0	25	0	0
T46	0	55	0	0
T47	0	41	0	0
T48	17827	0	0	0
T49	539794	0	0	0
T50	15661	0	0	0
T51	7235	0	0	0
T52	275544	0	0	0
T53	11972	0	0	0
T54	82013	0	0	0
T55	9878	0	0	0
T56	33853	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	569	0	0
T1	649181	1	0	0
T2	92057	0	0	0
T3	730011	3	0	0
T4	329803	0	0	0
T5	108148	1	0	0
T7	0	1	0	0
T8	0	1	0	0
T17	0	2	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	0	3	0	0
T57	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	29	0	0
T63	379836	2	0	0
T64	480364	0	0	0
T68	0	1	0	0
T76	0	1	0	0
T85	222324	0	0	0
T86	151456	0	0	0
T87	21413	0	0	0
T88	27591	0	0	0
T89	119045	0	0	0
T90	8083	0	0	0
T104	0	1	0	0
T116	0	1	0	0
T129	0	3	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	3	0	0
T133	0	4	0	0
T134	3774	0	0	0
T135	21133	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	269	0	0
T3	730011	1	0	0
T4	329803	0	0	0
T5	108148	1	0	0
T6	184524	0	0	0
T17	0	1	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	0	0	0
T35	0	1	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T60	0	1	0	0
T91	0	1	0	0
T95	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719042364	323460707	0	0
T1	649181	47870	0	0
T2	92057	91965	0	0
T3	730011	587273	0	0
T4	329803	329796	0	0
T5	108148	107994	0	0
T18	35753	35661	0	0
T19	194665	180165	0	0
T20	16113	16058	0	0
T21	71664	71564	0	0
T22	1238	1186	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	664	0	0
T1	649181	1	0	0
T2	92057	0	0	0
T3	730011	3	0	0
T4	329803	0	0	0
T5	108148	1	0	0
T7	0	1	0	0
T8	0	1	0	0
T17	0	2	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	0	3	0	0
T35	0	2	0	0
T57	0	2	0	0
T59	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	646	0	0
T1	649181	1	0	0
T2	92057	0	0	0
T3	730011	3	0	0
T4	329803	0	0	0
T5	108148	1	0	0
T7	0	1	0	0
T8	0	1	0	0
T17	0	2	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	0	3	0	0
T35	0	2	0	0
T57	0	2	0	0
T59	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	637	0	0
T1	649181	1	0	0
T2	92057	0	0	0
T3	730011	3	0	0
T4	329803	0	0	0
T5	108148	1	0	0
T7	0	1	0	0
T8	0	1	0	0
T17	0	2	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	0	3	0	0
T35	0	2	0	0
T57	0	2	0	0
T59	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	623	0	0
T1	649181	1	0	0
T2	92057	0	0	0
T3	730011	3	0	0
T4	329803	0	0	0
T5	108148	1	0	0
T7	0	1	0	0
T8	0	1	0	0
T17	0	2	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	0	3	0	0
T35	0	2	0	0
T57	0	2	0	0
T59	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1319	0	0
T3	730011	1	0	0
T4	329803	0	0	0
T5	108148	0	0	0
T6	184524	0	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T77	0	2	0	0
T81	0	3	0	0
T82	0	4	0	0
T95	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	123828	0	0
T3	730011	80	0	0
T4	329803	0	0	0
T5	108148	0	0	0
T6	184524	0	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	293	0	0
T35	0	503	0	0
T37	0	52	0	0
T53	0	137	0	0
T55	0	71	0	0
T77	0	118	0	0
T81	0	577	0	0
T82	0	682	0	0
T95	0	1085	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1216	0	0
T3	730011	1	0	0
T4	329803	0	0	0
T5	108148	0	0	0
T6	184524	0	0	0
T18	35753	0	0	0
T19	194665	0	0	0
T20	16113	0	0	0
T21	71664	0	0	0
T22	1238	0	0	0
T33	301669	3	0	0
T35	0	1	0	0
T37	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T77	0	2	0	0
T81	0	3	0	0
T82	0	4	0	0
T95	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	73	0	0
T17	233032	0	0	0
T35	24303	2	0	0
T36	49226	0	0	0
T39	423164	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	10008	0	0	0
T59	580397	0	0	0
T60	277106	0	0	0
T62	0	1	0	0
T77	9153	0	0	0
T78	70203	0	0	0
T91	0	1	0	0
T94	5079	0	0	0
T97	0	1	0	0
T102	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1462	0	0
T11	38151	370	0	0
T12	0	387	0	0
T13	0	163	0	0
T46	0	351	0	0
T47	0	191	0	0
T48	17827	0	0	0
T49	539794	0	0	0
T50	15661	0	0	0
T51	7235	0	0	0
T52	275544	0	0	0
T53	11972	0	0	0
T54	82013	0	0	0
T55	9878	0	0	0
T56	33853	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	1222	0	0
T11	38151	310	0	0
T12	0	327	0	0
T13	0	133	0	0
T46	0	291	0	0
T47	0	161	0	0
T48	17827	0	0	0
T49	539794	0	0	0
T50	15661	0	0	0
T51	7235	0	0	0
T52	275544	0	0	0
T53	11972	0	0	0
T54	82013	0	0	0
T55	9878	0	0	0
T56	33853	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719199704	719026279	0	0
T1	649181	649092	0	0
T2	92057	91966	0	0
T3	730011	729321	0	0
T4	329803	329796	0	0
T5	108148	108138	0	0
T18	35753	35662	0	0
T19	194665	194577	0	0
T20	16113	16059	0	0
T21	71664	71565	0	0
T22	1238	1187	0	0