Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=6 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	72546	72546	0	0
OutputsKnown_A	2147483647	2147483647	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	2147483647	2147483647	0	92448
gen_no_flops.OutputDelay_A	2147483647	2147483647	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72546	72546	0	0
T1	113	113	0	0
T2	113	113	0	0
T3	113	113	0	0
T7	113	113	0	0
T9	113	113	0	0
T13	113	113	0	0
T32	113	113	0	0
T34	113	113	0	0
T50	113	113	0	0
T51	113	113	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7175500	7169737	0	0
T2	3854430	3843808	0	0
T3	36190397	36189493	0	0
T7	37856469	37855565	0	0
T9	618223	609183	0	0
T13	5538017	5527960	0	0
T32	13755377	13744868	0	0
T34	2852007	2841385	0	0
T50	9665229	9658901	0	0
T51	1461655	1453858	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	92448
T1	3048000	3045408	0	144
T2	1637280	1632624	0	144
T3	15372912	15372528	0	144
T7	16080624	16080240	0	144
T9	262608	258624	0	144
T13	2352432	2348016	0	144
T32	5842992	5838384	0	144
T34	1211472	1206816	0	144
T50	4105584	4102752	0	144
T51	620880	617424	0	144

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4127500	4124185	0	0
T2	2217150	2211040	0	0
T3	20817485	20816965	0	0
T7	21775845	21775325	0	0
T9	355615	350415	0	0
T13	3185585	3179800	0	0
T32	7912385	7906340	0	0
T34	1640535	1634425	0	0
T50	5559645	5556005	0	0
T51	840775	836290	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	771781842	771599035	0	1926

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771599035	0	1926
T1	63500	63446	0	3
T2	34110	34013	0	3
T3	320269	320261	0	3
T7	335013	335005	0	3
T9	5471	5388	0	3
T13	49009	48917	0	3
T32	121729	121633	0	3
T34	25239	25142	0	3
T50	85533	85474	0	3
T51	12935	12863	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	642	642	0	0
OutputsKnown_A	771781842	771606931	0	0
gen_no_flops.OutputDelay_A	771781842	771606931	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	642	642	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T32	1	1	0	0
T34	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0