Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.95	100.00	100.00	83.78			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	83.78			83.78

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.95	100.00	100.00	83.78			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	83.78			83.78

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T200,T201
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13226	0	0
DisabledNoTrigBkwd_A	2147483647	762782	0	0
DisabledNoTrigFwd_A	2147483647	1725514221	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13226	0	0
T14	111860	0	0	0
T98	360884	0	0	0
T109	318719	0	0	0
T199	3400	981	0	0
T200	1117	287	0	0
T201	0	752	0	0
T202	0	912	0	0
T203	3273	867	0	0
T204	0	862	0	0
T205	0	267	0	0
T206	2723	499	0	0
T207	0	413	0	0
T208	0	757	0	0
T209	0	630	0	0
T210	1443	628	0	0
T211	0	642	0	0
T212	0	379	0	0
T213	0	904	0	0
T214	0	1109	0	0
T215	0	638	0	0
T216	0	755	0	0
T217	0	255	0	0
T218	0	689	0	0
T219	157143	0	0	0
T220	40502	0	0	0
T221	111893	0	0	0
T222	3855	0	0	0
T223	168836	0	0	0
T224	7184	0	0	0
T225	301171	0	0	0
T226	179884	0	0	0
T227	38974	0	0	0
T228	348321	0	0	0
T229	37144	0	0	0
T230	210417	0	0	0
T231	108505	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	762782	0	0
T2	136440	148	0	0
T3	1281076	1297	0	0
T5	0	55	0	0
T7	1340052	21	0	0
T8	644048	1130	0	0
T9	21884	0	0	0
T13	196036	16	0	0
T25	0	5117	0	0
T26	0	4027	0	0
T32	486916	15	0	0
T33	0	390	0	0
T34	100956	41	0	0
T37	0	3732	0	0
T39	0	1986	0	0
T50	342132	82	0	0
T51	51740	2	0	0
T52	0	77	0	0
T53	0	92	0	0
T54	0	134	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1725514221	0	0
T1	254000	193381	0	0
T2	136440	19716	0	0
T3	1281076	961683	0	0
T7	1340052	1333341	0	0
T9	21884	15169	0	0
T13	196036	157312	0	0
T32	486916	377209	0	0
T34	100956	75255	0	0
T50	342132	250387	0	0
T51	51740	35442	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T210,T213
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	771781842	2286	0	0
DisabledNoTrigBkwd_A	771781842	235224	0	0
DisabledNoTrigFwd_A	771781842	375600612	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	2286	0	0
T109	318719	0	0	0
T206	2723	499	0	0
T210	1443	628	0	0
T213	0	904	0	0
T217	0	255	0	0
T225	301171	0	0	0
T226	179884	0	0	0
T227	38974	0	0	0
T228	348321	0	0	0
T229	37144	0	0	0
T230	210417	0	0	0
T231	108505	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	235224	0	0
T2	34110	31	0	0
T3	320269	1	0	0
T7	335013	1	0	0
T8	161012	406	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T32	121729	15	0	0
T33	0	142	0	0
T34	25239	41	0	0
T50	85533	82	0	0
T51	12935	2	0	0
T52	0	30	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	375600612	0	0
T1	63500	3034	0	0
T2	34110	8877	0	0
T3	320269	319714	0	0
T7	335013	334575	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	38941	0	0
T34	25239	1868	0	0
T50	85533	2686	0	0
T51	12935	4252	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T3,T9,T7
1	1	Covered	T2,T3,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T203,T204
1	1	Covered	T2,T3,T7

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	771781842	5966	0	0
DisabledNoTrigBkwd_A	771781842	164488	0	0
DisabledNoTrigFwd_A	771781842	475053621	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	5966	0	0
T14	111860	0	0	0
T98	360884	0	0	0
T199	3400	981	0	0
T203	3273	867	0	0
T204	0	862	0	0
T207	0	413	0	0
T208	0	757	0	0
T211	0	642	0	0
T216	0	755	0	0
T218	0	689	0	0
T219	157143	0	0	0
T220	40502	0	0	0
T221	111893	0	0	0
T222	3855	0	0	0
T223	168836	0	0	0
T224	7184	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	164488	0	0
T2	34110	47	0	0
T3	320269	2	0	0
T5	0	1	0	0
T7	335013	17	0	0
T8	161012	0	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	3	0	0
T26	0	1836	0	0
T32	121729	0	0	0
T33	0	57	0	0
T34	25239	0	0	0
T37	0	2292	0	0
T39	0	1986	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T53	0	23	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	475053621	0	0
T1	63500	63449	0	0
T2	34110	884	0	0
T3	320269	319172	0	0
T7	335013	331467	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	118288	0	0
T34	25239	24121	0	0
T50	85533	85477	0	0
T51	12935	5458	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T3,T9,T7
1	1	Covered	T2,T3,T9

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T202,T214
1	1	Covered	T2,T3,T9

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	771781842	2308	0	0
DisabledNoTrigBkwd_A	771781842	171554	0	0
DisabledNoTrigFwd_A	771781842	456385831	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	2308	0	0
T11	41023	0	0	0
T60	702635	0	0	0
T99	46884	0	0	0
T200	1117	287	0	0
T202	0	912	0	0
T214	0	1109	0	0
T232	11717	0	0	0
T233	23715	0	0	0
T234	23482	0	0	0
T235	178591	0	0	0
T236	604662	0	0	0
T237	95467	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	171554	0	0
T2	34110	39	0	0
T3	320269	0	0	0
T5	0	54	0	0
T7	335013	2	0	0
T8	161012	0	0	0
T9	5471	0	0	0
T13	49009	16	0	0
T25	0	4263	0	0
T26	0	2	0	0
T32	121729	0	0	0
T33	0	149	0	0
T34	25239	0	0	0
T37	0	1440	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	0	21	0	0
T54	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	456385831	0	0
T1	63500	63449	0	0
T2	34110	888	0	0
T3	320269	319715	0	0
T7	335013	333635	0	0
T9	5471	1600	0	0
T13	49009	10552	0	0
T32	121729	98344	0	0
T34	25239	24121	0	0
T50	85533	81112	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T2,T9,T7
1	1	Covered	T2,T3,T9

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T205,T209
1	1	Covered	T2,T3,T9

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	771781842	2666	0	0
DisabledNoTrigBkwd_A	771781842	191516	0	0
DisabledNoTrigFwd_A	771781842	418474157	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	2666	0	0
T66	32569	0	0	0
T67	322127	0	0	0
T201	1707	752	0	0
T205	0	267	0	0
T209	0	630	0	0
T212	0	379	0	0
T215	0	638	0	0
T238	388712	0	0	0
T239	113182	0	0	0
T240	208627	0	0	0
T241	13192	0	0	0
T242	130137	0	0	0
T243	106781	0	0	0
T244	7800	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	191516	0	0
T2	34110	31	0	0
T3	320269	1294	0	0
T7	335013	1	0	0
T8	161012	724	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	851	0	0
T26	0	2189	0	0
T32	121729	0	0	0
T33	0	42	0	0
T34	25239	0	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	0	26	0	0
T53	0	69	0	0
T54	0	133	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	418474157	0	0
T1	63500	63449	0	0
T2	34110	9067	0	0
T3	320269	3082	0	0
T7	335013	333664	0	0
T9	5471	2787	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	81112	0	0
T51	12935	12866	0	0