Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.78	100.00	95.56	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.78	100.00	95.56	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T7

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T13
1	0	1	Covered	T3,T9,T7
1	1	0	Covered	T25,T26,T5
1	1	1	Covered	T1,T25,T26

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T25,T26
0	1	Covered	T5,T6,T27
1	0	Covered	T28,T29,T30

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T25,T26
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T28,T29,T30

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T26
1	0	Covered	T5,T31
1	1	Covered	T5,T6,T27

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T3,T7

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T7,T13

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T3,T32,T33

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T7,T34,T8

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T15
IdleSt	175	Covered	T15
Phase0St	146	Covered	T15
Phase1St	192	Covered	T15
Phase2St	209	Covered	T15
Phase3St	227	Covered	T15
TerminalSt	243	Covered	T15
TimeoutSt	153	Covered	T15

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	278	Covered	T15
IdleSt->Phase0St	146	Covered	T15
IdleSt->TimeoutSt	153	Covered	T15
Phase0St->FsmErrorSt	278	Not Covered
Phase0St->IdleSt	188	Covered	T15
Phase0St->Phase1St	192	Covered	T15
Phase1St->FsmErrorSt	278	Not Covered
Phase1St->IdleSt	205	Covered	T15
Phase1St->Phase2St	209	Covered	T15
Phase2St->FsmErrorSt	278	Not Covered
Phase2St->IdleSt	223	Covered	T15
Phase2St->Phase3St	227	Covered	T15
Phase3St->FsmErrorSt	278	Not Covered
Phase3St->IdleSt	239	Covered	T15
Phase3St->TerminalSt	243	Covered	T15
TerminalSt->FsmErrorSt	278	Not Covered
TerminalSt->IdleSt	255	Covered	T15
TimeoutSt->FsmErrorSt	278	Not Covered
TimeoutSt->IdleSt	175	Covered	T15
TimeoutSt->Phase0St	166	Covered	T15

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T35,T36
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T25,T6,T27
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T37,T5,T38
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T39,T27,T40
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T7,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1115	0	0
CheckAccumTrig0_A	2147483647	2614	0	0
CheckAccumTrig1_A	2147483647	136	0	0
CheckClr_A	2147483647	1268	0	0
CheckEn_A	2147483647	1299464744	0	0
CheckPhase0_A	2147483647	3054	0	0
CheckPhase1_A	2147483647	3000	0	0
CheckPhase2_A	2147483647	2935	0	0
CheckPhase3_A	2147483647	2869	0	0
CheckTimeout0_A	2147483647	4723	0	0
CheckTimeoutSt1_A	2147483647	592875	0	0
CheckTimeoutSt2_A	2147483647	4234	0	0
CheckTimeoutStTrig_A	2147483647	352	0	0
ErrorStAllEscAsserted_A	2147483647	5815	0	0
ErrorStIsTerminal_A	2147483647	4855	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1115	0	0
T10	86320	169	0	0
T11	0	279	0	0
T12	0	124	0	0
T36	108464	0	0	0
T38	590504	0	0	0
T41	0	243	0	0
T42	0	300	0	0
T43	80500	0	0	0
T44	1828704	0	0	0
T45	69392	0	0	0
T46	89312	0	0	0
T47	168788	0	0	0
T48	449992	0	0	0
T49	624320	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2614	0	0
T2	136440	4	0	0
T3	1281076	7	0	0
T5	0	2	0	0
T7	1340052	7	0	0
T8	644048	3	0	0
T9	21884	0	0	0
T13	196036	2	0	0
T25	0	3	0	0
T26	0	3	0	0
T32	486916	1	0	0
T33	0	4	0	0
T34	100956	1	0	0
T37	0	4	0	0
T39	0	5	0	0
T50	342132	1	0	0
T51	51740	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T54	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	136	0	0
T10	21580	0	0	0
T28	140036	1	0	0
T29	388510	1	0	0
T30	1886246	2	0	0
T31	508849	1	0	0
T36	27116	0	0	0
T40	260056	0	0	0
T43	20125	0	0	0
T44	457176	0	0	0
T55	177995	1	0	0
T56	27586	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	4995	1	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	5	0	0
T68	0	4	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	26590	0	0	0
T73	8318	0	0	0
T74	512196	0	0	0
T75	701118	0	0	0
T76	145146	0	0	0
T77	899548	0	0	0
T78	12675	0	0	0
T79	32271	0	0	0
T80	169558	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1268	0	0
T3	640538	5	0	0
T5	0	24	0	0
T6	0	6	0	0
T7	1340052	6	0	0
T8	644048	1	0	0
T9	10942	0	0	0
T13	196036	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	14	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	486916	0	0	0
T33	271436	0	0	0
T34	100956	0	0	0
T35	0	5	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	4	0	0
T48	0	2	0	0
T50	342132	0	0	0
T51	51740	0	0	0
T52	334524	0	0	0
T53	332740	0	0	0
T73	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1299464744	0	0
T1	254000	193378	0	0
T2	136440	16044	0	0
T3	1281076	645390	0	0
T7	1340052	1022181	0	0
T9	21884	15167	0	0
T13	196036	157309	0	0
T32	486916	377206	0	0
T34	100956	74223	0	0
T50	342132	250384	0	0
T51	51740	31777	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3054	0	0
T2	136440	4	0	0
T3	1281076	7	0	0
T5	0	9	0	0
T7	1340052	7	0	0
T8	644048	3	0	0
T9	21884	0	0	0
T13	196036	2	0	0
T25	0	3	0	0
T26	0	3	0	0
T32	486916	1	0	0
T33	0	4	0	0
T34	100956	1	0	0
T37	0	4	0	0
T39	0	5	0	0
T50	342132	1	0	0
T51	51740	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T54	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3000	0	0
T2	136440	4	0	0
T3	1281076	7	0	0
T5	0	9	0	0
T6	0	4	0	0
T7	1340052	7	0	0
T8	644048	3	0	0
T9	21884	0	0	0
T13	196036	2	0	0
T25	0	2	0	0
T26	0	3	0	0
T32	486916	1	0	0
T33	0	4	0	0
T34	100956	1	0	0
T37	0	4	0	0
T39	0	5	0	0
T50	342132	1	0	0
T51	51740	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T54	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2935	0	0
T2	136440	4	0	0
T3	1281076	7	0	0
T5	0	8	0	0
T6	0	4	0	0
T7	1340052	7	0	0
T8	644048	3	0	0
T9	21884	0	0	0
T13	196036	2	0	0
T25	0	2	0	0
T26	0	3	0	0
T32	486916	1	0	0
T33	0	4	0	0
T34	100956	1	0	0
T37	0	3	0	0
T39	0	5	0	0
T50	342132	1	0	0
T51	51740	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T54	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2869	0	0
T2	136440	4	0	0
T3	1281076	7	0	0
T5	0	18	0	0
T6	0	4	0	0
T7	1340052	6	0	0
T8	644048	3	0	0
T9	21884	0	0	0
T13	196036	2	0	0
T25	0	2	0	0
T26	0	3	0	0
T32	486916	1	0	0
T33	0	4	0	0
T34	100956	1	0	0
T37	0	3	0	0
T39	0	4	0	0
T50	342132	1	0	0
T51	51740	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T54	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4723	0	0
T1	63500	1	0	0
T2	34110	0	0	0
T3	320269	0	0	0
T5	586084	47	0	0
T6	899282	16	0	0
T7	335013	0	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	1	0	0
T26	511651	2	0	0
T27	853860	96	0	0
T28	0	7	0	0
T29	0	1	0	0
T30	0	3	0	0
T32	121729	0	0	0
T34	25239	0	0	0
T35	0	17	0	0
T36	0	8	0	0
T39	871798	0	0	0
T40	0	18	0	0
T46	0	1	0	0
T48	0	3	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T73	0	3	0	0
T82	21370	1	0	0
T85	64980	16	0	0
T86	0	7	0	0
T87	560682	0	0	0
T88	133206	0	0	0
T89	653844	0	0	0
T90	1746252	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	592875	0	0
T1	63500	166	0	0
T2	34110	0	0	0
T3	320269	0	0	0
T5	586084	9550	0	0
T6	899282	2997	0	0
T7	335013	0	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	46	0	0
T26	511651	165	0	0
T27	853860	15155	0	0
T28	0	2066	0	0
T29	0	2	0	0
T30	0	1107	0	0
T32	121729	0	0	0
T34	25239	0	0	0
T35	0	2101	0	0
T36	0	879	0	0
T39	871798	0	0	0
T40	0	1242	0	0
T46	0	20	0	0
T48	0	168	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T73	0	437	0	0
T82	21370	429	0	0
T85	64980	1013	0	0
T86	0	539	0	0
T87	560682	0	0	0
T88	133206	0	0	0
T89	653844	0	0	0
T90	1746252	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4234	0	0
T1	63500	1	0	0
T2	34110	0	0	0
T3	320269	0	0	0
T5	586084	31	0	0
T6	899282	14	0	0
T7	335013	0	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	1	0	0
T26	511651	2	0	0
T27	853860	89	0	0
T28	0	5	0	0
T30	0	7	0	0
T32	121729	0	0	0
T34	25239	0	0	0
T35	0	17	0	0
T36	0	7	0	0
T39	871798	0	0	0
T40	0	34	0	0
T43	0	1	0	0
T48	0	1	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T73	0	2	0	0
T82	21370	1	0	0
T85	64980	16	0	0
T86	0	7	0	0
T87	560682	0	0	0
T88	133206	0	0	0
T89	653844	0	0	0
T90	1746252	0	0	0
T91	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352	0	0
T5	1172168	9	0	0
T6	1798564	2	0	0
T27	1707720	6	0	0
T30	0	2	0	0
T36	0	1	0	0
T39	1743596	0	0	0
T46	0	1	0	0
T48	0	2	0	0
T55	0	1	0	0
T57	0	3	0	0
T60	0	6	0	0
T62	0	2	0	0
T73	0	1	0	0
T82	85480	0	0	0
T85	129960	0	0	0
T87	1121364	0	0	0
T88	266412	0	0	0
T89	1307688	0	0	0
T90	3492504	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	3	0	0
T96	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0
T99	0	2	0	0
T100	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5815	0	0
T10	86320	709	0	0
T11	0	1521	0	0
T12	0	678	0	0
T36	108464	0	0	0
T38	590504	0	0	0
T41	0	1438	0	0
T42	0	1469	0	0
T43	80500	0	0	0
T44	1828704	0	0	0
T45	69392	0	0	0
T46	89312	0	0	0
T47	168788	0	0	0
T48	449992	0	0	0
T49	624320	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4855	0	0
T10	86320	589	0	0
T11	0	1281	0	0
T12	0	558	0	0
T36	108464	0	0	0
T38	590504	0	0	0
T41	0	1198	0	0
T42	0	1229	0	0
T43	80500	0	0	0
T44	1828704	0	0	0
T45	69392	0	0	0
T46	89312	0	0	0
T47	168788	0	0	0
T48	449992	0	0	0
T49	624320	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	254000	253796	0	0
T2	136440	136064	0	0
T3	1281076	1281044	0	0
T7	1340052	1340020	0	0
T9	21884	21564	0	0
T13	196036	195680	0	0
T32	486916	486544	0	0
T34	100956	100580	0	0
T50	342132	341908	0	0
T51	51740	51464	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T7

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T51,T25,T26
1	0	1	Covered	T3,T32,T8
1	1	0	Covered	T25,T5,T6
1	1	1	Covered	T26,T5,T6

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T5,T6
0	1	Covered	T5,T6,T27
1	0	Covered	T30,T55,T56

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T26,T5,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T30,T55,T56

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T5,T6
1	0	Not Covered
1	1	Covered	T5,T6,T27

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T33,T53
1	Covered	T2,T3,T7

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T7,T53,T26

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T5,T6,T27

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T33,T5,T6

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T15
IdleSt	175	Covered	T15
Phase0St	146	Covered	T15
Phase1St	192	Covered	T15
Phase2St	209	Covered	T15
Phase3St	227	Covered	T15
TerminalSt	243	Covered	T15
TimeoutSt	153	Covered	T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T15
IdleSt->Phase0St	146	Covered	T15
IdleSt->TimeoutSt	153	Covered	T15
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T15
Phase0St->Phase1St	192	Covered	T15
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T15
Phase1St->Phase2St	209	Covered	T15
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T15
Phase2St->Phase3St	227	Covered	T15
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T15
Phase3St->TerminalSt	243	Covered	T15
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T15
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T15
TimeoutSt->Phase0St	166	Covered	T15

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T5,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T26,T5,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T26,T5,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T35,T36,T101
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T25,T102,T103
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T37,T38,T30
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T39,T40,T62
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T5,T39
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	771781842	284	0	0
CheckAccumTrig0_A	771781842	557	0	0
CheckAccumTrig1_A	771781842	33	0	0
CheckClr_A	771781842	280	0	0
CheckEn_A	771462135	353352383	0	0
CheckPhase0_A	771781842	668	0	0
CheckPhase1_A	771781842	658	0	0
CheckPhase2_A	771781842	648	0	0
CheckPhase3_A	771781842	631	0	0
CheckTimeout0_A	771781842	1514	0	0
CheckTimeoutSt1_A	771781842	185951	0	0
CheckTimeoutSt2_A	771781842	1394	0	0
CheckTimeoutStTrig_A	771781842	87	0	0
ErrorStAllEscAsserted_A	771781842	1508	0	0
ErrorStIsTerminal_A	771781842	1268	0	0
u_state_regs_A	771781842	771606931	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	284	0	0
T10	21580	35	0	0
T11	0	70	0	0
T12	0	20	0	0
T36	27116	0	0	0
T38	147626	0	0	0
T41	0	72	0	0
T42	0	87	0	0
T43	20125	0	0	0
T44	457176	0	0	0
T45	17348	0	0	0
T46	22328	0	0	0
T47	42197	0	0	0
T48	112498	0	0	0
T49	156080	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	557	0	0
T2	34110	1	0	0
T3	320269	1	0	0
T5	0	1	0	0
T7	335013	4	0	0
T8	161012	0	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T37	0	2	0	0
T39	0	5	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T53	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	33	0	0
T30	943123	1	0	0
T31	0	1	0	0
T40	130028	0	0	0
T55	177995	1	0	0
T56	27586	1	0	0
T57	0	1	0	0
T60	0	2	0	0
T62	0	1	0	0
T64	0	1	0	0
T67	0	1	0	0
T70	0	1	0	0
T74	256098	0	0	0
T75	350559	0	0	0
T76	72573	0	0	0
T77	899548	0	0	0
T78	12675	0	0	0
T79	32271	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	280	0	0
T5	0	2	0	0
T6	0	1	0	0
T7	335013	3	0	0
T8	161012	0	0	0
T13	49009	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T32	121729	0	0	0
T33	135718	0	0	0
T34	25239	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	4	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	83631	0	0	0
T53	166370	0	0	0
T84	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771462135	353352383	0	0
T1	63500	63448	0	0
T2	34110	884	0	0
T3	320269	3043	0	0
T7	335013	20308	0	0
T9	5471	5390	0	0
T13	49009	48919	0	0
T32	121729	118287	0	0
T34	25239	24120	0	0
T50	85533	85476	0	0
T51	12935	5457	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	668	0	0
T2	34110	1	0	0
T3	320269	1	0	0
T5	0	2	0	0
T7	335013	4	0	0
T8	161012	0	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T37	0	2	0	0
T39	0	5	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T53	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	658	0	0
T2	34110	1	0	0
T3	320269	1	0	0
T5	0	2	0	0
T6	0	4	0	0
T7	335013	4	0	0
T8	161012	0	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T37	0	2	0	0
T39	0	5	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T53	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	648	0	0
T2	34110	1	0	0
T3	320269	1	0	0
T5	0	2	0	0
T6	0	4	0	0
T7	335013	4	0	0
T8	161012	0	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T37	0	1	0	0
T39	0	5	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T53	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	631	0	0
T2	34110	1	0	0
T3	320269	1	0	0
T5	0	2	0	0
T6	0	4	0	0
T7	335013	4	0	0
T8	161012	0	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T37	0	1	0	0
T39	0	4	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T53	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1514	0	0
T5	293042	4	0	0
T6	449641	2	0	0
T26	511651	1	0	0
T27	426930	4	0	0
T28	0	3	0	0
T35	0	7	0	0
T36	0	3	0	0
T39	435899	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T85	32490	1	0	0
T87	280341	0	0	0
T88	66603	0	0	0
T89	326922	0	0	0
T90	873126	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	185951	0	0
T5	293042	984	0	0
T6	449641	456	0	0
T26	511651	124	0	0
T27	426930	1626	0	0
T28	0	765	0	0
T35	0	709	0	0
T36	0	260	0	0
T39	435899	0	0	0
T46	0	20	0	0
T48	0	57	0	0
T85	32490	67	0	0
T87	280341	0	0	0
T88	66603	0	0	0
T89	326922	0	0	0
T90	873126	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1394	0	0
T5	293042	3	0	0
T6	449641	1	0	0
T26	511651	1	0	0
T27	426930	1	0	0
T28	0	3	0	0
T30	0	5	0	0
T35	0	7	0	0
T36	0	2	0	0
T39	435899	0	0	0
T40	0	19	0	0
T85	32490	1	0	0
T87	280341	0	0	0
T88	66603	0	0	0
T89	326922	0	0	0
T90	873126	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	87	0	0
T5	293042	1	0	0
T6	449641	1	0	0
T27	426930	3	0	0
T30	0	2	0	0
T36	0	1	0	0
T39	435899	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T57	0	2	0	0
T82	21370	0	0	0
T85	32490	0	0	0
T87	280341	0	0	0
T88	66603	0	0	0
T89	326922	0	0	0
T90	873126	0	0	0
T92	0	1	0	0
T95	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1508	0	0
T10	21580	172	0	0
T11	0	422	0	0
T12	0	159	0	0
T36	27116	0	0	0
T38	147626	0	0	0
T41	0	374	0	0
T42	0	381	0	0
T43	20125	0	0	0
T44	457176	0	0	0
T45	17348	0	0	0
T46	22328	0	0	0
T47	42197	0	0	0
T48	112498	0	0	0
T49	156080	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1268	0	0
T10	21580	142	0	0
T11	0	362	0	0
T12	0	129	0	0
T36	27116	0	0	0
T38	147626	0	0	0
T41	0	314	0	0
T42	0	321	0	0
T43	20125	0	0	0
T44	457176	0	0	0
T45	17348	0	0	0
T46	22328	0	0	0
T47	42197	0	0	0
T48	112498	0	0	0
T49	156080	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T9
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T7

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T25,T26
1	0	1	Covered	T3,T13,T32
1	1	0	Covered	T26,T5,T6
1	1	1	Covered	T5,T6,T27

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T27
0	1	Covered	T5,T27,T73
1	0	Covered	T29,T58,T67

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T6,T27
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T29,T58,T67

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T27
1	0	Not Covered
1	1	Covered	T5,T27,T73

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T13,T33
1	Covered	T2,T13,T52

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T13
1	Covered	T13,T37,T5

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T13
1	Covered	T33,T54,T25

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T13,T52
1	Covered	T7,T26,T5

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T13,T52

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T7,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T7,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T13,T52

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T15
IdleSt	175	Covered	T15
Phase0St	146	Covered	T15
Phase1St	192	Covered	T15
Phase2St	209	Covered	T15
Phase3St	227	Covered	T15
TerminalSt	243	Covered	T15
TimeoutSt	153	Covered	T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T15
IdleSt->Phase0St	146	Covered	T15
IdleSt->TimeoutSt	153	Covered	T15
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T15
Phase0St->Phase1St	192	Covered	T15
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T15
Phase1St->Phase2St	209	Covered	T15
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T15
Phase2St->Phase3St	227	Covered	T15
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T15
Phase3St->TerminalSt	243	Covered	T15
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T15
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T15
TimeoutSt->Phase0St	166	Covered	T15

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T27
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T27,T29
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T27
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T27
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T40,T103,T104
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T7,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T7,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T40,T105
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T7,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T7,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T40,T64
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T7,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T7,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T40,T95,T106
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T7,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T7,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T13,T37
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T7,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	771781842	279	0	0
CheckAccumTrig0_A	771781842	554	0	0
CheckAccumTrig1_A	771781842	23	0	0
CheckClr_A	771781842	252	0	0
CheckEn_A	771462135	346644655	0	0
CheckPhase0_A	771781842	640	0	0
CheckPhase1_A	771781842	629	0	0
CheckPhase2_A	771781842	617	0	0
CheckPhase3_A	771781842	608	0	0
CheckTimeout0_A	771781842	915	0	0
CheckTimeoutSt1_A	771781842	119970	0	0
CheckTimeoutSt2_A	771781842	817	0	0
CheckTimeoutStTrig_A	771781842	74	0	0
ErrorStAllEscAsserted_A	771781842	1480	0	0
ErrorStIsTerminal_A	771781842	1240	0	0
u_state_regs_A	771781842	771606931	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	279	0	0
T10	21580	57	0	0
T11	0	86	0	0
T12	0	33	0	0
T36	27116	0	0	0
T38	147626	0	0	0
T41	0	53	0	0
T42	0	50	0	0
T43	20125	0	0	0
T44	457176	0	0	0
T45	17348	0	0	0
T46	22328	0	0	0
T47	42197	0	0	0
T48	112498	0	0	0
T49	156080	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	554	0	0
T2	34110	1	0	0
T3	320269	0	0	0
T5	0	1	0	0
T7	335013	1	0	0
T8	161012	0	0	0
T9	5471	0	0	0
T13	49009	2	0	0
T25	0	1	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T37	0	2	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	0	1	0	0
T54	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	23	0	0
T10	21580	0	0	0
T29	388510	1	0	0
T36	27116	0	0	0
T38	147626	0	0	0
T43	20125	0	0	0
T44	457176	0	0	0
T45	17348	0	0	0
T46	22328	0	0	0
T47	42197	0	0	0
T58	0	1	0	0
T67	0	1	0	0
T69	0	1	0	0
T71	0	1	0	0
T73	8318	0	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	252	0	0
T5	0	4	0	0
T6	0	1	0	0
T7	335013	1	0	0
T8	161012	0	0	0
T13	49009	1	0	0
T26	0	1	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	121729	0	0	0
T33	135718	0	0	0
T34	25239	0	0	0
T37	0	1	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	83631	0	0	0
T53	166370	0	0	0
T73	0	1	0	0
T82	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771462135	346644655	0	0
T1	63500	63448	0	0
T2	34110	888	0	0
T3	320269	319714	0	0
T7	335013	333634	0	0
T9	5471	1600	0	0
T13	49009	10552	0	0
T32	121729	98343	0	0
T34	25239	24120	0	0
T50	85533	81111	0	0
T51	12935	12865	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	640	0	0
T2	34110	1	0	0
T3	320269	0	0	0
T5	0	7	0	0
T7	335013	1	0	0
T8	161012	0	0	0
T9	5471	0	0	0
T13	49009	2	0	0
T25	0	1	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T37	0	2	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	0	1	0	0
T54	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	629	0	0
T2	34110	1	0	0
T3	320269	0	0	0
T5	0	7	0	0
T7	335013	1	0	0
T8	161012	0	0	0
T9	5471	0	0	0
T13	49009	2	0	0
T25	0	1	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T37	0	2	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	0	1	0	0
T54	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	617	0	0
T2	34110	1	0	0
T3	320269	0	0	0
T5	0	6	0	0
T7	335013	1	0	0
T8	161012	0	0	0
T9	5471	0	0	0
T13	49009	2	0	0
T25	0	1	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T37	0	2	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	0	1	0	0
T54	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	608	0	0
T2	34110	1	0	0
T3	320269	0	0	0
T5	0	6	0	0
T7	335013	1	0	0
T8	161012	0	0	0
T9	5471	0	0	0
T13	49009	2	0	0
T25	0	1	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T37	0	2	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	0	1	0	0
T54	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	915	0	0
T5	293042	25	0	0
T6	449641	9	0	0
T27	426930	54	0	0
T28	0	1	0	0
T29	0	1	0	0
T35	0	5	0	0
T36	0	3	0	0
T39	435899	0	0	0
T73	0	2	0	0
T82	21370	1	0	0
T85	32490	2	0	0
T87	280341	0	0	0
T88	66603	0	0	0
T89	326922	0	0	0
T90	873126	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	119970	0	0
T5	293042	5583	0	0
T6	449641	1745	0	0
T27	426930	8458	0	0
T28	0	7	0	0
T29	0	2	0	0
T35	0	826	0	0
T36	0	364	0	0
T39	435899	0	0	0
T73	0	222	0	0
T82	21370	429	0	0
T85	32490	106	0	0
T87	280341	0	0	0
T88	66603	0	0	0
T89	326922	0	0	0
T90	873126	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	817	0	0
T5	293042	19	0	0
T6	449641	9	0	0
T27	426930	51	0	0
T28	0	1	0	0
T35	0	5	0	0
T36	0	3	0	0
T39	435899	0	0	0
T43	0	1	0	0
T73	0	1	0	0
T82	21370	1	0	0
T85	32490	2	0	0
T87	280341	0	0	0
T88	66603	0	0	0
T89	326922	0	0	0
T90	873126	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	74	0	0
T5	293042	6	0	0
T6	449641	0	0	0
T27	426930	3	0	0
T39	435899	0	0	0
T60	0	1	0	0
T62	0	2	0	0
T73	0	1	0	0
T82	21370	0	0	0
T85	32490	0	0	0
T87	280341	0	0	0
T88	66603	0	0	0
T89	326922	0	0	0
T90	873126	0	0	0
T93	0	1	0	0
T95	0	1	0	0
T97	0	2	0	0
T99	0	1	0	0
T100	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1480	0	0
T10	21580	193	0	0
T11	0	392	0	0
T12	0	173	0	0
T36	27116	0	0	0
T38	147626	0	0	0
T41	0	365	0	0
T42	0	357	0	0
T43	20125	0	0	0
T44	457176	0	0	0
T45	17348	0	0	0
T46	22328	0	0	0
T47	42197	0	0	0
T48	112498	0	0	0
T49	156080	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1240	0	0
T10	21580	163	0	0
T11	0	332	0	0
T12	0	143	0	0
T36	27116	0	0	0
T38	147626	0	0	0
T41	0	305	0	0
T42	0	297	0	0
T43	20125	0	0	0
T44	457176	0	0	0
T45	17348	0	0	0
T46	22328	0	0	0
T47	42197	0	0	0
T48	112498	0	0	0
T49	156080	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T7

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T34
1	0	1	Covered	T32,T50,T8
1	1	0	Covered	T5,T39,T6
1	1	1	Covered	T1,T25,T26

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T25,T26
0	1	Covered	T5,T6,T48
1	0	Covered	T28,T30,T59

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T25,T26
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T30,T59

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T26
1	0	Covered	T5
1	1	Covered	T5,T6,T48

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T33,T81,T25

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T32
1	Covered	T2,T50,T51

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T50
1	Covered	T3,T32,T81

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T32
1	Covered	T7,T34,T8

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T51,T8

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T32,T50

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T34

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T7,T32

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T15
IdleSt	175	Covered	T15
Phase0St	146	Covered	T15
Phase1St	192	Covered	T15
Phase2St	209	Covered	T15
Phase3St	227	Covered	T15
TerminalSt	243	Covered	T15
TimeoutSt	153	Covered	T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T15
IdleSt->Phase0St	146	Covered	T15
IdleSt->TimeoutSt	153	Covered	T15
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T15
Phase0St->Phase1St	192	Covered	T15
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T15
Phase1St->Phase2St	209	Covered	T15
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T15
Phase2St->Phase3St	227	Covered	T15
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T15
Phase3St->TerminalSt	243	Covered	T15
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T15
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T15
TimeoutSt->Phase0St	166	Covered	T15

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T26
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T105,T31
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T35,T57
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T112,T98
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T96,T100
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T7,T81
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	771781842	287	0	0
CheckAccumTrig0_A	771781842	919	0	0
CheckAccumTrig1_A	771781842	54	0	0
CheckClr_A	771781842	462	0	0
CheckEn_A	771462135	288350537	0	0
CheckPhase0_A	771781842	1057	0	0
CheckPhase1_A	771781842	1033	0	0
CheckPhase2_A	771781842	1005	0	0
CheckPhase3_A	771781842	978	0	0
CheckTimeout0_A	771781842	1219	0	0
CheckTimeoutSt1_A	771781842	136099	0	0
CheckTimeoutSt2_A	771781842	1067	0	0
CheckTimeoutStTrig_A	771781842	98	0	0
ErrorStAllEscAsserted_A	771781842	1394	0	0
ErrorStIsTerminal_A	771781842	1154	0	0
u_state_regs_A	771781842	771606931	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	287	0	0
T10	21580	46	0	0
T11	0	56	0	0
T12	0	36	0	0
T36	27116	0	0	0
T38	147626	0	0	0
T41	0	53	0	0
T42	0	96	0	0
T43	20125	0	0	0
T44	457176	0	0	0
T45	17348	0	0	0
T46	22328	0	0	0
T47	42197	0	0	0
T48	112498	0	0	0
T49	156080	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	919	0	0
T2	34110	1	0	0
T3	320269	1	0	0
T7	335013	1	0	0
T8	161012	1	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T32	121729	1	0	0
T33	0	1	0	0
T34	25239	1	0	0
T50	85533	1	0	0
T51	12935	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	54	0	0
T28	140036	1	0	0
T30	943123	1	0	0
T31	508849	0	0	0
T40	130028	0	0	0
T59	4995	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	3	0	0
T68	0	4	0	0
T72	26590	0	0	0
T74	256098	0	0	0
T75	350559	0	0	0
T76	72573	0	0	0
T80	169558	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	462	0	0
T3	320269	1	0	0
T5	0	8	0	0
T6	0	3	0	0
T7	335013	1	0	0
T8	161012	0	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T27	0	13	0	0
T32	121729	0	0	0
T34	25239	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T48	0	1	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	83631	0	0	0
T81	0	1	0	0
T83	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771462135	288350537	0	0
T1	63500	3034	0	0
T2	34110	8877	0	0
T3	320269	319551	0	0
T7	335013	334575	0	0
T9	5471	5390	0	0
T13	49009	48919	0	0
T32	121729	38941	0	0
T34	25239	839	0	0
T50	85533	2686	0	0
T51	12935	590	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1057	0	0
T2	34110	1	0	0
T3	320269	1	0	0
T7	335013	1	0	0
T8	161012	1	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T32	121729	1	0	0
T33	0	1	0	0
T34	25239	1	0	0
T50	85533	1	0	0
T51	12935	1	0	0
T52	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1033	0	0
T2	34110	1	0	0
T3	320269	1	0	0
T7	335013	1	0	0
T8	161012	1	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T32	121729	1	0	0
T33	0	1	0	0
T34	25239	1	0	0
T50	85533	1	0	0
T51	12935	1	0	0
T52	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1005	0	0
T2	34110	1	0	0
T3	320269	1	0	0
T7	335013	1	0	0
T8	161012	1	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T32	121729	1	0	0
T33	0	1	0	0
T34	25239	1	0	0
T50	85533	1	0	0
T51	12935	1	0	0
T52	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	978	0	0
T2	34110	1	0	0
T3	320269	1	0	0
T7	335013	1	0	0
T8	161012	1	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T32	121729	1	0	0
T33	0	1	0	0
T34	25239	1	0	0
T50	85533	1	0	0
T51	12935	1	0	0
T52	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1219	0	0
T1	63500	1	0	0
T2	34110	0	0	0
T3	320269	0	0	0
T5	0	7	0	0
T6	0	5	0	0
T7	335013	0	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	36	0	0
T28	0	2	0	0
T32	121729	0	0	0
T34	25239	0	0	0
T35	0	3	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T85	0	5	0	0
T86	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	136099	0	0
T1	63500	166	0	0
T2	34110	0	0	0
T3	320269	0	0	0
T5	0	1556	0	0
T6	0	796	0	0
T7	335013	0	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	46	0	0
T26	0	41	0	0
T27	0	4604	0	0
T28	0	651	0	0
T32	121729	0	0	0
T34	25239	0	0	0
T35	0	345	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T85	0	352	0	0
T86	0	539	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1067	0	0
T1	63500	1	0	0
T2	34110	0	0	0
T3	320269	0	0	0
T5	0	5	0	0
T6	0	4	0	0
T7	335013	0	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	36	0	0
T28	0	1	0	0
T32	121729	0	0	0
T34	25239	0	0	0
T35	0	3	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T85	0	5	0	0
T86	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	98	0	0
T5	293042	2	0	0
T6	449641	1	0	0
T27	426930	0	0	0
T39	435899	0	0	0
T48	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T60	0	5	0	0
T82	21370	0	0	0
T85	32490	0	0	0
T87	280341	0	0	0
T88	66603	0	0	0
T89	326922	0	0	0
T90	873126	0	0	0
T94	0	1	0	0
T96	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1394	0	0
T10	21580	182	0	0
T11	0	337	0	0
T12	0	179	0	0
T36	27116	0	0	0
T38	147626	0	0	0
T41	0	311	0	0
T42	0	385	0	0
T43	20125	0	0	0
T44	457176	0	0	0
T45	17348	0	0	0
T46	22328	0	0	0
T47	42197	0	0	0
T48	112498	0	0	0
T49	156080	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1154	0	0
T10	21580	152	0	0
T11	0	277	0	0
T12	0	149	0	0
T36	27116	0	0	0
T38	147626	0	0	0
T41	0	251	0	0
T42	0	325	0	0
T43	20125	0	0	0
T44	457176	0	0	0
T45	17348	0	0	0
T46	22328	0	0	0
T47	42197	0	0	0
T48	112498	0	0	0
T49	156080	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T9
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T7

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T25,T26,T5
1	0	1	Covered	T9,T7,T8
1	1	0	Covered	T25,T5,T6
1	1	1	Covered	T5,T27,T85

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T27,T85
0	1	Covered	T5,T27,T28
1	0	Covered	T5,T40,T92

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T27,T85
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T40,T92

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T85
1	0	Covered	T31
1	1	Covered	T5,T27,T28

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T2,T33,T5

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T7,T52,T5

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T3,T53,T25

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T3,T8,T54

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T7,T8

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T7,T53

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T8,T53

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T8,T33

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T15
IdleSt	175	Covered	T15
Phase0St	146	Covered	T15
Phase1St	192	Covered	T15
Phase2St	209	Covered	T15
Phase3St	227	Covered	T15
TerminalSt	243	Covered	T15
TimeoutSt	153	Covered	T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T15
IdleSt->Phase0St	146	Covered	T15
IdleSt->TimeoutSt	153	Covered	T15
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T15
Phase0St->Phase1St	192	Covered	T15
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T15
Phase1St->Phase2St	209	Covered	T15
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T15
Phase2St->Phase3St	227	Covered	T15
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T15
Phase3St->TerminalSt	243	Covered	T15
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T15
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T15
TimeoutSt->Phase0St	166	Covered	T15

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T27,T85
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T27,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T27,T85
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T27,T85
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T113,T114,T115
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T116,T117,T102
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T31,T62
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T7,T5,T112
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T8,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	771781842	265	0	0
CheckAccumTrig0_A	771781842	584	0	0
CheckAccumTrig1_A	771781842	26	0	0
CheckClr_A	771781842	274	0	0
CheckEn_A	771462135	311117169	0	0
CheckPhase0_A	771781842	689	0	0
CheckPhase1_A	771781842	680	0	0
CheckPhase2_A	771781842	665	0	0
CheckPhase3_A	771781842	652	0	0
CheckTimeout0_A	771781842	1075	0	0
CheckTimeoutSt1_A	771781842	150855	0	0
CheckTimeoutSt2_A	771781842	956	0	0
CheckTimeoutStTrig_A	771781842	93	0	0
ErrorStAllEscAsserted_A	771781842	1433	0	0
ErrorStIsTerminal_A	771781842	1193	0	0
u_state_regs_A	771781842	771606931	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	265	0	0
T10	21580	31	0	0
T11	0	67	0	0
T12	0	35	0	0
T36	27116	0	0	0
T38	147626	0	0	0
T41	0	65	0	0
T42	0	67	0	0
T43	20125	0	0	0
T44	457176	0	0	0
T45	17348	0	0	0
T46	22328	0	0	0
T47	42197	0	0	0
T48	112498	0	0	0
T49	156080	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	584	0	0
T2	34110	1	0	0
T3	320269	5	0	0
T7	335013	1	0	0
T8	161012	2	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	26	0	0
T5	293042	1	0	0
T6	449641	0	0	0
T27	426930	0	0	0
T39	435899	0	0	0
T40	0	2	0	0
T64	0	1	0	0
T71	0	1	0	0
T82	21370	0	0	0
T85	32490	0	0	0
T87	280341	0	0	0
T88	66603	0	0	0
T89	326922	0	0	0
T90	873126	0	0	0
T92	0	1	0	0
T94	0	1	0	0
T106	0	2	0	0
T118	0	2	0	0
T119	0	4	0	0
T120	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	274	0	0
T3	320269	4	0	0
T5	0	10	0	0
T6	0	1	0	0
T7	335013	1	0	0
T8	161012	1	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T30	0	1	0	0
T32	121729	0	0	0
T34	25239	0	0	0
T40	0	3	0	0
T48	0	1	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	83631	0	0	0
T56	0	3	0	0
T116	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771462135	311117169	0	0
T1	63500	63448	0	0
T2	34110	5395	0	0
T3	320269	3082	0	0
T7	335013	333664	0	0
T9	5471	2787	0	0
T13	49009	48919	0	0
T32	121729	121635	0	0
T34	25239	25144	0	0
T50	85533	81111	0	0
T51	12935	12865	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	689	0	0
T2	34110	1	0	0
T3	320269	5	0	0
T7	335013	1	0	0
T8	161012	2	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	680	0	0
T2	34110	1	0	0
T3	320269	5	0	0
T7	335013	1	0	0
T8	161012	2	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	665	0	0
T2	34110	1	0	0
T3	320269	5	0	0
T7	335013	1	0	0
T8	161012	2	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	652	0	0
T2	34110	1	0	0
T3	320269	5	0	0
T5	0	10	0	0
T7	335013	0	0	0
T8	161012	2	0	0
T9	5471	0	0	0
T13	49009	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T32	121729	0	0	0
T33	0	1	0	0
T34	25239	0	0	0
T50	85533	0	0	0
T51	12935	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1075	0	0
T5	293042	11	0	0
T6	449641	0	0	0
T27	426930	2	0	0
T28	0	1	0	0
T30	0	3	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	435899	0	0	0
T40	0	18	0	0
T48	0	2	0	0
T73	0	1	0	0
T82	21370	0	0	0
T85	32490	8	0	0
T87	280341	0	0	0
T88	66603	0	0	0
T89	326922	0	0	0
T90	873126	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	150855	0	0
T5	293042	1427	0	0
T6	449641	0	0	0
T27	426930	467	0	0
T28	0	643	0	0
T30	0	1107	0	0
T35	0	221	0	0
T36	0	255	0	0
T39	435899	0	0	0
T40	0	1242	0	0
T48	0	111	0	0
T73	0	215	0	0
T82	21370	0	0	0
T85	32490	488	0	0
T87	280341	0	0	0
T88	66603	0	0	0
T89	326922	0	0	0
T90	873126	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	956	0	0
T5	293042	4	0	0
T6	449641	0	0	0
T27	426930	1	0	0
T30	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	435899	0	0	0
T40	0	15	0	0
T48	0	1	0	0
T73	0	1	0	0
T82	21370	0	0	0
T85	32490	8	0	0
T87	280341	0	0	0
T88	66603	0	0	0
T89	326922	0	0	0
T90	873126	0	0	0
T91	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	93	0	0
T5	293042	6	0	0
T6	449641	0	0	0
T27	426930	1	0	0
T28	0	1	0	0
T30	0	1	0	0
T31	0	4	0	0
T39	435899	0	0	0
T40	0	1	0	0
T48	0	1	0	0
T82	21370	0	0	0
T85	32490	0	0	0
T87	280341	0	0	0
T88	66603	0	0	0
T89	326922	0	0	0
T90	873126	0	0	0
T95	0	3	0	0
T97	0	2	0	0
T121	0	4	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1433	0	0
T10	21580	162	0	0
T11	0	370	0	0
T12	0	167	0	0
T36	27116	0	0	0
T38	147626	0	0	0
T41	0	388	0	0
T42	0	346	0	0
T43	20125	0	0	0
T44	457176	0	0	0
T45	17348	0	0	0
T46	22328	0	0	0
T47	42197	0	0	0
T48	112498	0	0	0
T49	156080	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	1193	0	0
T10	21580	132	0	0
T11	0	310	0	0
T12	0	137	0	0
T36	27116	0	0	0
T38	147626	0	0	0
T41	0	328	0	0
T42	0	286	0	0
T43	20125	0	0	0
T44	457176	0	0	0
T45	17348	0	0	0
T46	22328	0	0	0
T47	42197	0	0	0
T48	112498	0	0	0
T49	156080	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771781842	771606931	0	0
T1	63500	63449	0	0
T2	34110	34016	0	0
T3	320269	320261	0	0
T7	335013	335005	0	0
T9	5471	5391	0	0
T13	49009	48920	0	0
T32	121729	121636	0	0
T34	25239	25145	0	0
T50	85533	85477	0	0
T51	12935	12866	0	0