Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T214,T215,T216
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T5

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13032	0	0
DisabledNoTrigBkwd_A	2147483647	920944	0	0
DisabledNoTrigFwd_A	2147483647	1775658324	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13032	0	0
T116	180623	0	0	0
T125	55379	0	0	0
T214	1619	672	0	0
T215	2346	215	0	0
T216	0	706	0	0
T217	0	328	0	0
T218	2101	936	0	0
T219	1223	426	0	0
T220	0	498	0	0
T221	0	992	0	0
T222	3279	952	0	0
T223	0	1396	0	0
T224	0	768	0	0
T225	0	385	0	0
T226	0	586	0	0
T227	0	1067	0	0
T228	0	949	0	0
T229	0	202	0	0
T230	0	713	0	0
T231	0	246	0	0
T232	0	221	0	0
T233	0	774	0	0
T234	1245	0	0	0
T235	301912	0	0	0
T236	73171	0	0	0
T237	162066	0	0	0
T238	27363	0	0	0
T239	63692	0	0	0
T240	108538	0	0	0
T241	7665	0	0	0
T242	379836	0	0	0
T243	81068	0	0	0
T244	335162	0	0	0
T245	579983	0	0	0
T246	7509	0	0	0
T247	97655	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	920944	0	0
T4	763028	1726	0	0
T5	2177844	4440	0	0
T6	506780	6469	0	0
T7	67227	5	0	0
T8	652768	4	0	0
T9	0	2	0	0
T11	0	9	0	0
T12	0	10	0	0
T19	187432	6	0	0
T20	75268	0	0	0
T21	1135488	182	0	0
T22	19588	0	0	0
T23	671124	3921	0	0
T24	61923	14	0	0
T25	0	571	0	0
T40	0	6	0	0
T57	0	682	0	0
T58	0	61	0	0
T59	0	4	0	0
T60	0	27	0	0
T64	0	11	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1775658324	0	0
T1	77400	27446	0	0
T2	24696	18507	0	0
T3	113132	55407	0	0
T4	763028	2024645	0	0
T5	2177844	2012468	0	0
T6	506780	142507	0	0
T7	268908	197772	0	0
T19	187432	143374	0	0
T20	75268	64290	0	0
T21	1135488	826701	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T3,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T218,T219,T222
1	1	Covered	T1,T3,T7

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	790843828	2737	0	0
DisabledNoTrigBkwd_A	790843828	273149	0	0
DisabledNoTrigFwd_A	790843828	380465690	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790843828	2737	0	0
T125	55379	0	0	0
T218	2101	936	0	0
T219	1223	426	0	0
T222	3279	952	0	0
T229	0	202	0	0
T232	0	221	0	0
T242	379836	0	0	0
T243	81068	0	0	0
T244	335162	0	0	0
T245	579983	0	0	0
T246	7509	0	0	0
T247	97655	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790843828	273149	0	0
T4	190757	917	0	0
T5	544461	3950	0	0
T6	126695	1787	0	0
T7	67227	5	0	0
T8	163192	3	0	0
T9	0	1	0	0
T19	46858	0	0	0
T20	18817	0	0	0
T21	283872	182	0	0
T22	4897	0	0	0
T23	167781	836	0	0
T24	0	14	0	0
T58	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790843828	380465690	0	0
T1	19350	582	0	0
T2	6174	6083	0	0
T3	28283	9337	0	0
T4	190757	614654	0	0
T5	544461	975695	0	0
T6	126695	1608	0	0
T7	67227	61177	0	0
T19	46858	46764	0	0
T20	18817	17727	0	0
T21	283872	17224	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T215,T216,T220
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	790843828	4455	0	0
DisabledNoTrigBkwd_A	790843828	218782	0	0
DisabledNoTrigFwd_A	790843828	459368768	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790843828	4455	0	0
T116	180623	0	0	0
T215	2346	215	0	0
T216	0	706	0	0
T220	0	498	0	0
T227	0	1067	0	0
T228	0	949	0	0
T231	0	246	0	0
T233	0	774	0	0
T234	1245	0	0	0
T235	301912	0	0	0
T236	73171	0	0	0
T237	162066	0	0	0
T238	27363	0	0	0
T239	63692	0	0	0
T240	108538	0	0	0
T241	7665	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790843828	218782	0	0
T4	190757	167	0	0
T5	544461	81	0	0
T6	126695	2567	0	0
T8	163192	0	0	0
T19	46858	0	0	0
T20	18817	0	0	0
T21	283872	0	0	0
T22	4897	0	0	0
T23	167781	0	0	0
T24	20641	0	0	0
T25	0	571	0	0
T40	0	3	0	0
T57	0	71	0	0
T58	0	5	0	0
T59	0	2	0	0
T60	0	26	0	0
T64	0	11	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790843828	459368768	0	0
T1	19350	4504	0	0
T2	6174	3165	0	0
T3	28283	9229	0	0
T4	190757	827542	0	0
T5	544461	383086	0	0
T6	126695	3066	0	0
T7	67227	2257	0	0
T19	46858	46764	0	0
T20	18817	14718	0	0
T21	283872	253255	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T214,T217,T223
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	790843828	4848	0	0
DisabledNoTrigBkwd_A	790843828	205423	0	0
DisabledNoTrigFwd_A	790843828	498331021	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790843828	4848	0	0
T89	461352	0	0	0
T97	36384	0	0	0
T98	120220	0	0	0
T109	865872	0	0	0
T212	1743	0	0	0
T214	1619	672	0	0
T217	0	328	0	0
T223	0	1396	0	0
T224	0	768	0	0
T225	0	385	0	0
T226	0	586	0	0
T230	0	713	0	0
T248	7459	0	0	0
T249	654898	0	0	0
T250	15784	0	0	0
T251	127882	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790843828	205423	0	0
T4	190757	418	0	0
T5	544461	409	0	0
T6	126695	0	0	0
T8	163192	1	0	0
T11	0	3	0	0
T12	0	10	0	0
T19	46858	1	0	0
T20	18817	0	0	0
T21	283872	0	0	0
T22	4897	0	0	0
T23	167781	1480	0	0
T24	20641	0	0	0
T57	0	599	0	0
T58	0	30	0	0
T60	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790843828	498331021	0	0
T1	19350	4199	0	0
T2	6174	3176	0	0
T3	28283	22034	0	0
T4	190757	449728	0	0
T5	544461	110055	0	0
T6	126695	126541	0	0
T7	67227	67169	0	0
T19	46858	39873	0	0
T20	18817	13115	0	0
T21	283872	278110	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T221
1	1	Covered	T1,T3,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T19,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	790843828	992	0	0
DisabledNoTrigBkwd_A	790843828	223590	0	0
DisabledNoTrigFwd_A	790843828	437492845	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790843828	992	0	0
T80	213522	0	0	0
T221	1786	992	0	0
T252	16589	0	0	0
T253	539584	0	0	0
T254	16184	0	0	0
T255	194141	0	0	0
T256	8926	0	0	0
T257	363731	0	0	0
T258	45568	0	0	0
T259	18248	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790843828	223590	0	0
T4	190757	224	0	0
T5	544461	0	0	0
T6	126695	2115	0	0
T8	163192	0	0	0
T9	0	1	0	0
T11	0	6	0	0
T19	46858	5	0	0
T20	18817	0	0	0
T21	283872	0	0	0
T22	4897	0	0	0
T23	167781	1605	0	0
T24	20641	0	0	0
T40	0	3	0	0
T57	0	12	0	0
T58	0	23	0	0
T59	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790843828	437492845	0	0
T1	19350	18161	0	0
T2	6174	6083	0	0
T3	28283	14807	0	0
T4	190757	132721	0	0
T5	544461	543632	0	0
T6	126695	11292	0	0
T7	67227	67169	0	0
T19	46858	9973	0	0
T20	18817	18730	0	0
T21	283872	278112	0	0