Line Coverage for Module :
alert_handler_esc_timer
| Line No. | Total | Covered | Percent |
TOTAL | | 101 | 101 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
ALWAYS | 128 | 89 | 89 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
ALWAYS | 299 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
79 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
138 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
151 |
1 |
1 |
152 |
1 |
1 |
153 |
1 |
1 |
|
|
|
MISSING_ELSE |
163 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
172 |
1 |
1 |
173 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
181 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
201 |
1 |
1 |
202 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
208 |
1 |
1 |
209 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
226 |
1 |
1 |
227 |
1 |
1 |
228 |
1 |
1 |
|
|
|
MISSING_ELSE |
232 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
238 |
1 |
1 |
239 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
243 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
|
|
|
MISSING_ELSE |
252 |
1 |
1 |
253 |
1 |
1 |
254 |
1 |
1 |
255 |
1 |
1 |
|
|
|
MISSING_ELSE |
262 |
1 |
1 |
263 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
279 |
1 |
1 |
|
|
|
MISSING_ELSE |
286 |
4 |
4 |
289 |
4 |
4 |
299 |
3 |
3 |
Cond Coverage for Module :
alert_handler_esc_timer
| Total | Covered | Percent |
Conditions | 47 | 44 | 93.62 |
Logical | 47 | 44 | 93.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 61
EXPRESSION (cnt_clr && ((!cnt_en)))
---1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 61
EXPRESSION (cnt_clr && cnt_en)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T7 |
LINE 145
EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T35 |
1 | 1 | 1 | Covered | T7,T4,T5 |
LINE 151
EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
------1----- -----2----- --3-
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T5,T19 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 165
EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
-----------------1----------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T3,T5,T21 |
1 | 0 | Covered | T4,T5,T23 |
LINE 165
SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T23 |
LINE 165
SUB-EXPRESSION (cnt_ge && timeout_en_i)
---1-- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T36 |
1 | 1 | Covered | T3,T5,T21 |
LINE 185
EXPRESSION (crashdump_phase_i == 2'b0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T7,T4,T5 |
LINE 202
EXPRESSION (crashdump_phase_i == 2'b1)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T7,T4 |
1 | Covered | T4,T5,T19 |
LINE 219
EXPRESSION (crashdump_phase_i == 2'b10)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T7,T4 |
1 | Covered | T3,T4,T5 |
LINE 236
EXPRESSION (crashdump_phase_i == 2'b11)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T7,T4 |
1 | Covered | T4,T5,T21 |
LINE 277
EXPRESSION (accu_fail_i || cnt_error)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T13,T14,T15 |
LINE 289
EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T4,T5,T21 |
LINE 289
EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T7,T4,T5 |
LINE 289
EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T3,T4,T5 |
LINE 289
EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T3,T7,T4 |
FSM Coverage for Module :
alert_handler_esc_timer
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
8 |
8 |
100.00 |
(Not included in score) |
Transitions |
20 |
14 |
70.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
FsmErrorSt |
278 |
Covered |
T16 |
IdleSt |
175 |
Covered |
T16 |
Phase0St |
146 |
Covered |
T16 |
Phase1St |
192 |
Covered |
T16 |
Phase2St |
209 |
Covered |
T16 |
Phase3St |
227 |
Covered |
T16 |
TerminalSt |
243 |
Covered |
T16 |
TimeoutSt |
153 |
Covered |
T16 |
transitions | Line No. | Covered | Tests |
IdleSt->FsmErrorSt |
278 |
Covered |
T16 |
IdleSt->Phase0St |
146 |
Covered |
T16 |
IdleSt->TimeoutSt |
153 |
Covered |
T16 |
Phase0St->FsmErrorSt |
278 |
Not Covered |
|
Phase0St->IdleSt |
188 |
Covered |
T16 |
Phase0St->Phase1St |
192 |
Covered |
T16 |
Phase1St->FsmErrorSt |
278 |
Not Covered |
|
Phase1St->IdleSt |
205 |
Covered |
T16 |
Phase1St->Phase2St |
209 |
Covered |
T16 |
Phase2St->FsmErrorSt |
278 |
Not Covered |
|
Phase2St->IdleSt |
223 |
Covered |
T16 |
Phase2St->Phase3St |
227 |
Covered |
T16 |
Phase3St->FsmErrorSt |
278 |
Not Covered |
|
Phase3St->IdleSt |
239 |
Covered |
T16 |
Phase3St->TerminalSt |
243 |
Covered |
T16 |
TerminalSt->FsmErrorSt |
278 |
Not Covered |
|
TerminalSt->IdleSt |
255 |
Covered |
T16 |
TimeoutSt->FsmErrorSt |
278 |
Not Covered |
|
TimeoutSt->IdleSt |
175 |
Covered |
T16 |
TimeoutSt->Phase0St |
166 |
Covered |
T16 |
Branch Coverage for Module :
alert_handler_esc_timer
| Line No. | Total | Covered | Percent |
Branches |
|
26 |
26 |
100.00 |
CASE |
138 |
22 |
22 |
100.00 |
IF |
277 |
2 |
2 |
100.00 |
IF |
299 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 case (state_q)
-2-: 145 if (((accu_trig_i && en_i) && (!clr_i)))
-3-: 151 if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-: 165 if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-: 172 if (timeout_en_i)
-6-: 187 if (clr_i)
-7-: 191 if (cnt_ge)
-8-: 204 if (clr_i)
-9-: 208 if (cnt_ge)
-10-: 222 if (clr_i)
-11-: 226 if (cnt_ge)
-12-: 238 if (clr_i)
-13-: 242 if (cnt_ge)
-14-: 254 if (clr_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T4,T5 |
IdleSt |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
IdleSt |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
TimeoutSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T4,T5 |
TimeoutSt |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
TimeoutSt |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T5 |
Phase0St |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T37,T38,T39 |
Phase0St |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T7,T4 |
Phase0St |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T7,T4 |
Phase1St |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T6,T23,T40 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T3,T7,T4 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T3,T7,T4 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T41,T42,T43 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
Covered |
T3,T7,T4 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
Covered |
T3,T7,T4 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T18,T44,T45 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T3,T7,T4 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T3,T7,T4 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T3,T7,T4 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T3,T7,T4 |
FsmErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T14,T15 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T14,T15 |
LineNo. Expression
-1-: 277 if ((accu_fail_i || cnt_error))
Branches:
-1- | Status | Tests |
1 |
Covered |
T13,T14,T15 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 299 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
alert_handler_esc_timer
Assertion Details
AccuFailToFsmError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
813 |
0 |
0 |
T13 |
85368 |
96 |
0 |
0 |
T14 |
0 |
139 |
0 |
0 |
T15 |
0 |
159 |
0 |
0 |
T46 |
0 |
155 |
0 |
0 |
T47 |
0 |
264 |
0 |
0 |
T48 |
2150756 |
0 |
0 |
0 |
T49 |
82876 |
0 |
0 |
0 |
T50 |
512492 |
0 |
0 |
0 |
T51 |
1009124 |
0 |
0 |
0 |
T52 |
1014912 |
0 |
0 |
0 |
T53 |
3694664 |
0 |
0 |
0 |
T54 |
141684 |
0 |
0 |
0 |
T55 |
3775700 |
0 |
0 |
0 |
T56 |
83512 |
0 |
0 |
0 |
CheckAccumTrig0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2609 |
0 |
0 |
T4 |
763028 |
13 |
0 |
0 |
T5 |
2177844 |
15 |
0 |
0 |
T6 |
506780 |
4 |
0 |
0 |
T7 |
67227 |
1 |
0 |
0 |
T8 |
652768 |
2 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T19 |
187432 |
1 |
0 |
0 |
T20 |
75268 |
0 |
0 |
0 |
T21 |
1135488 |
1 |
0 |
0 |
T22 |
19588 |
0 |
0 |
0 |
T23 |
671124 |
15 |
0 |
0 |
T24 |
61923 |
1 |
0 |
0 |
T25 |
0 |
7 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T57 |
0 |
2 |
0 |
0 |
T58 |
0 |
2 |
0 |
0 |
T59 |
0 |
2 |
0 |
0 |
T60 |
0 |
2 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T62 |
0 |
1 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
CheckAccumTrig1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
117 |
0 |
0 |
T4 |
190757 |
1 |
0 |
0 |
T5 |
1088922 |
1 |
0 |
0 |
T6 |
253390 |
0 |
0 |
0 |
T8 |
326384 |
0 |
0 |
0 |
T19 |
93716 |
0 |
0 |
0 |
T20 |
37634 |
0 |
0 |
0 |
T21 |
567744 |
0 |
0 |
0 |
T22 |
9794 |
0 |
0 |
0 |
T23 |
335562 |
2 |
0 |
0 |
T24 |
41282 |
1 |
0 |
0 |
T38 |
396969 |
0 |
0 |
0 |
T57 |
67859 |
0 |
0 |
0 |
T64 |
30307 |
1 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T66 |
168201 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
1 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T72 |
0 |
1 |
0 |
0 |
T73 |
0 |
1 |
0 |
0 |
T74 |
0 |
1 |
0 |
0 |
T75 |
0 |
1 |
0 |
0 |
T76 |
0 |
1 |
0 |
0 |
T77 |
0 |
2 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T79 |
0 |
1 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T81 |
21614 |
0 |
0 |
0 |
T82 |
242567 |
0 |
0 |
0 |
T83 |
374326 |
0 |
0 |
0 |
T84 |
94059 |
0 |
0 |
0 |
T85 |
13975 |
0 |
0 |
0 |
T86 |
307942 |
0 |
0 |
0 |
T87 |
123102 |
0 |
0 |
0 |
CheckClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1240 |
0 |
0 |
T3 |
56566 |
1 |
0 |
0 |
T4 |
572271 |
3 |
0 |
0 |
T5 |
2177844 |
4 |
0 |
0 |
T6 |
506780 |
1 |
0 |
0 |
T7 |
134454 |
1 |
0 |
0 |
T8 |
326384 |
1 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T19 |
187432 |
1 |
0 |
0 |
T20 |
75268 |
0 |
0 |
0 |
T21 |
1135488 |
0 |
0 |
0 |
T22 |
19588 |
0 |
0 |
0 |
T23 |
671124 |
6 |
0 |
0 |
T24 |
41282 |
1 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T57 |
67859 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T81 |
0 |
2 |
0 |
0 |
T88 |
0 |
1 |
0 |
0 |
T89 |
0 |
2 |
0 |
0 |
T90 |
0 |
2 |
0 |
0 |
T91 |
0 |
2 |
0 |
0 |
T92 |
0 |
2 |
0 |
0 |
T93 |
0 |
1 |
0 |
0 |
CheckEn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1450968816 |
0 |
0 |
T1 |
77400 |
27445 |
0 |
0 |
T2 |
24696 |
18505 |
0 |
0 |
T3 |
113132 |
55404 |
0 |
0 |
T4 |
763028 |
2024635 |
0 |
0 |
T5 |
2177844 |
1113372 |
0 |
0 |
T6 |
506780 |
139057 |
0 |
0 |
T7 |
268908 |
197769 |
0 |
0 |
T19 |
187432 |
143371 |
0 |
0 |
T20 |
75268 |
64287 |
0 |
0 |
T21 |
1135488 |
731167 |
0 |
0 |
CheckPhase0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2926 |
0 |
0 |
T3 |
56566 |
2 |
0 |
0 |
T4 |
763028 |
14 |
0 |
0 |
T5 |
2177844 |
18 |
0 |
0 |
T6 |
506780 |
4 |
0 |
0 |
T7 |
134454 |
1 |
0 |
0 |
T8 |
326384 |
2 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T19 |
187432 |
2 |
0 |
0 |
T20 |
75268 |
0 |
0 |
0 |
T21 |
1135488 |
2 |
0 |
0 |
T22 |
19588 |
0 |
0 |
0 |
T23 |
671124 |
18 |
0 |
0 |
T24 |
41282 |
2 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T57 |
0 |
3 |
0 |
0 |
T58 |
0 |
4 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
3 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
CheckPhase1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2870 |
0 |
0 |
T3 |
56566 |
2 |
0 |
0 |
T4 |
763028 |
14 |
0 |
0 |
T5 |
2177844 |
18 |
0 |
0 |
T6 |
506780 |
3 |
0 |
0 |
T7 |
134454 |
1 |
0 |
0 |
T8 |
326384 |
2 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T19 |
187432 |
2 |
0 |
0 |
T20 |
75268 |
0 |
0 |
0 |
T21 |
1135488 |
2 |
0 |
0 |
T22 |
19588 |
0 |
0 |
0 |
T23 |
671124 |
17 |
0 |
0 |
T24 |
41282 |
2 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T57 |
0 |
3 |
0 |
0 |
T58 |
0 |
4 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
3 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
CheckPhase2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2822 |
0 |
0 |
T3 |
56566 |
2 |
0 |
0 |
T4 |
763028 |
14 |
0 |
0 |
T5 |
2177844 |
18 |
0 |
0 |
T6 |
506780 |
3 |
0 |
0 |
T7 |
134454 |
1 |
0 |
0 |
T8 |
326384 |
2 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T19 |
187432 |
2 |
0 |
0 |
T20 |
75268 |
0 |
0 |
0 |
T21 |
1135488 |
2 |
0 |
0 |
T22 |
19588 |
0 |
0 |
0 |
T23 |
671124 |
17 |
0 |
0 |
T24 |
41282 |
2 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T57 |
0 |
3 |
0 |
0 |
T58 |
0 |
4 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
3 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
CheckPhase3_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2748 |
0 |
0 |
T3 |
56566 |
2 |
0 |
0 |
T4 |
763028 |
14 |
0 |
0 |
T5 |
2177844 |
18 |
0 |
0 |
T6 |
506780 |
3 |
0 |
0 |
T7 |
134454 |
1 |
0 |
0 |
T8 |
326384 |
2 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T19 |
187432 |
2 |
0 |
0 |
T20 |
75268 |
0 |
0 |
0 |
T21 |
1135488 |
2 |
0 |
0 |
T22 |
19588 |
0 |
0 |
0 |
T23 |
671124 |
17 |
0 |
0 |
T24 |
41282 |
2 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T57 |
0 |
3 |
0 |
0 |
T58 |
0 |
4 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
3 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
CheckTimeout0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
3995 |
0 |
0 |
T1 |
77400 |
15 |
0 |
0 |
T2 |
24696 |
0 |
0 |
0 |
T3 |
113132 |
5 |
0 |
0 |
T4 |
763028 |
1 |
0 |
0 |
T5 |
2177844 |
171 |
0 |
0 |
T6 |
506780 |
0 |
0 |
0 |
T7 |
268908 |
0 |
0 |
0 |
T18 |
0 |
8 |
0 |
0 |
T19 |
187432 |
1 |
0 |
0 |
T20 |
75268 |
0 |
0 |
0 |
T21 |
1135488 |
14 |
0 |
0 |
T22 |
0 |
1 |
0 |
0 |
T23 |
0 |
3 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
2 |
0 |
0 |
T60 |
0 |
47 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
T94 |
0 |
18 |
0 |
0 |
T95 |
0 |
21 |
0 |
0 |
T96 |
0 |
1 |
0 |
0 |
CheckTimeoutSt1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
438978 |
0 |
0 |
T1 |
77400 |
1599 |
0 |
0 |
T2 |
24696 |
0 |
0 |
0 |
T3 |
113132 |
779 |
0 |
0 |
T4 |
763028 |
21 |
0 |
0 |
T5 |
2177844 |
17426 |
0 |
0 |
T6 |
506780 |
0 |
0 |
0 |
T7 |
268908 |
0 |
0 |
0 |
T18 |
0 |
1751 |
0 |
0 |
T19 |
187432 |
313 |
0 |
0 |
T20 |
75268 |
0 |
0 |
0 |
T21 |
1135488 |
2393 |
0 |
0 |
T22 |
0 |
123 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
2 |
0 |
0 |
T40 |
0 |
67 |
0 |
0 |
T41 |
0 |
25 |
0 |
0 |
T57 |
0 |
212 |
0 |
0 |
T58 |
0 |
969 |
0 |
0 |
T60 |
0 |
4449 |
0 |
0 |
T64 |
0 |
2 |
0 |
0 |
T94 |
0 |
2945 |
0 |
0 |
T95 |
0 |
2652 |
0 |
0 |
T96 |
0 |
35 |
0 |
0 |
CheckTimeoutSt2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
3621 |
0 |
0 |
T1 |
77400 |
15 |
0 |
0 |
T2 |
24696 |
0 |
0 |
0 |
T3 |
113132 |
3 |
0 |
0 |
T4 |
763028 |
0 |
0 |
0 |
T5 |
2177844 |
168 |
0 |
0 |
T6 |
506780 |
0 |
0 |
0 |
T7 |
268908 |
0 |
0 |
0 |
T18 |
0 |
13 |
0 |
0 |
T19 |
187432 |
0 |
0 |
0 |
T20 |
75268 |
0 |
0 |
0 |
T21 |
1135488 |
13 |
0 |
0 |
T22 |
0 |
1 |
0 |
0 |
T25 |
0 |
3 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T60 |
0 |
44 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T62 |
0 |
11 |
0 |
0 |
T65 |
0 |
16 |
0 |
0 |
T91 |
0 |
2 |
0 |
0 |
T93 |
0 |
1 |
0 |
0 |
T94 |
0 |
18 |
0 |
0 |
T95 |
0 |
21 |
0 |
0 |
T96 |
0 |
1 |
0 |
0 |
T97 |
0 |
2 |
0 |
0 |
T98 |
0 |
4 |
0 |
0 |
T99 |
0 |
1 |
0 |
0 |
CheckTimeoutStTrig_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
254 |
0 |
0 |
T3 |
56566 |
1 |
0 |
0 |
T4 |
381514 |
0 |
0 |
0 |
T5 |
1633383 |
2 |
0 |
0 |
T6 |
380085 |
0 |
0 |
0 |
T7 |
134454 |
0 |
0 |
0 |
T8 |
326384 |
0 |
0 |
0 |
T9 |
474054 |
0 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T19 |
140574 |
0 |
0 |
0 |
T20 |
56451 |
0 |
0 |
0 |
T21 |
1135488 |
1 |
0 |
0 |
T22 |
19588 |
0 |
0 |
0 |
T23 |
671124 |
0 |
0 |
0 |
T24 |
41282 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T57 |
135718 |
0 |
0 |
0 |
T58 |
23401 |
1 |
0 |
0 |
T60 |
0 |
2 |
0 |
0 |
T62 |
0 |
5 |
0 |
0 |
T64 |
30307 |
0 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T94 |
111065 |
0 |
0 |
0 |
T98 |
0 |
2 |
0 |
0 |
T100 |
0 |
3 |
0 |
0 |
T101 |
0 |
2 |
0 |
0 |
T102 |
0 |
1 |
0 |
0 |
T103 |
0 |
1 |
0 |
0 |
T104 |
0 |
2 |
0 |
0 |
T105 |
0 |
4 |
0 |
0 |
T106 |
0 |
3 |
0 |
0 |
T107 |
0 |
1 |
0 |
0 |
ErrorStAllEscAsserted_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
4342 |
0 |
0 |
T13 |
85368 |
693 |
0 |
0 |
T14 |
0 |
730 |
0 |
0 |
T15 |
0 |
706 |
0 |
0 |
T46 |
0 |
736 |
0 |
0 |
T47 |
0 |
1477 |
0 |
0 |
T48 |
2150756 |
0 |
0 |
0 |
T49 |
82876 |
0 |
0 |
0 |
T50 |
512492 |
0 |
0 |
0 |
T51 |
1009124 |
0 |
0 |
0 |
T52 |
1014912 |
0 |
0 |
0 |
T53 |
3694664 |
0 |
0 |
0 |
T54 |
141684 |
0 |
0 |
0 |
T55 |
3775700 |
0 |
0 |
0 |
T56 |
83512 |
0 |
0 |
0 |
ErrorStIsTerminal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
3622 |
0 |
0 |
T13 |
85368 |
573 |
0 |
0 |
T14 |
0 |
610 |
0 |
0 |
T15 |
0 |
586 |
0 |
0 |
T46 |
0 |
616 |
0 |
0 |
T47 |
0 |
1237 |
0 |
0 |
T48 |
2150756 |
0 |
0 |
0 |
T49 |
82876 |
0 |
0 |
0 |
T50 |
512492 |
0 |
0 |
0 |
T51 |
1009124 |
0 |
0 |
0 |
T52 |
1014912 |
0 |
0 |
0 |
T53 |
3694664 |
0 |
0 |
0 |
T54 |
141684 |
0 |
0 |
0 |
T55 |
3775700 |
0 |
0 |
0 |
T56 |
83512 |
0 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
77400 |
77072 |
0 |
0 |
T2 |
24696 |
24332 |
0 |
0 |
T3 |
113132 |
112780 |
0 |
0 |
T4 |
763028 |
762992 |
0 |
0 |
T5 |
2177844 |
2177756 |
0 |
0 |
T6 |
506780 |
506748 |
0 |
0 |
T7 |
268908 |
268676 |
0 |
0 |
T19 |
187432 |
187056 |
0 |
0 |
T20 |
75268 |
74920 |
0 |
0 |
T21 |
1135488 |
1134652 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
| Line No. | Total | Covered | Percent |
TOTAL | | 101 | 101 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
ALWAYS | 128 | 89 | 89 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
ALWAYS | 299 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
79 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
138 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
151 |
1 |
1 |
152 |
1 |
1 |
153 |
1 |
1 |
|
|
|
MISSING_ELSE |
163 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
172 |
1 |
1 |
173 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
181 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
201 |
1 |
1 |
202 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
208 |
1 |
1 |
209 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
226 |
1 |
1 |
227 |
1 |
1 |
228 |
1 |
1 |
|
|
|
MISSING_ELSE |
232 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
238 |
1 |
1 |
239 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
243 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
|
|
|
MISSING_ELSE |
252 |
1 |
1 |
253 |
1 |
1 |
254 |
1 |
1 |
255 |
1 |
1 |
|
|
|
MISSING_ELSE |
262 |
1 |
1 |
263 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
279 |
1 |
1 |
|
|
|
MISSING_ELSE |
286 |
4 |
4 |
289 |
4 |
4 |
299 |
3 |
3 |
Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
| Total | Covered | Percent |
Conditions | 45 | 42 | 93.33 |
Logical | 45 | 42 | 93.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 61
EXPRESSION (cnt_clr && ((!cnt_en)))
---1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 61
EXPRESSION (cnt_clr && cnt_en)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T7 |
LINE 145
EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T3,T7 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T7,T4,T5 |
LINE 151
EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
------1----- -----2----- --3-
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T4,T5,T23 |
1 | 1 | 0 | Covered | T3,T4,T5 |
1 | 1 | 1 | Covered | T1,T3,T5 |
LINE 165
EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
-----------------1----------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T5 |
0 | 1 | Covered | T3,T5,T60 |
1 | 0 | Covered | T5,T23,T24 |
LINE 165
SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T3,T5 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T5,T23,T24 |
LINE 165
SUB-EXPRESSION (cnt_ge && timeout_en_i)
---1-- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T5,T60 |
LINE 185
EXPRESSION (crashdump_phase_i == 2'b0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T7,T4,T5 |
LINE 202
EXPRESSION (crashdump_phase_i == 2'b1)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T7,T4 |
1 | Covered | T23,T11,T59 |
LINE 219
EXPRESSION (crashdump_phase_i == 2'b10)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T7,T4,T5 |
1 | Covered | T3,T4,T5 |
LINE 236
EXPRESSION (crashdump_phase_i == 2'b11)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T7,T4 |
1 | Covered | T4,T5,T23 |
LINE 277
EXPRESSION (accu_fail_i || cnt_error)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T13,T14,T15 |
LINE 289
EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T4,T5,T21 |
LINE 289
EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T7,T4,T5 |
LINE 289
EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T3,T4,T5 |
LINE 289
EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T3,T7,T4 |
FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
8 |
8 |
100.00 |
(Not included in score) |
Transitions |
14 |
14 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
FsmErrorSt |
278 |
Covered |
T16 |
IdleSt |
175 |
Covered |
T16 |
Phase0St |
146 |
Covered |
T16 |
Phase1St |
192 |
Covered |
T16 |
Phase2St |
209 |
Covered |
T16 |
Phase3St |
227 |
Covered |
T16 |
TerminalSt |
243 |
Covered |
T16 |
TimeoutSt |
153 |
Covered |
T16 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
IdleSt->FsmErrorSt |
278 |
Covered |
T16 |
|
IdleSt->Phase0St |
146 |
Covered |
T16 |
|
IdleSt->TimeoutSt |
153 |
Covered |
T16 |
|
Phase0St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase0St->IdleSt |
188 |
Covered |
T16 |
|
Phase0St->Phase1St |
192 |
Covered |
T16 |
|
Phase1St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase1St->IdleSt |
205 |
Covered |
T16 |
|
Phase1St->Phase2St |
209 |
Covered |
T16 |
|
Phase2St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase2St->IdleSt |
223 |
Covered |
T16 |
|
Phase2St->Phase3St |
227 |
Covered |
T16 |
|
Phase3St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase3St->IdleSt |
239 |
Covered |
T16 |
|
Phase3St->TerminalSt |
243 |
Covered |
T16 |
|
TerminalSt->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TerminalSt->IdleSt |
255 |
Covered |
T16 |
|
TimeoutSt->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TimeoutSt->IdleSt |
175 |
Covered |
T16 |
|
TimeoutSt->Phase0St |
166 |
Covered |
T16 |
|
Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
| Line No. | Total | Covered | Percent |
Branches |
|
26 |
26 |
100.00 |
CASE |
138 |
22 |
22 |
100.00 |
IF |
277 |
2 |
2 |
100.00 |
IF |
299 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 case (state_q)
-2-: 145 if (((accu_trig_i && en_i) && (!clr_i)))
-3-: 151 if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-: 165 if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-: 172 if (timeout_en_i)
-6-: 187 if (clr_i)
-7-: 191 if (cnt_ge)
-8-: 204 if (clr_i)
-9-: 208 if (cnt_ge)
-10-: 222 if (clr_i)
-11-: 226 if (cnt_ge)
-12-: 238 if (clr_i)
-13-: 242 if (cnt_ge)
-14-: 254 if (clr_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T4,T5 |
IdleSt |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T5 |
IdleSt |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
TimeoutSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T5,T23 |
TimeoutSt |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T5 |
TimeoutSt |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T5 |
Phase0St |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T37,T39,T68 |
Phase0St |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T7,T4 |
Phase0St |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T7,T4 |
Phase1St |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T6,T23,T62 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T3,T7,T4 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T3,T7,T4 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T41,T42,T43 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
Covered |
T3,T7,T4 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
Covered |
T3,T7,T4 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T18,T44,T108 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T3,T7,T4 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T3,T7,T4 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T3,T7,T4 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T3,T7,T4 |
FsmErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T14,T15 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T14,T15 |
LineNo. Expression
-1-: 277 if ((accu_fail_i || cnt_error))
Branches:
-1- | Status | Tests |
1 |
Covered |
T13,T14,T15 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 299 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer
Assertion Details
AccuFailToFsmError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
193 |
0 |
0 |
T13 |
21342 |
25 |
0 |
0 |
T14 |
0 |
30 |
0 |
0 |
T15 |
0 |
43 |
0 |
0 |
T46 |
0 |
27 |
0 |
0 |
T47 |
0 |
68 |
0 |
0 |
T48 |
537689 |
0 |
0 |
0 |
T49 |
20719 |
0 |
0 |
0 |
T50 |
128123 |
0 |
0 |
0 |
T51 |
252281 |
0 |
0 |
0 |
T52 |
253728 |
0 |
0 |
0 |
T53 |
923666 |
0 |
0 |
0 |
T54 |
35421 |
0 |
0 |
0 |
T55 |
943925 |
0 |
0 |
0 |
T56 |
20878 |
0 |
0 |
0 |
CheckAccumTrig0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
945 |
0 |
0 |
T4 |
190757 |
5 |
0 |
0 |
T5 |
544461 |
6 |
0 |
0 |
T6 |
126695 |
2 |
0 |
0 |
T7 |
67227 |
1 |
0 |
0 |
T8 |
163192 |
1 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
1 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
6 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
CheckAccumTrig1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
46 |
0 |
0 |
T5 |
544461 |
1 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T8 |
163192 |
0 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
2 |
0 |
0 |
T24 |
20641 |
1 |
0 |
0 |
T57 |
67859 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T68 |
0 |
1 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T72 |
0 |
1 |
0 |
0 |
T73 |
0 |
1 |
0 |
0 |
T74 |
0 |
1 |
0 |
0 |
CheckClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
483 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
2 |
0 |
0 |
T5 |
544461 |
1 |
0 |
0 |
T6 |
126695 |
1 |
0 |
0 |
T7 |
67227 |
1 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
4 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T81 |
0 |
2 |
0 |
0 |
CheckEn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790563850 |
301032068 |
0 |
0 |
T1 |
19350 |
582 |
0 |
0 |
T2 |
6174 |
6082 |
0 |
0 |
T3 |
28283 |
9336 |
0 |
0 |
T4 |
190757 |
614651 |
0 |
0 |
T5 |
544461 |
80696 |
0 |
0 |
T6 |
126695 |
1608 |
0 |
0 |
T7 |
67227 |
61176 |
0 |
0 |
T19 |
46858 |
46763 |
0 |
0 |
T20 |
18817 |
17726 |
0 |
0 |
T21 |
283872 |
17223 |
0 |
0 |
CheckPhase0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
1030 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
5 |
0 |
0 |
T5 |
544461 |
8 |
0 |
0 |
T6 |
126695 |
2 |
0 |
0 |
T7 |
67227 |
1 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
1 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
8 |
0 |
0 |
T24 |
0 |
2 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
CheckPhase1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
1011 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
5 |
0 |
0 |
T5 |
544461 |
8 |
0 |
0 |
T6 |
126695 |
1 |
0 |
0 |
T7 |
67227 |
1 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
1 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
7 |
0 |
0 |
T24 |
0 |
2 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
CheckPhase2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
994 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
5 |
0 |
0 |
T5 |
544461 |
8 |
0 |
0 |
T6 |
126695 |
1 |
0 |
0 |
T7 |
67227 |
1 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
1 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
7 |
0 |
0 |
T24 |
0 |
2 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
CheckPhase3_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
962 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
5 |
0 |
0 |
T5 |
544461 |
8 |
0 |
0 |
T6 |
126695 |
1 |
0 |
0 |
T7 |
67227 |
1 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
1 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
7 |
0 |
0 |
T24 |
0 |
2 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
CheckTimeout0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
899 |
0 |
0 |
T1 |
19350 |
4 |
0 |
0 |
T2 |
6174 |
0 |
0 |
0 |
T3 |
28283 |
2 |
0 |
0 |
T4 |
190757 |
0 |
0 |
0 |
T5 |
544461 |
8 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
10 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T60 |
0 |
22 |
0 |
0 |
T95 |
0 |
3 |
0 |
0 |
T96 |
0 |
1 |
0 |
0 |
CheckTimeoutSt1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
97668 |
0 |
0 |
T1 |
19350 |
429 |
0 |
0 |
T2 |
6174 |
0 |
0 |
0 |
T3 |
28283 |
358 |
0 |
0 |
T4 |
190757 |
0 |
0 |
0 |
T5 |
544461 |
790 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
1774 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T24 |
0 |
2 |
0 |
0 |
T41 |
0 |
25 |
0 |
0 |
T60 |
0 |
1789 |
0 |
0 |
T95 |
0 |
376 |
0 |
0 |
T96 |
0 |
35 |
0 |
0 |
CheckTimeoutSt2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
786 |
0 |
0 |
T1 |
19350 |
4 |
0 |
0 |
T2 |
6174 |
0 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
0 |
0 |
0 |
T5 |
544461 |
6 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
10 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T60 |
0 |
21 |
0 |
0 |
T95 |
0 |
3 |
0 |
0 |
T96 |
0 |
1 |
0 |
0 |
T97 |
0 |
1 |
0 |
0 |
T98 |
0 |
1 |
0 |
0 |
CheckTimeoutStTrig_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
66 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
0 |
0 |
0 |
T5 |
544461 |
1 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T62 |
0 |
5 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T98 |
0 |
1 |
0 |
0 |
T100 |
0 |
1 |
0 |
0 |
T104 |
0 |
1 |
0 |
0 |
ErrorStAllEscAsserted_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
1122 |
0 |
0 |
T13 |
21342 |
188 |
0 |
0 |
T14 |
0 |
196 |
0 |
0 |
T15 |
0 |
181 |
0 |
0 |
T46 |
0 |
170 |
0 |
0 |
T47 |
0 |
387 |
0 |
0 |
T48 |
537689 |
0 |
0 |
0 |
T49 |
20719 |
0 |
0 |
0 |
T50 |
128123 |
0 |
0 |
0 |
T51 |
252281 |
0 |
0 |
0 |
T52 |
253728 |
0 |
0 |
0 |
T53 |
923666 |
0 |
0 |
0 |
T54 |
35421 |
0 |
0 |
0 |
T55 |
943925 |
0 |
0 |
0 |
T56 |
20878 |
0 |
0 |
0 |
ErrorStIsTerminal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
942 |
0 |
0 |
T13 |
21342 |
158 |
0 |
0 |
T14 |
0 |
166 |
0 |
0 |
T15 |
0 |
151 |
0 |
0 |
T46 |
0 |
140 |
0 |
0 |
T47 |
0 |
327 |
0 |
0 |
T48 |
537689 |
0 |
0 |
0 |
T49 |
20719 |
0 |
0 |
0 |
T50 |
128123 |
0 |
0 |
0 |
T51 |
252281 |
0 |
0 |
0 |
T52 |
253728 |
0 |
0 |
0 |
T53 |
923666 |
0 |
0 |
0 |
T54 |
35421 |
0 |
0 |
0 |
T55 |
943925 |
0 |
0 |
0 |
T56 |
20878 |
0 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
790696413 |
0 |
0 |
T1 |
19350 |
19268 |
0 |
0 |
T2 |
6174 |
6083 |
0 |
0 |
T3 |
28283 |
28195 |
0 |
0 |
T4 |
190757 |
190748 |
0 |
0 |
T5 |
544461 |
544439 |
0 |
0 |
T6 |
126695 |
126687 |
0 |
0 |
T7 |
67227 |
67169 |
0 |
0 |
T19 |
46858 |
46764 |
0 |
0 |
T20 |
18817 |
18730 |
0 |
0 |
T21 |
283872 |
283663 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
| Line No. | Total | Covered | Percent |
TOTAL | | 101 | 101 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
ALWAYS | 128 | 89 | 89 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
ALWAYS | 299 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
79 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
138 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
151 |
1 |
1 |
152 |
1 |
1 |
153 |
1 |
1 |
|
|
|
MISSING_ELSE |
163 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
172 |
1 |
1 |
173 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
181 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
201 |
1 |
1 |
202 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
208 |
1 |
1 |
209 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
226 |
1 |
1 |
227 |
1 |
1 |
228 |
1 |
1 |
|
|
|
MISSING_ELSE |
232 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
238 |
1 |
1 |
239 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
243 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
|
|
|
MISSING_ELSE |
252 |
1 |
1 |
253 |
1 |
1 |
254 |
1 |
1 |
255 |
1 |
1 |
|
|
|
MISSING_ELSE |
262 |
1 |
1 |
263 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
279 |
1 |
1 |
|
|
|
MISSING_ELSE |
286 |
4 |
4 |
289 |
4 |
4 |
299 |
3 |
3 |
Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
| Total | Covered | Percent |
Conditions | 45 | 42 | 93.33 |
Logical | 45 | 42 | 93.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 61
EXPRESSION (cnt_clr && ((!cnt_en)))
---1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 61
EXPRESSION (cnt_clr && cnt_en)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 145
EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 151
EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
------1----- -----2----- --3-
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T5,T6,T20 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T5 |
LINE 165
EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
-----------------1----------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T5 |
0 | 1 | Covered | T5,T60,T98 |
1 | 0 | Covered | T64,T66,T67 |
LINE 165
SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T3,T5 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T64,T66,T67 |
LINE 165
SUB-EXPRESSION (cnt_ge && timeout_en_i)
---1-- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T60,T98 |
LINE 185
EXPRESSION (crashdump_phase_i == 2'b0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T4,T5,T58 |
1 | Covered | T4,T5,T6 |
LINE 202
EXPRESSION (crashdump_phase_i == 2'b1)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T58,T25 |
LINE 219
EXPRESSION (crashdump_phase_i == 2'b10)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T59 |
LINE 236
EXPRESSION (crashdump_phase_i == 2'b11)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T64,T109 |
LINE 277
EXPRESSION (accu_fail_i || cnt_error)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T13,T14,T15 |
LINE 289
EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T5,T57,T64 |
LINE 289
EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T4,T5,T57 |
LINE 289
EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T4,T5,T6 |
LINE 289
EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T4,T5,T6 |
FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
8 |
8 |
100.00 |
(Not included in score) |
Transitions |
14 |
14 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
FsmErrorSt |
278 |
Covered |
T16 |
IdleSt |
175 |
Covered |
T16 |
Phase0St |
146 |
Covered |
T16 |
Phase1St |
192 |
Covered |
T16 |
Phase2St |
209 |
Covered |
T16 |
Phase3St |
227 |
Covered |
T16 |
TerminalSt |
243 |
Covered |
T16 |
TimeoutSt |
153 |
Covered |
T16 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
IdleSt->FsmErrorSt |
278 |
Covered |
T16 |
|
IdleSt->Phase0St |
146 |
Covered |
T16 |
|
IdleSt->TimeoutSt |
153 |
Covered |
T16 |
|
Phase0St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase0St->IdleSt |
188 |
Covered |
T16 |
|
Phase0St->Phase1St |
192 |
Covered |
T16 |
|
Phase1St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase1St->IdleSt |
205 |
Covered |
T16 |
|
Phase1St->Phase2St |
209 |
Covered |
T16 |
|
Phase2St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase2St->IdleSt |
223 |
Covered |
T16 |
|
Phase2St->Phase3St |
227 |
Covered |
T16 |
|
Phase3St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase3St->IdleSt |
239 |
Covered |
T16 |
|
Phase3St->TerminalSt |
243 |
Covered |
T16 |
|
TerminalSt->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TerminalSt->IdleSt |
255 |
Covered |
T16 |
|
TimeoutSt->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TimeoutSt->IdleSt |
175 |
Covered |
T16 |
|
TimeoutSt->Phase0St |
166 |
Covered |
T16 |
|
Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
| Line No. | Total | Covered | Percent |
Branches |
|
26 |
26 |
100.00 |
CASE |
138 |
22 |
22 |
100.00 |
IF |
277 |
2 |
2 |
100.00 |
IF |
299 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 case (state_q)
-2-: 145 if (((accu_trig_i && en_i) && (!clr_i)))
-3-: 151 if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-: 165 if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-: 172 if (timeout_en_i)
-6-: 187 if (clr_i)
-7-: 191 if (cnt_ge)
-8-: 204 if (clr_i)
-9-: 208 if (cnt_ge)
-10-: 222 if (clr_i)
-11-: 226 if (cnt_ge)
-12-: 238 if (clr_i)
-13-: 242 if (cnt_ge)
-14-: 254 if (clr_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
IdleSt |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T5 |
IdleSt |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
TimeoutSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T64,T60 |
TimeoutSt |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T5 |
TimeoutSt |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T5 |
Phase0St |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T110,T111,T112 |
Phase0St |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
Phase0St |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
Phase1St |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T40,T66,T38 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T113,T114,T115 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
Covered |
T4,T5,T6 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
Covered |
T4,T5,T6 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T116,T70,T111 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T4,T5,T6 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T4,T5,T6 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T5,T25,T88 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T4,T5,T6 |
FsmErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T14,T15 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T14,T15 |
LineNo. Expression
-1-: 277 if ((accu_fail_i || cnt_error))
Branches:
-1- | Status | Tests |
1 |
Covered |
T13,T14,T15 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 299 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer
Assertion Details
AccuFailToFsmError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
210 |
0 |
0 |
T13 |
21342 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
36 |
0 |
0 |
T46 |
0 |
45 |
0 |
0 |
T47 |
0 |
69 |
0 |
0 |
T48 |
537689 |
0 |
0 |
0 |
T49 |
20719 |
0 |
0 |
0 |
T50 |
128123 |
0 |
0 |
0 |
T51 |
252281 |
0 |
0 |
0 |
T52 |
253728 |
0 |
0 |
0 |
T53 |
923666 |
0 |
0 |
0 |
T54 |
35421 |
0 |
0 |
0 |
T55 |
943925 |
0 |
0 |
0 |
T56 |
20878 |
0 |
0 |
0 |
CheckAccumTrig0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
547 |
0 |
0 |
T4 |
190757 |
2 |
0 |
0 |
T5 |
544461 |
6 |
0 |
0 |
T6 |
126695 |
1 |
0 |
0 |
T8 |
163192 |
0 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
0 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
CheckAccumTrig1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
24 |
0 |
0 |
T38 |
396969 |
0 |
0 |
0 |
T64 |
30307 |
1 |
0 |
0 |
T66 |
168201 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T70 |
0 |
1 |
0 |
0 |
T75 |
0 |
1 |
0 |
0 |
T76 |
0 |
1 |
0 |
0 |
T77 |
0 |
2 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T79 |
0 |
1 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T81 |
21614 |
0 |
0 |
0 |
T82 |
242567 |
0 |
0 |
0 |
T83 |
374326 |
0 |
0 |
0 |
T84 |
94059 |
0 |
0 |
0 |
T85 |
13975 |
0 |
0 |
0 |
T86 |
307942 |
0 |
0 |
0 |
T87 |
123102 |
0 |
0 |
0 |
CheckClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
240 |
0 |
0 |
T5 |
544461 |
3 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T8 |
163192 |
0 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
0 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T57 |
67859 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T88 |
0 |
1 |
0 |
0 |
T89 |
0 |
1 |
0 |
0 |
T90 |
0 |
2 |
0 |
0 |
T91 |
0 |
1 |
0 |
0 |
T92 |
0 |
1 |
0 |
0 |
T93 |
0 |
1 |
0 |
0 |
CheckEn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790563850 |
363323468 |
0 |
0 |
T1 |
19350 |
4504 |
0 |
0 |
T2 |
6174 |
3165 |
0 |
0 |
T3 |
28283 |
9229 |
0 |
0 |
T4 |
190757 |
827538 |
0 |
0 |
T5 |
544461 |
379606 |
0 |
0 |
T6 |
126695 |
3066 |
0 |
0 |
T7 |
67227 |
2257 |
0 |
0 |
T19 |
46858 |
46763 |
0 |
0 |
T20 |
18817 |
14717 |
0 |
0 |
T21 |
283872 |
253252 |
0 |
0 |
CheckPhase0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
627 |
0 |
0 |
T4 |
190757 |
2 |
0 |
0 |
T5 |
544461 |
7 |
0 |
0 |
T6 |
126695 |
1 |
0 |
0 |
T8 |
163192 |
0 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
0 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
2 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
CheckPhase1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
611 |
0 |
0 |
T4 |
190757 |
2 |
0 |
0 |
T5 |
544461 |
7 |
0 |
0 |
T6 |
126695 |
1 |
0 |
0 |
T8 |
163192 |
0 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
0 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
2 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
CheckPhase2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
602 |
0 |
0 |
T4 |
190757 |
2 |
0 |
0 |
T5 |
544461 |
7 |
0 |
0 |
T6 |
126695 |
1 |
0 |
0 |
T8 |
163192 |
0 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
0 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
2 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
CheckPhase3_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
595 |
0 |
0 |
T4 |
190757 |
2 |
0 |
0 |
T5 |
544461 |
7 |
0 |
0 |
T6 |
126695 |
1 |
0 |
0 |
T8 |
163192 |
0 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
0 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
2 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
CheckTimeout0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
1049 |
0 |
0 |
T1 |
19350 |
6 |
0 |
0 |
T2 |
6174 |
0 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
0 |
0 |
0 |
T5 |
544461 |
12 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T18 |
0 |
5 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
2 |
0 |
0 |
T22 |
0 |
1 |
0 |
0 |
T60 |
0 |
22 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
T94 |
0 |
5 |
0 |
0 |
T95 |
0 |
9 |
0 |
0 |
CheckTimeoutSt1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
104271 |
0 |
0 |
T1 |
19350 |
574 |
0 |
0 |
T2 |
6174 |
0 |
0 |
0 |
T3 |
28283 |
205 |
0 |
0 |
T4 |
190757 |
0 |
0 |
0 |
T5 |
544461 |
964 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T18 |
0 |
667 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
338 |
0 |
0 |
T22 |
0 |
123 |
0 |
0 |
T60 |
0 |
1771 |
0 |
0 |
T64 |
0 |
2 |
0 |
0 |
T94 |
0 |
801 |
0 |
0 |
T95 |
0 |
1136 |
0 |
0 |
CheckTimeoutSt2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
955 |
0 |
0 |
T1 |
19350 |
6 |
0 |
0 |
T2 |
6174 |
0 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
0 |
0 |
0 |
T5 |
544461 |
11 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T18 |
0 |
5 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
2 |
0 |
0 |
T22 |
0 |
1 |
0 |
0 |
T25 |
0 |
3 |
0 |
0 |
T60 |
0 |
21 |
0 |
0 |
T94 |
0 |
5 |
0 |
0 |
T95 |
0 |
9 |
0 |
0 |
CheckTimeoutStTrig_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
69 |
0 |
0 |
T5 |
544461 |
1 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T8 |
163192 |
0 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
0 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T57 |
67859 |
0 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T98 |
0 |
1 |
0 |
0 |
T100 |
0 |
1 |
0 |
0 |
T101 |
0 |
2 |
0 |
0 |
T104 |
0 |
1 |
0 |
0 |
T105 |
0 |
4 |
0 |
0 |
T106 |
0 |
3 |
0 |
0 |
ErrorStAllEscAsserted_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
1049 |
0 |
0 |
T13 |
21342 |
171 |
0 |
0 |
T14 |
0 |
169 |
0 |
0 |
T15 |
0 |
183 |
0 |
0 |
T46 |
0 |
193 |
0 |
0 |
T47 |
0 |
333 |
0 |
0 |
T48 |
537689 |
0 |
0 |
0 |
T49 |
20719 |
0 |
0 |
0 |
T50 |
128123 |
0 |
0 |
0 |
T51 |
252281 |
0 |
0 |
0 |
T52 |
253728 |
0 |
0 |
0 |
T53 |
923666 |
0 |
0 |
0 |
T54 |
35421 |
0 |
0 |
0 |
T55 |
943925 |
0 |
0 |
0 |
T56 |
20878 |
0 |
0 |
0 |
ErrorStIsTerminal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
869 |
0 |
0 |
T13 |
21342 |
141 |
0 |
0 |
T14 |
0 |
139 |
0 |
0 |
T15 |
0 |
153 |
0 |
0 |
T46 |
0 |
163 |
0 |
0 |
T47 |
0 |
273 |
0 |
0 |
T48 |
537689 |
0 |
0 |
0 |
T49 |
20719 |
0 |
0 |
0 |
T50 |
128123 |
0 |
0 |
0 |
T51 |
252281 |
0 |
0 |
0 |
T52 |
253728 |
0 |
0 |
0 |
T53 |
923666 |
0 |
0 |
0 |
T54 |
35421 |
0 |
0 |
0 |
T55 |
943925 |
0 |
0 |
0 |
T56 |
20878 |
0 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
790696413 |
0 |
0 |
T1 |
19350 |
19268 |
0 |
0 |
T2 |
6174 |
6083 |
0 |
0 |
T3 |
28283 |
28195 |
0 |
0 |
T4 |
190757 |
190748 |
0 |
0 |
T5 |
544461 |
544439 |
0 |
0 |
T6 |
126695 |
126687 |
0 |
0 |
T7 |
67227 |
67169 |
0 |
0 |
T19 |
46858 |
46764 |
0 |
0 |
T20 |
18817 |
18730 |
0 |
0 |
T21 |
283872 |
283663 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
| Line No. | Total | Covered | Percent |
TOTAL | | 101 | 101 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
ALWAYS | 128 | 89 | 89 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
ALWAYS | 299 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
79 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
138 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
151 |
1 |
1 |
152 |
1 |
1 |
153 |
1 |
1 |
|
|
|
MISSING_ELSE |
163 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
172 |
1 |
1 |
173 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
181 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
201 |
1 |
1 |
202 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
208 |
1 |
1 |
209 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
226 |
1 |
1 |
227 |
1 |
1 |
228 |
1 |
1 |
|
|
|
MISSING_ELSE |
232 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
238 |
1 |
1 |
239 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
243 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
|
|
|
MISSING_ELSE |
252 |
1 |
1 |
253 |
1 |
1 |
254 |
1 |
1 |
255 |
1 |
1 |
|
|
|
MISSING_ELSE |
262 |
1 |
1 |
263 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
279 |
1 |
1 |
|
|
|
MISSING_ELSE |
286 |
4 |
4 |
289 |
4 |
4 |
299 |
3 |
3 |
Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
| Total | Covered | Percent |
Conditions | 45 | 43 | 95.56 |
Logical | 45 | 43 | 95.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 61
EXPRESSION (cnt_clr && ((!cnt_en)))
---1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 61
EXPRESSION (cnt_clr && cnt_en)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 145
EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T19 |
LINE 151
EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
------1----- -----2----- --3-
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T5,T19 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 165
EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
-----------------1----------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T21,T58,T100 |
1 | 0 | Covered | T4,T60,T117 |
LINE 165
SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T60,T117 |
LINE 165
SUB-EXPRESSION (cnt_ge && timeout_en_i)
---1-- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T36 |
1 | 1 | Covered | T21,T58,T100 |
LINE 185
EXPRESSION (crashdump_phase_i == 2'b0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T4,T5,T19 |
1 | Covered | T5,T58,T12 |
LINE 202
EXPRESSION (crashdump_phase_i == 2'b1)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T4,T5,T21 |
1 | Covered | T4,T5,T19 |
LINE 219
EXPRESSION (crashdump_phase_i == 2'b10)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T4,T5,T19 |
1 | Covered | T4,T23,T57 |
LINE 236
EXPRESSION (crashdump_phase_i == 2'b11)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T4,T5,T19 |
1 | Covered | T4,T5,T21 |
LINE 277
EXPRESSION (accu_fail_i || cnt_error)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T13,T14,T15 |
LINE 289
EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T4,T5,T23 |
LINE 289
EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T4,T5,T21 |
LINE 289
EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T4,T5,T19 |
LINE 289
EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T4,T5,T19 |
FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
8 |
8 |
100.00 |
(Not included in score) |
Transitions |
14 |
14 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
FsmErrorSt |
278 |
Covered |
T16 |
IdleSt |
175 |
Covered |
T16 |
Phase0St |
146 |
Covered |
T16 |
Phase1St |
192 |
Covered |
T16 |
Phase2St |
209 |
Covered |
T16 |
Phase3St |
227 |
Covered |
T16 |
TerminalSt |
243 |
Covered |
T16 |
TimeoutSt |
153 |
Covered |
T16 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
IdleSt->FsmErrorSt |
278 |
Covered |
T16 |
|
IdleSt->Phase0St |
146 |
Covered |
T16 |
|
IdleSt->TimeoutSt |
153 |
Covered |
T16 |
|
Phase0St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase0St->IdleSt |
188 |
Covered |
T16 |
|
Phase0St->Phase1St |
192 |
Covered |
T16 |
|
Phase1St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase1St->IdleSt |
205 |
Covered |
T16 |
|
Phase1St->Phase2St |
209 |
Covered |
T16 |
|
Phase2St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase2St->IdleSt |
223 |
Covered |
T16 |
|
Phase2St->Phase3St |
227 |
Covered |
T16 |
|
Phase3St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase3St->IdleSt |
239 |
Covered |
T16 |
|
Phase3St->TerminalSt |
243 |
Covered |
T16 |
|
TerminalSt->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TerminalSt->IdleSt |
255 |
Covered |
T16 |
|
TimeoutSt->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TimeoutSt->IdleSt |
175 |
Covered |
T16 |
|
TimeoutSt->Phase0St |
166 |
Covered |
T16 |
|
Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
| Line No. | Total | Covered | Percent |
Branches |
|
26 |
26 |
100.00 |
CASE |
138 |
22 |
22 |
100.00 |
IF |
277 |
2 |
2 |
100.00 |
IF |
299 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 case (state_q)
-2-: 145 if (((accu_trig_i && en_i) && (!clr_i)))
-3-: 151 if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-: 165 if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-: 172 if (timeout_en_i)
-6-: 187 if (clr_i)
-7-: 191 if (cnt_ge)
-8-: 204 if (clr_i)
-9-: 208 if (cnt_ge)
-10-: 222 if (clr_i)
-11-: 226 if (cnt_ge)
-12-: 238 if (clr_i)
-13-: 242 if (cnt_ge)
-14-: 254 if (clr_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T19 |
IdleSt |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
IdleSt |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
TimeoutSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T21,T58 |
TimeoutSt |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T4 |
TimeoutSt |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T5 |
Phase0St |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T38,T75,T118 |
Phase0St |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T19 |
Phase0St |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T19 |
Phase1St |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T45,T119,T120 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T4,T5,T19 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T4,T5,T19 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T108,T121,T122 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
Covered |
T4,T5,T19 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
Covered |
T4,T5,T19 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T45,T116,T123 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T4,T5,T19 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T4,T5,T19 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T4,T19,T23 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T4,T5,T19 |
FsmErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T14,T15 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T14,T15 |
LineNo. Expression
-1-: 277 if ((accu_fail_i || cnt_error))
Branches:
-1- | Status | Tests |
1 |
Covered |
T13,T14,T15 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 299 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer
Assertion Details
AccuFailToFsmError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
250 |
0 |
0 |
T13 |
21342 |
27 |
0 |
0 |
T14 |
0 |
43 |
0 |
0 |
T15 |
0 |
45 |
0 |
0 |
T46 |
0 |
54 |
0 |
0 |
T47 |
0 |
81 |
0 |
0 |
T48 |
537689 |
0 |
0 |
0 |
T49 |
20719 |
0 |
0 |
0 |
T50 |
128123 |
0 |
0 |
0 |
T51 |
252281 |
0 |
0 |
0 |
T52 |
253728 |
0 |
0 |
0 |
T53 |
923666 |
0 |
0 |
0 |
T54 |
35421 |
0 |
0 |
0 |
T55 |
943925 |
0 |
0 |
0 |
T56 |
20878 |
0 |
0 |
0 |
CheckAccumTrig0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
529 |
0 |
0 |
T4 |
190757 |
3 |
0 |
0 |
T5 |
544461 |
3 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T8 |
163192 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T19 |
46858 |
1 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
5 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T62 |
0 |
1 |
0 |
0 |
CheckAccumTrig1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
21 |
0 |
0 |
T4 |
190757 |
1 |
0 |
0 |
T5 |
544461 |
0 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T8 |
163192 |
0 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
0 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T117 |
0 |
1 |
0 |
0 |
T124 |
0 |
1 |
0 |
0 |
T125 |
0 |
1 |
0 |
0 |
T126 |
0 |
1 |
0 |
0 |
T127 |
0 |
1 |
0 |
0 |
T128 |
0 |
1 |
0 |
0 |
T129 |
0 |
1 |
0 |
0 |
T130 |
0 |
1 |
0 |
0 |
CheckClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
233 |
0 |
0 |
T4 |
190757 |
1 |
0 |
0 |
T5 |
544461 |
0 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T8 |
163192 |
1 |
0 |
0 |
T19 |
46858 |
1 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
2 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T89 |
0 |
1 |
0 |
0 |
T91 |
0 |
1 |
0 |
0 |
T92 |
0 |
1 |
0 |
0 |
T98 |
0 |
1 |
0 |
0 |
T109 |
0 |
3 |
0 |
0 |
CheckEn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790563850 |
406075264 |
0 |
0 |
T1 |
19350 |
4199 |
0 |
0 |
T2 |
6174 |
3176 |
0 |
0 |
T3 |
28283 |
22033 |
0 |
0 |
T4 |
190757 |
449725 |
0 |
0 |
T5 |
544461 |
109439 |
0 |
0 |
T6 |
126695 |
126541 |
0 |
0 |
T7 |
67227 |
67168 |
0 |
0 |
T19 |
46858 |
39872 |
0 |
0 |
T20 |
18817 |
13115 |
0 |
0 |
T21 |
283872 |
182583 |
0 |
0 |
CheckPhase0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
598 |
0 |
0 |
T4 |
190757 |
4 |
0 |
0 |
T5 |
544461 |
3 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T8 |
163192 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T19 |
46858 |
1 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
1 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
5 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
CheckPhase1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
589 |
0 |
0 |
T4 |
190757 |
4 |
0 |
0 |
T5 |
544461 |
3 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T8 |
163192 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T19 |
46858 |
1 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
1 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
5 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
CheckPhase2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
579 |
0 |
0 |
T4 |
190757 |
4 |
0 |
0 |
T5 |
544461 |
3 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T8 |
163192 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T19 |
46858 |
1 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
1 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
5 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
CheckPhase3_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
562 |
0 |
0 |
T4 |
190757 |
4 |
0 |
0 |
T5 |
544461 |
3 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T8 |
163192 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T19 |
46858 |
1 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
1 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
5 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
CheckTimeout0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
901 |
0 |
0 |
T1 |
19350 |
4 |
0 |
0 |
T2 |
6174 |
0 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
1 |
0 |
0 |
T5 |
544461 |
151 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T18 |
0 |
3 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T94 |
0 |
13 |
0 |
0 |
T95 |
0 |
1 |
0 |
0 |
CheckTimeoutSt1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
106481 |
0 |
0 |
T1 |
19350 |
476 |
0 |
0 |
T2 |
6174 |
0 |
0 |
0 |
T3 |
28283 |
177 |
0 |
0 |
T4 |
190757 |
21 |
0 |
0 |
T5 |
544461 |
15672 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T18 |
0 |
431 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
91 |
0 |
0 |
T58 |
0 |
17 |
0 |
0 |
T60 |
0 |
6 |
0 |
0 |
T94 |
0 |
2144 |
0 |
0 |
T95 |
0 |
137 |
0 |
0 |
CheckTimeoutSt2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
823 |
0 |
0 |
T1 |
19350 |
4 |
0 |
0 |
T2 |
6174 |
0 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
0 |
0 |
0 |
T5 |
544461 |
151 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T18 |
0 |
3 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T93 |
0 |
1 |
0 |
0 |
T94 |
0 |
13 |
0 |
0 |
T95 |
0 |
1 |
0 |
0 |
T97 |
0 |
1 |
0 |
0 |
T98 |
0 |
3 |
0 |
0 |
T99 |
0 |
1 |
0 |
0 |
CheckTimeoutStTrig_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
56 |
0 |
0 |
T8 |
163192 |
0 |
0 |
0 |
T9 |
474054 |
0 |
0 |
0 |
T21 |
283872 |
1 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
0 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T43 |
0 |
1 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T57 |
67859 |
0 |
0 |
0 |
T58 |
23401 |
1 |
0 |
0 |
T64 |
30307 |
0 |
0 |
0 |
T75 |
0 |
2 |
0 |
0 |
T94 |
111065 |
0 |
0 |
0 |
T100 |
0 |
1 |
0 |
0 |
T102 |
0 |
1 |
0 |
0 |
T103 |
0 |
1 |
0 |
0 |
T107 |
0 |
1 |
0 |
0 |
T131 |
0 |
1 |
0 |
0 |
ErrorStAllEscAsserted_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
1104 |
0 |
0 |
T13 |
21342 |
155 |
0 |
0 |
T14 |
0 |
194 |
0 |
0 |
T15 |
0 |
170 |
0 |
0 |
T46 |
0 |
190 |
0 |
0 |
T47 |
0 |
395 |
0 |
0 |
T48 |
537689 |
0 |
0 |
0 |
T49 |
20719 |
0 |
0 |
0 |
T50 |
128123 |
0 |
0 |
0 |
T51 |
252281 |
0 |
0 |
0 |
T52 |
253728 |
0 |
0 |
0 |
T53 |
923666 |
0 |
0 |
0 |
T54 |
35421 |
0 |
0 |
0 |
T55 |
943925 |
0 |
0 |
0 |
T56 |
20878 |
0 |
0 |
0 |
ErrorStIsTerminal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
924 |
0 |
0 |
T13 |
21342 |
125 |
0 |
0 |
T14 |
0 |
164 |
0 |
0 |
T15 |
0 |
140 |
0 |
0 |
T46 |
0 |
160 |
0 |
0 |
T47 |
0 |
335 |
0 |
0 |
T48 |
537689 |
0 |
0 |
0 |
T49 |
20719 |
0 |
0 |
0 |
T50 |
128123 |
0 |
0 |
0 |
T51 |
252281 |
0 |
0 |
0 |
T52 |
253728 |
0 |
0 |
0 |
T53 |
923666 |
0 |
0 |
0 |
T54 |
35421 |
0 |
0 |
0 |
T55 |
943925 |
0 |
0 |
0 |
T56 |
20878 |
0 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
790696413 |
0 |
0 |
T1 |
19350 |
19268 |
0 |
0 |
T2 |
6174 |
6083 |
0 |
0 |
T3 |
28283 |
28195 |
0 |
0 |
T4 |
190757 |
190748 |
0 |
0 |
T5 |
544461 |
544439 |
0 |
0 |
T6 |
126695 |
126687 |
0 |
0 |
T7 |
67227 |
67169 |
0 |
0 |
T19 |
46858 |
46764 |
0 |
0 |
T20 |
18817 |
18730 |
0 |
0 |
T21 |
283872 |
283663 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
| Line No. | Total | Covered | Percent |
TOTAL | | 101 | 101 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
ALWAYS | 128 | 89 | 89 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
ALWAYS | 299 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
79 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
138 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
151 |
1 |
1 |
152 |
1 |
1 |
153 |
1 |
1 |
|
|
|
MISSING_ELSE |
163 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
172 |
1 |
1 |
173 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
181 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
201 |
1 |
1 |
202 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
208 |
1 |
1 |
209 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
226 |
1 |
1 |
227 |
1 |
1 |
228 |
1 |
1 |
|
|
|
MISSING_ELSE |
232 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
238 |
1 |
1 |
239 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
243 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
|
|
|
MISSING_ELSE |
252 |
1 |
1 |
253 |
1 |
1 |
254 |
1 |
1 |
255 |
1 |
1 |
|
|
|
MISSING_ELSE |
262 |
1 |
1 |
263 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
279 |
1 |
1 |
|
|
|
MISSING_ELSE |
286 |
4 |
4 |
289 |
4 |
4 |
299 |
3 |
3 |
Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
| Total | Covered | Percent |
Conditions | 45 | 43 | 95.56 |
Logical | 45 | 43 | 95.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 61
EXPRESSION (cnt_clr && ((!cnt_en)))
---1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 61
EXPRESSION (cnt_clr && cnt_en)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 145
EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Covered | T35 |
1 | 1 | 1 | Covered | T4,T6,T23 |
LINE 151
EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
------1----- -----2----- --3-
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T4 |
1 | 0 | 1 | Covered | T4,T5,T23 |
1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | Covered | T1,T3,T19 |
LINE 165
EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
-----------------1----------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T19 |
0 | 1 | Covered | T3,T19,T57 |
1 | 0 | Covered | T23,T109,T66 |
LINE 165
SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
-----1----- --2- -----3----
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T3,T19 |
1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T23,T109,T66 |
LINE 165
SUB-EXPRESSION (cnt_ge && timeout_en_i)
---1-- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T19 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T19,T57 |
LINE 185
EXPRESSION (crashdump_phase_i == 2'b0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T19 |
1 | Covered | T58,T132,T109 |
LINE 202
EXPRESSION (crashdump_phase_i == 2'b1)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T4,T19,T6 |
1 | Covered | T3,T4,T23 |
LINE 219
EXPRESSION (crashdump_phase_i == 2'b10)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T19 |
1 | Covered | T4,T6,T57 |
LINE 236
EXPRESSION (crashdump_phase_i == 2'b11)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T6 |
1 | Covered | T19,T23,T11 |
LINE 277
EXPRESSION (accu_fail_i || cnt_error)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T13,T14,T15 |
LINE 289
EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T4,T19,T6 |
LINE 289
EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T3,T19,T6 |
LINE 289
EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T23,T9,T59 |
LINE 289
EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
---------------1--------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T4,T19,T23 |
FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
8 |
8 |
100.00 |
(Not included in score) |
Transitions |
14 |
14 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
FsmErrorSt |
278 |
Covered |
T16 |
IdleSt |
175 |
Covered |
T16 |
Phase0St |
146 |
Covered |
T16 |
Phase1St |
192 |
Covered |
T16 |
Phase2St |
209 |
Covered |
T16 |
Phase3St |
227 |
Covered |
T16 |
TerminalSt |
243 |
Covered |
T16 |
TimeoutSt |
153 |
Covered |
T16 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
IdleSt->FsmErrorSt |
278 |
Covered |
T16 |
|
IdleSt->Phase0St |
146 |
Covered |
T16 |
|
IdleSt->TimeoutSt |
153 |
Covered |
T16 |
|
Phase0St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase0St->IdleSt |
188 |
Covered |
T16 |
|
Phase0St->Phase1St |
192 |
Covered |
T16 |
|
Phase1St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase1St->IdleSt |
205 |
Covered |
T16 |
|
Phase1St->Phase2St |
209 |
Covered |
T16 |
|
Phase2St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase2St->IdleSt |
223 |
Covered |
T16 |
|
Phase2St->Phase3St |
227 |
Covered |
T16 |
|
Phase3St->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
Phase3St->IdleSt |
239 |
Covered |
T16 |
|
Phase3St->TerminalSt |
243 |
Covered |
T16 |
|
TerminalSt->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TerminalSt->IdleSt |
255 |
Covered |
T16 |
|
TimeoutSt->FsmErrorSt |
278 |
Excluded |
|
[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV. |
TimeoutSt->IdleSt |
175 |
Covered |
T16 |
|
TimeoutSt->Phase0St |
166 |
Covered |
T16 |
|
Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
| Line No. | Total | Covered | Percent |
Branches |
|
26 |
26 |
100.00 |
CASE |
138 |
22 |
22 |
100.00 |
IF |
277 |
2 |
2 |
100.00 |
IF |
299 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 case (state_q)
-2-: 145 if (((accu_trig_i && en_i) && (!clr_i)))
-3-: 151 if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-: 165 if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-: 172 if (timeout_en_i)
-6-: 187 if (clr_i)
-7-: 191 if (cnt_ge)
-8-: 204 if (clr_i)
-9-: 208 if (cnt_ge)
-10-: 222 if (clr_i)
-11-: 226 if (cnt_ge)
-12-: 238 if (clr_i)
-13-: 242 if (cnt_ge)
-14-: 254 if (clr_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T6,T23 |
IdleSt |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T19 |
IdleSt |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
TimeoutSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T19,T23 |
TimeoutSt |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T19 |
TimeoutSt |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T21,T40 |
Phase0St |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T92,T100,T127 |
Phase0St |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T4,T19 |
Phase0St |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T3,T4,T19 |
Phase1St |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T61,T133,T134 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T3,T4,T19 |
Phase1St |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T3,T4,T19 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T109,T116,T135 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
Covered |
T3,T4,T19 |
Phase2St |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
Covered |
T3,T4,T19 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T40,T109,T136 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T3,T4,T19 |
Phase3St |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T3,T4,T19 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T3,T4,T23 |
TerminalSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T3,T4,T19 |
FsmErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T14,T15 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T14,T15 |
LineNo. Expression
-1-: 277 if ((accu_fail_i || cnt_error))
Branches:
-1- | Status | Tests |
1 |
Covered |
T13,T14,T15 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 299 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer
Assertion Details
AccuFailToFsmError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
160 |
0 |
0 |
T13 |
21342 |
24 |
0 |
0 |
T14 |
0 |
26 |
0 |
0 |
T15 |
0 |
35 |
0 |
0 |
T46 |
0 |
29 |
0 |
0 |
T47 |
0 |
46 |
0 |
0 |
T48 |
537689 |
0 |
0 |
0 |
T49 |
20719 |
0 |
0 |
0 |
T50 |
128123 |
0 |
0 |
0 |
T51 |
252281 |
0 |
0 |
0 |
T52 |
253728 |
0 |
0 |
0 |
T53 |
923666 |
0 |
0 |
0 |
T54 |
35421 |
0 |
0 |
0 |
T55 |
943925 |
0 |
0 |
0 |
T56 |
20878 |
0 |
0 |
0 |
CheckAccumTrig0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
588 |
0 |
0 |
T4 |
190757 |
3 |
0 |
0 |
T5 |
544461 |
0 |
0 |
0 |
T6 |
126695 |
1 |
0 |
0 |
T8 |
163192 |
0 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
4 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
CheckAccumTrig1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
26 |
0 |
0 |
T8 |
163192 |
0 |
0 |
0 |
T9 |
474054 |
0 |
0 |
0 |
T23 |
167781 |
1 |
0 |
0 |
T24 |
20641 |
0 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
T57 |
67859 |
0 |
0 |
0 |
T58 |
23401 |
0 |
0 |
0 |
T64 |
30307 |
0 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T81 |
21614 |
0 |
0 |
0 |
T94 |
111065 |
0 |
0 |
0 |
T109 |
865872 |
1 |
0 |
0 |
T123 |
0 |
1 |
0 |
0 |
T137 |
0 |
1 |
0 |
0 |
T138 |
0 |
1 |
0 |
0 |
T139 |
0 |
1 |
0 |
0 |
T140 |
0 |
1 |
0 |
0 |
T141 |
0 |
1 |
0 |
0 |
CheckClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
284 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
1 |
0 |
0 |
T5 |
544461 |
0 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
2 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T98 |
0 |
4 |
0 |
0 |
T109 |
0 |
6 |
0 |
0 |
CheckEn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790563850 |
380538016 |
0 |
0 |
T1 |
19350 |
18160 |
0 |
0 |
T2 |
6174 |
6082 |
0 |
0 |
T3 |
28283 |
14806 |
0 |
0 |
T4 |
190757 |
132721 |
0 |
0 |
T5 |
544461 |
543631 |
0 |
0 |
T6 |
126695 |
7842 |
0 |
0 |
T7 |
67227 |
67168 |
0 |
0 |
T19 |
46858 |
9973 |
0 |
0 |
T20 |
18817 |
18729 |
0 |
0 |
T21 |
283872 |
278109 |
0 |
0 |
CheckPhase0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
671 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
3 |
0 |
0 |
T5 |
544461 |
0 |
0 |
0 |
T6 |
126695 |
1 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T19 |
46858 |
1 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
5 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
CheckPhase1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
659 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
3 |
0 |
0 |
T5 |
544461 |
0 |
0 |
0 |
T6 |
126695 |
1 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T19 |
46858 |
1 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
5 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
CheckPhase2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
647 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
3 |
0 |
0 |
T5 |
544461 |
0 |
0 |
0 |
T6 |
126695 |
1 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T19 |
46858 |
1 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
5 |
0 |
0 |
T40 |
0 |
2 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
CheckPhase3_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
629 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
3 |
0 |
0 |
T5 |
544461 |
0 |
0 |
0 |
T6 |
126695 |
1 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T19 |
46858 |
1 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
5 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
CheckTimeout0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
1146 |
0 |
0 |
T1 |
19350 |
1 |
0 |
0 |
T2 |
6174 |
0 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
0 |
0 |
0 |
T5 |
544461 |
0 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T19 |
46858 |
1 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
1 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T60 |
0 |
2 |
0 |
0 |
T95 |
0 |
8 |
0 |
0 |
CheckTimeoutSt1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
130558 |
0 |
0 |
T1 |
19350 |
120 |
0 |
0 |
T2 |
6174 |
0 |
0 |
0 |
T3 |
28283 |
39 |
0 |
0 |
T4 |
190757 |
0 |
0 |
0 |
T5 |
544461 |
0 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T18 |
0 |
653 |
0 |
0 |
T19 |
46858 |
313 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
190 |
0 |
0 |
T40 |
0 |
67 |
0 |
0 |
T57 |
0 |
212 |
0 |
0 |
T58 |
0 |
952 |
0 |
0 |
T60 |
0 |
883 |
0 |
0 |
T95 |
0 |
1003 |
0 |
0 |
CheckTimeoutSt2_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
1057 |
0 |
0 |
T1 |
19350 |
1 |
0 |
0 |
T2 |
6174 |
0 |
0 |
0 |
T3 |
28283 |
0 |
0 |
0 |
T4 |
190757 |
0 |
0 |
0 |
T5 |
544461 |
0 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T18 |
0 |
5 |
0 |
0 |
T19 |
46858 |
0 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
1 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T60 |
0 |
2 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T62 |
0 |
11 |
0 |
0 |
T65 |
0 |
16 |
0 |
0 |
T91 |
0 |
2 |
0 |
0 |
T95 |
0 |
8 |
0 |
0 |
CheckTimeoutStTrig_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
63 |
0 |
0 |
T3 |
28283 |
1 |
0 |
0 |
T4 |
190757 |
0 |
0 |
0 |
T5 |
544461 |
0 |
0 |
0 |
T6 |
126695 |
0 |
0 |
0 |
T7 |
67227 |
0 |
0 |
0 |
T19 |
46858 |
1 |
0 |
0 |
T20 |
18817 |
0 |
0 |
0 |
T21 |
283872 |
0 |
0 |
0 |
T22 |
4897 |
0 |
0 |
0 |
T23 |
167781 |
0 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T65 |
0 |
2 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T92 |
0 |
1 |
0 |
0 |
T100 |
0 |
1 |
0 |
0 |
T142 |
0 |
1 |
0 |
0 |
T143 |
0 |
1 |
0 |
0 |
ErrorStAllEscAsserted_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
1067 |
0 |
0 |
T13 |
21342 |
179 |
0 |
0 |
T14 |
0 |
171 |
0 |
0 |
T15 |
0 |
172 |
0 |
0 |
T46 |
0 |
183 |
0 |
0 |
T47 |
0 |
362 |
0 |
0 |
T48 |
537689 |
0 |
0 |
0 |
T49 |
20719 |
0 |
0 |
0 |
T50 |
128123 |
0 |
0 |
0 |
T51 |
252281 |
0 |
0 |
0 |
T52 |
253728 |
0 |
0 |
0 |
T53 |
923666 |
0 |
0 |
0 |
T54 |
35421 |
0 |
0 |
0 |
T55 |
943925 |
0 |
0 |
0 |
T56 |
20878 |
0 |
0 |
0 |
ErrorStIsTerminal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
887 |
0 |
0 |
T13 |
21342 |
149 |
0 |
0 |
T14 |
0 |
141 |
0 |
0 |
T15 |
0 |
142 |
0 |
0 |
T46 |
0 |
153 |
0 |
0 |
T47 |
0 |
302 |
0 |
0 |
T48 |
537689 |
0 |
0 |
0 |
T49 |
20719 |
0 |
0 |
0 |
T50 |
128123 |
0 |
0 |
0 |
T51 |
252281 |
0 |
0 |
0 |
T52 |
253728 |
0 |
0 |
0 |
T53 |
923666 |
0 |
0 |
0 |
T54 |
35421 |
0 |
0 |
0 |
T55 |
943925 |
0 |
0 |
0 |
T56 |
20878 |
0 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
790843828 |
790696413 |
0 |
0 |
T1 |
19350 |
19268 |
0 |
0 |
T2 |
6174 |
6083 |
0 |
0 |
T3 |
28283 |
28195 |
0 |
0 |
T4 |
190757 |
190748 |
0 |
0 |
T5 |
544461 |
544439 |
0 |
0 |
T6 |
126695 |
126687 |
0 |
0 |
T7 |
67227 |
67169 |
0 |
0 |
T19 |
46858 |
46764 |
0 |
0 |
T20 |
18817 |
18730 |
0 |
0 |
T21 |
283872 |
283663 |
0 |
0 |