Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	70598	1			T3	10		T35	2		T57	3
class_i[0x1]	61531	1			T60	4		T75	7		T41	40
class_i[0x2]	48551	1			T3	5		T35	487		T18	1
class_i[0x3]	49841	1			T3	10		T57	67		T17	160

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	63008	1			T3	5		T35	30		T57	14
alert[0x1]	54948	1			T3	11		T35	446		T57	22
alert[0x2]	55213	1			T3	4		T35	7		T57	11
alert[0x3]	57352	1			T3	5		T35	6		T57	23

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

230226

1

T3

25

T35

489

T57

70

esc_ping_fail

295

1

T8

7

T9

11

T10

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	62922	1			T3	5		T35	30		T57	14
esc_integrity_fail	alert[0x1]	54861	1			T3	11		T35	446		T57	22
esc_integrity_fail	alert[0x2]	55149	1			T3	4		T35	7		T57	11
esc_integrity_fail	alert[0x3]	57294	1			T3	5		T35	6		T57	23
esc_ping_fail	alert[0x0]	86	1			T8	2		T9	2		T10	1
esc_ping_fail	alert[0x1]	87	1			T8	3		T9	5		T117	1
esc_ping_fail	alert[0x2]	64	1			T8	2		T9	1		T10	1
esc_ping_fail	alert[0x3]	58	1			T9	3		T10	1		T96	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	70528	1			T3	10		T35	2		T57	3
esc_integrity_fail	class_i[0x1]	61448	1			T60	4		T75	7		T41	40
esc_integrity_fail	class_i[0x2]	48461	1			T3	5		T35	487		T18	1
esc_integrity_fail	class_i[0x3]	49789	1			T3	10		T57	67		T17	160
esc_ping_fail	class_i[0x0]	70	1			T10	1		T96	2		T48	1
esc_ping_fail	class_i[0x1]	83	1			T96	1		T117	1		T48	4
esc_ping_fail	class_i[0x2]	90	1			T8	7		T9	1		T10	1
esc_ping_fail	class_i[0x3]	52	1			T9	10		T10	1		T96	1