Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	802478565	0	0	644
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	802478565	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	802478565	802316967	0	0
tb.dut.CheckAccuCntDw	0	0	644	644	0	0
tb.dut.CheckEscCntDw	0	0	644	644	0	0
tb.dut.CheckNAlerts	0	0	644	644	0	0
tb.dut.CheckNClasses	0	0	644	644	0	0
tb.dut.CheckNEscSev	0	0	644	644	0	0
tb.dut.CrashdumpKnownO_A	0	0	802478565	802316967	0	0
tb.dut.EdnKnownO_A	0	0	802478565	802316967	0	0
tb.dut.EscPKnownO_A	0	0	802478565	802316967	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	802478565	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	802478565	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	802478565	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	802478565	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	802478565	70	0	0
tb.dut.IrqAKnownO_A	0	0	802478565	802316967	0	0
tb.dut.IrqBKnownO_A	0	0	802478565	802316967	0	0
tb.dut.IrqCKnownO_A	0	0	802478565	802316967	0	0
tb.dut.IrqDKnownO_A	0	0	802478565	802316967	0	0
tb.dut.TlAReadyKnownO_A	0	0	802478565	802316967	0	0
tb.dut.TlDValidKnownO_A	0	0	802478565	802316967	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	826835224	3734245	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	826835224	21090	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	826835224	21004	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	826835224	21151	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	826835224	21598	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	826835224	20854	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	826835224	21146	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	826835224	20320	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	826835224	21094	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	826835224	20612	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	826835224	21337	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	826835224	21009	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	826835224	20970	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	826835224	21126	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	826835224	20503	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	826835224	21343	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	826835224	20931	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	826835224	21166	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	826835224	21138	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	826835224	21068	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	826835224	20864	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	826835224	21004	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	826835224	20907	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	826835224	21296	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	826835224	21219	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	826835224	20611	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	826835224	21344	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	826835224	21162	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	826835224	21281	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	826835224	20735	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	826835224	21504	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	826835224	21012	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	826835224	20980	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	826835224	20470	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	826835224	21038	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	826835224	21719	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	826835224	20919	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	826835224	20731	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	826835224	20788	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	826835224	21238	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	826835224	20639	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	826835224	21071	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	826835224	20576	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	826835224	20966	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	826835224	21090	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	826835224	21260	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	826835224	21128	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	826835224	21269	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	826835224	21022	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	826835224	20787	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	826835224	21236	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	826835224	20555	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	826835224	21107	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	826835224	20572	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	826835224	21207	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	826835224	20726	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	826835224	20536	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	826835224	21218	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	826835224	20500	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	826835224	21633	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	826835224	21050	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	826835224	20757	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	826835224	21015	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	826835224	20792	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	826835224	21275	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	826835224	20887	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	826835224	21238	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	826835224	21146	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	826835224	20889	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	826835224	21161	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	826835224	39865	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	826835224	20904	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	826835224	20922	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	826835224	21274	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	826835224	20603	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	826835224	21048	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	826835224	20840	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	826835224	20998	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	826835224	20726	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	802478565	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	802478565	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	802478565	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	802478565	2024	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	802478565	212414	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	802478565	412605817	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	802478565	173	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	802478565	886	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	802478565	59	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	802478565	423	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	802319401	304537100	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	802478565	1017	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	802478565	1003	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	802478565	980	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	802478565	959	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	802478565	1687	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	802478565	209229	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	802478565	1544	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	802478565	84	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	802478565	1280	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	802478565	1070	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	644	644	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	802478565	802316967	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	802478565	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	802478565	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	802478565	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	802478565	4651	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	802478565	186613	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	802478565	473551167	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	802478565	234	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	802478565	567	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	802478565	22	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	802478565	289	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	802319401	376565645	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	802478565	662	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	802478565	647	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	802478565	635	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	802478565	621	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	802478565	871	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	802478565	117665	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	802478565	762	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	802478565	87	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	802478565	1302	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	802478565	1092	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	644	644	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	802478565	802316967	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	802478565	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	802478565	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	802478565	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	802478565	2365	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	802478565	167547	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	802478565	448927312	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	802478565	222	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	802478565	558	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	802478565	33	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	802478565	250	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	802319401	370649089	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	802478565	652	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	802478565	640	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	802478565	630	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	802478565	614	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	802478565	1289	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	802478565	176566	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	802478565	1190	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	802478565	66	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	802478565	1230	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	802478565	1020	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	644	644	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	802478565	802316967	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	802478565	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	802478565	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	802478565	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	802478565	2587	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	802478565	167817	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	802478565	495769485	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	802478565	228	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	802478565	499	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	802478565	17	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	802478565	222	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	802319401	418239266	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	802478565	586	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	802478565	581	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	802478565	568	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	802478565	562	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	802478565	1395	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	802478565	167763	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	802478565	1302	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	802478565	76	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	802478565	1226	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	802478565	1016	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	644	644	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	802478565	802316967	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	826835224	144538970	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	826835224	826192434	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	826835224	826192434	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	826835224	234498219	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	826835224	826192434	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	826835224	826192434	0	0
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