Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	179	1			T1	1		T56	1		T57	1
index[0x1]	170	1			T1	1		T58	1		T17	2
index[0x2]	190	1			T21	1		T23	1		T15	1
index[0x3]	186	1			T1	1		T35	1		T17	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	224	1			T1	1		T36	1		T40	2
lens_less_than_1000[1]	154	1			T1	1		T35	1		T57	1
lens_less_than_1000[2]	119	1			T1	1		T17	1		T60	1
lens_less_than_1000[3]	64	1			T21	1		T36	1		T41	3
lens_less_than_1000[4]	63	1			T23	1		T77	2		T49	1
lens_less_than_1000[5]	41	1			T56	1		T41	1		T64	3
lens_less_than_1000[6]	17	1			T251	1		T95	1		T110	1
lens_less_than_1000[7]	18	1			T41	1		T52	1		T118	1
lens_less_than_1000[8]	10	1			T252	1		T253	1		T254	1
lens_less_than_1000[9]	3	1			T69	1		T255	1		T256	1
len_2	12	1			T59	1		T65	1		T257	2

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[8]]	0	1	1
[index[0x1]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	56	1			T78	1		T258	1		T52	2
index[0x0]	lens_less_than_1000[1]	37	1			T1	1		T57	1		T60	1
index[0x0]	lens_less_than_1000[2]	26	1			T60	1		T41	1		T65	2
index[0x0]	lens_less_than_1000[3]	16	1			T36	1		T259	2		T260	1
index[0x0]	lens_less_than_1000[4]	16	1			T66	1		T251	1		T261	2
index[0x0]	lens_less_than_1000[5]	9	1			T56	1		T52	1		T88	1
index[0x0]	lens_less_than_1000[6]	6	1			T262	1		T263	3		T264	1
index[0x0]	lens_less_than_1000[7]	5	1			T69	1		T74	1		T265	1
index[0x0]	lens_less_than_1000[9]	1	1			T255	1		-	-		-	-
index[0x0]	len_2	7	1			T59	1		T257	2		T246	1
index[0x1]	lens_less_than_1000[0]	46	1			T1	1		T36	1		T101	1
index[0x1]	lens_less_than_1000[1]	40	1			T58	1		T17	2		T101	1
index[0x1]	lens_less_than_1000[2]	29	1			T266	1		T65	1		T267	1
index[0x1]	lens_less_than_1000[3]	13	1			T236	1		T268	1		T269	1
index[0x1]	lens_less_than_1000[4]	13	1			T52	1		T65	1		T66	1
index[0x1]	lens_less_than_1000[5]	12	1			T52	2		T270	1		T254	1
index[0x1]	lens_less_than_1000[6]	4	1			T246	1		T214	1		T271	1
index[0x1]	lens_less_than_1000[7]	6	1			T118	1		T272	1		T69	1
index[0x1]	lens_less_than_1000[8]	5	1			T252	1		T273	1		T274	1
index[0x1]	len_2	2	1			T65	1		T275	1		-	-
index[0x2]	lens_less_than_1000[0]	60	1			T40	2		T60	1		T41	1
index[0x2]	lens_less_than_1000[1]	37	1			T15	1		T62	1		T43	1
index[0x2]	lens_less_than_1000[2]	29	1			T276	1		T55	1		T102	1
index[0x2]	lens_less_than_1000[3]	20	1			T21	1		T41	2		T83	1
index[0x2]	lens_less_than_1000[4]	22	1			T23	1		T77	2		T49	1
index[0x2]	lens_less_than_1000[5]	9	1			T41	1		T64	3		T91	1
index[0x2]	lens_less_than_1000[6]	4	1			T110	1		T73	1		T277	1
index[0x2]	lens_less_than_1000[7]	4	1			T52	1		T71	1		T112	1
index[0x2]	lens_less_than_1000[8]	2	1			T253	1		T278	1		-	-
index[0x2]	lens_less_than_1000[9]	1	1			T256	1		-	-		-	-
index[0x2]	len_2	2	1			T279	1		T244	1		-	-
index[0x3]	lens_less_than_1000[0]	62	1			T82	1		T43	1		T258	1
index[0x3]	lens_less_than_1000[1]	40	1			T35	1		T62	1		T63	1
index[0x3]	lens_less_than_1000[2]	35	1			T1	1		T17	1		T280	2
index[0x3]	lens_less_than_1000[3]	15	1			T41	1		T225	1		T281	1
index[0x3]	lens_less_than_1000[4]	12	1			T65	1		T224	1		T66	1
index[0x3]	lens_less_than_1000[5]	11	1			T102	1		T282	1		T125	1
index[0x3]	lens_less_than_1000[6]	3	1			T251	1		T95	1		T74	1
index[0x3]	lens_less_than_1000[7]	3	1			T41	1		T283	1		T284	1
index[0x3]	lens_less_than_1000[8]	3	1			T254	1		T214	1		T285	1
index[0x3]	lens_less_than_1000[9]	1	1			T69	1		-	-		-	-
index[0x3]	len_2	1	1			T222	1		-	-		-	-