Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.15	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	1	39	97.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	1	39	97.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	84	1			T35	1		T17	1		T41	1
class_index[0x1]	87	1			T36	2		T41	6		T82	1
class_index[0x2]	66	1			T25	1		T36	1		T59	1
class_index[0x3]	76	1			T60	1		T41	3		T101	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	117	1			T25	1		T17	1		T41	4
intr_timeout_cnt[1]	79	1			T59	1		T60	2		T41	2
intr_timeout_cnt[2]	30	1			T36	2		T41	1		T82	1
intr_timeout_cnt[3]	17	1			T36	1		T62	1		T52	1
intr_timeout_cnt[4]	7	1			T35	1		T41	1		T286	1
intr_timeout_cnt[5]	12	1			T62	1		T65	1		T95	1
intr_timeout_cnt[6]	9	1			T41	1		T88	1		T69	1
intr_timeout_cnt[7]	19	1			T88	1		T238	1		T254	1
intr_timeout_cnt[8]	18	1			T41	1		T52	2		T282	1
intr_timeout_cnt[9]	5	1			T41	2		T238	1		T287	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	1	39	97.50	1

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	36	1			T17	1		T44	1		T87	1
class_index[0x0]	intr_timeout_cnt[1]	20	1			T226	1		T282	1		T238	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T91	1		T288	1		T286	1
class_index[0x0]	intr_timeout_cnt[3]	7	1			T62	1		T52	1		T125	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T35	1		T289	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	1	1			T71	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	3	1			T242	1		T290	1		T291	1
class_index[0x0]	intr_timeout_cnt[7]	3	1			T292	1		T293	1		T294	1
class_index[0x0]	intr_timeout_cnt[8]	6	1			T52	1		T282	1		T295	1
class_index[0x0]	intr_timeout_cnt[9]	1	1			T41	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	41	1			T41	3		T90	1		T93	1
class_index[0x1]	intr_timeout_cnt[1]	15	1			T41	2		T90	1		T92	1
class_index[0x1]	intr_timeout_cnt[2]	7	1			T36	1		T82	1		T90	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T36	1		T73	1		T296	1
class_index[0x1]	intr_timeout_cnt[4]	1	1			T297	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	6	1			T95	1		T295	1		T298	1
class_index[0x1]	intr_timeout_cnt[6]	3	1			T69	1		T232	1		T38	1
class_index[0x1]	intr_timeout_cnt[7]	7	1			T88	1		T254	1		T292	1
class_index[0x1]	intr_timeout_cnt[8]	3	1			T254	1		T287	1		T299	1
class_index[0x1]	intr_timeout_cnt[9]	1	1			T41	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	17	1			T25	1		T41	1		T53	1
class_index[0x2]	intr_timeout_cnt[1]	25	1			T59	1		T60	1		T91	1
class_index[0x2]	intr_timeout_cnt[2]	10	1			T36	1		T44	1		T88	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T69	1		T300	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	1	1			T286	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	2	1			T62	1		T301	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	2	1			T88	1		T248	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T238	1		T302	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	5	1			T41	1		T52	1		T232	1
class_index[0x3]	intr_timeout_cnt[0]	23	1			T101	1		T115	1		T116	1
class_index[0x3]	intr_timeout_cnt[1]	19	1			T60	1		T62	1		T44	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T41	1		T116	1		T295	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T91	1		T289	3		T297	1
class_index[0x3]	intr_timeout_cnt[4]	3	1			T41	1		T303	1		T304	1
class_index[0x3]	intr_timeout_cnt[5]	3	1			T65	1		T254	1		T246	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T41	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	7	1			T291	1		T246	1		T305	1
class_index[0x3]	intr_timeout_cnt[8]	4	1			T69	1		T306	1		T307	1
class_index[0x3]	intr_timeout_cnt[9]	3	1			T238	1		T287	1		T297	1