Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	361718	1			T14	8		T126	1		T171	8
all_values[1]	361718	1			T14	8		T126	1		T171	8
all_values[2]	361718	1			T14	8		T126	1		T171	8
all_values[3]	361718	1			T14	8		T126	1		T171	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

720827

1

T14

11

T126

4

T171

19

auto[1]

726045

1

T14

21

T171

13

T172

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

859111

1

T14

22

T126

4

T171

23

auto[1]

587761

1

T14

10

T171

9

T172

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103237	1			T14	4		T126	1		T171	2
all_values[0]	auto[0]	auto[1]	77218	1			T14	1		T171	2		T172	2
all_values[0]	auto[1]	auto[0]	104113	1			T14	3		T171	4		T172	1
all_values[0]	auto[1]	auto[1]	77150	1			T172	2		T192	2		T234	4
all_values[1]	auto[0]	auto[0]	108190	1			T126	1		T171	4		T172	5
all_values[1]	auto[0]	auto[1]	72253	1			T14	2		T171	1		T192	1
all_values[1]	auto[1]	auto[0]	109101	1			T14	6		T171	2		T192	2
all_values[1]	auto[1]	auto[1]	72174	1			T171	1		T234	2		T361	1
all_values[2]	auto[0]	auto[0]	106770	1			T14	2		T126	1		T171	2
all_values[2]	auto[0]	auto[1]	73268	1			T171	3		T234	2		T362	3
all_values[2]	auto[1]	auto[0]	108224	1			T14	5		T171	2		T172	4
all_values[2]	auto[1]	auto[1]	73456	1			T14	1		T171	1		T361	1
all_values[3]	auto[0]	auto[0]	108897	1			T14	1		T126	1		T171	5
all_values[3]	auto[0]	auto[1]	70994	1			T14	1		T172	1		T192	3
all_values[3]	auto[1]	auto[0]	110579	1			T14	1		T171	2		T192	3
all_values[3]	auto[1]	auto[1]	71248	1			T14	5		T171	1		T172	1