Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	361718	1			T14	8		T126	1		T171	8
all_pins[1]	361718	1			T14	8		T126	1		T171	8
all_pins[2]	361718	1			T14	8		T126	1		T171	8
all_pins[3]	361718	1			T14	8		T126	1		T171	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1152844	1			T14	26		T126	4		T171	29
values[0x1]	294028	1			T14	6		T171	3		T172	3
transitions[0x0=>0x1]	194785	1			T14	5		T171	3		T172	2
transitions[0x1=>0x0]	195054	1			T14	5		T171	3		T172	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	284568	1			T14	8		T126	1		T171	8
all_pins[0]	values[0x1]	77150	1			T172	2		T192	2		T234	4
all_pins[0]	transitions[0x0=>0x1]	76445	1			T172	1		T192	1		T234	2
all_pins[0]	transitions[0x1=>0x0]	70812	1			T14	5		T171	1		T361	1
all_pins[1]	values[0x0]	289544	1			T14	8		T126	1		T171	7
all_pins[1]	values[0x1]	72174	1			T171	1		T234	2		T361	1
all_pins[1]	transitions[0x0=>0x1]	39276	1			T171	1		T361	1		T240	3
all_pins[1]	transitions[0x1=>0x0]	44252	1			T172	2		T192	2		T234	2
all_pins[2]	values[0x0]	288262	1			T14	7		T126	1		T171	7
all_pins[2]	values[0x1]	73456	1			T14	1		T171	1		T361	1
all_pins[2]	transitions[0x0=>0x1]	40303	1			T14	1		T171	1		T361	1
all_pins[2]	transitions[0x1=>0x0]	39021	1			T171	1		T234	2		T361	1
all_pins[3]	values[0x0]	290470	1			T14	3		T126	1		T171	7
all_pins[3]	values[0x1]	71248	1			T14	5		T171	1		T172	1
all_pins[3]	transitions[0x0=>0x1]	38761	1			T14	4		T171	1		T172	1
all_pins[3]	transitions[0x1=>0x0]	40969	1			T171	1		T361	1		T363	1