Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T14	7		T171	7		T172	4
all_values[1]	269	1			T14	7		T171	7		T172	4
all_values[2]	269	1			T14	7		T171	7		T172	4
all_values[3]	269	1			T14	7		T171	7		T172	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

576

1

T14

15

T171

11

T172

12

auto[1]

500

1

T14

13

T171

17

T172

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

465

1

T14

11

T171

13

T172

7

auto[1]

611

1

T14

17

T171

15

T172

9

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

661

1

T14

16

T171

19

T172

9

auto[1]

415

1

T14

12

T171

9

T172

7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

64

1

T14

3

T192

1

T234

1

all_values[0]

auto[0]

auto[0]

auto[1]

24

1

T14

1

T171

1

T234

1

all_values[0]

auto[0]

auto[1]

auto[0]

47

1

T14

1

T171

4

T240

2

all_values[0]

auto[0]

auto[1]

auto[1]

30

1

T172

1

T192

2

T234

2

all_values[0]

auto[1]

auto[0]

auto[1]

59

1

T14

2

T171

1

T172

3

all_values[0]

auto[1]

auto[1]

auto[1]

45

1

T171

1

T234

1

T361

2

all_values[1]

auto[0]

auto[0]

auto[0]

53

1

T14

1

T171

2

T172

2

all_values[1]

auto[0]

auto[0]

auto[1]

23

1

T171

1

T364

2

T365

1

all_values[1]

auto[0]

auto[1]

auto[0]

66

1

T14

2

T171

2

T192

1

all_values[1]

auto[0]

auto[1]

auto[1]

20

1

T234

1

T361

1

T240

1

all_values[1]

auto[1]

auto[0]

auto[1]

62

1

T14

2

T172

2

T192

3

all_values[1]

auto[1]

auto[1]

auto[1]

45

1

T14

2

T171

2

T192

1

all_values[2]

auto[0]

auto[0]

auto[0]

75

1

T14

1

T171

1

T172

3

all_values[2]

auto[0]

auto[0]

auto[1]

24

1

T171

2

T234

1

T362

2

all_values[2]

auto[0]

auto[1]

auto[0]

58

1

T14

3

T171

1

T172

1

all_values[2]

auto[0]

auto[1]

auto[1]

19

1

T14

1

T171

1

T240

1

all_values[2]

auto[1]

auto[0]

auto[1]

41

1

T14

2

T361

1

T362

1

all_values[2]

auto[1]

auto[1]

auto[1]

52

1

T171

2

T234

1

T361

1

all_values[3]

auto[0]

auto[0]

auto[0]

63

1

T171

2

T172

1

T234

3

all_values[3]

auto[0]

auto[0]

auto[1]

22

1

T192

2

T234

1

T361

2

all_values[3]

auto[0]

auto[1]

auto[0]

39

1

T171

1

T192

2

T361

1

all_values[3]

auto[0]

auto[1]

auto[1]

34

1

T14

3

T171

1

T172

1

all_values[3]

auto[1]

auto[0]

auto[1]

66

1

T14

3

T171

1

T172

1

all_values[3]

auto[1]

auto[1]

auto[1]

45

1

T14

1

T171

2

T172

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal