Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	86990	1			T3	463		T5	52		T18	1436
accum_cnt_1000	223125	1			T1	57		T3	574		T5	695
accum_cnt_100	27689	1			T1	18		T3	31		T20	16
accum_cnt_50	70578	1			T1	34		T3	1102		T20	11
accum_cnt_10	202171	1			T1	27		T2	1		T3	9
accum_cnt_0	423311	1			T1	352		T2	3		T3	2181

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	267178	1			T1	122		T2	1		T3	1090
class_index[0x1]	267178	1			T1	122		T2	1		T3	1090
class_index[0x2]	267176	1			T1	122		T2	1		T3	1090
class_index[0x3]	267175	1			T1	122		T2	1		T3	1090

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	20772	1			T18	516		T40	540		T60	132
class_index[0x0]	accum_cnt_1000	58782	1			T1	57		T58	33		T18	573
class_index[0x0]	accum_cnt_100	8759	1			T1	18		T20	16		T56	78
class_index[0x0]	accum_cnt_50	24204	1			T1	24		T20	11		T22	2
class_index[0x0]	accum_cnt_10	61429	1			T1	17		T2	1		T20	2
class_index[0x0]	accum_cnt_0	84409	1			T1	6		T3	1090		T4	803
class_index[0x1]	accum_cnt_2000	21633	1			T60	200		T75	33		T61	211
class_index[0x1]	accum_cnt_1000	52938	1			T58	38		T7	891		T60	521
class_index[0x1]	accum_cnt_100	7001	1			T58	14		T7	86		T36	42
class_index[0x1]	accum_cnt_50	15522	1			T1	6		T58	12		T7	56
class_index[0x1]	accum_cnt_10	54171	1			T1	4		T4	794		T21	2
class_index[0x1]	accum_cnt_0	105543	1			T1	112		T2	1		T3	1090
class_index[0x2]	accum_cnt_2000	22446	1			T5	52		T18	509		T40	529
class_index[0x2]	accum_cnt_1000	60391	1			T5	695		T35	1		T16	960
class_index[0x2]	accum_cnt_100	6454	1			T5	34		T16	184		T18	32
class_index[0x2]	accum_cnt_50	14518	1			T3	1086		T5	25		T22	6
class_index[0x2]	accum_cnt_10	43950	1			T3	4		T5	3		T22	5
class_index[0x2]	accum_cnt_0	111694	1			T1	122		T2	1		T4	803
class_index[0x3]	accum_cnt_2000	22139	1			T3	463		T18	411		T78	510
class_index[0x3]	accum_cnt_1000	51014	1			T3	574		T56	24		T58	12
class_index[0x3]	accum_cnt_100	5475	1			T3	31		T56	24		T58	29
class_index[0x3]	accum_cnt_50	16334	1			T1	4		T3	16		T56	18
class_index[0x3]	accum_cnt_10	42621	1			T1	6		T3	5		T4	803
class_index[0x3]	accum_cnt_0	121665	1			T1	112		T2	1		T3	1