Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4516	1			T77	1		T62	3		T63	38
alert[0x1]	3319	1			T9	1		T60	121		T96	1
alert[0x2]	5455	1			T60	255		T96	1		T63	2
alert[0x3]	10122	1			T17	6		T77	47		T63	12
alert[0x4]	2952	1			T41	16		T236	3		T65	85
alert[0x5]	6914	1			T60	457		T104	1		T62	11
alert[0x6]	3905	1			T236	8		T52	29		T54	1
alert[0x7]	10548	1			T8	1		T62	55		T63	96
alert[0x8]	4485	1			T59	1		T9	1		T63	88
alert[0x9]	4132	1			T8	1		T41	2		T10	1
alert[0xa]	3128	1			T35	12		T41	20		T96	1
alert[0xb]	7710	1			T1	3		T17	5		T60	434
alert[0xc]	3962	1			T59	32		T9	1		T60	4
alert[0xd]	5302	1			T60	396		T41	4		T62	24
alert[0xe]	3288	1			T1	12		T60	131		T41	1
alert[0xf]	5083	1			T8	1		T9	1		T10	2
alert[0x10]	5347	1			T9	1		T60	105		T10	1
alert[0x11]	3303	1			T17	13		T63	50		T44	10
alert[0x12]	4201	1			T60	4		T65	13		T308	2
alert[0x13]	15081	1			T8	1		T9	1		T60	47
alert[0x14]	1928	1			T7	1		T10	1		T62	3
alert[0x15]	8701	1			T4	1		T8	1		T60	313
alert[0x16]	11729	1			T4	1		T9	1		T60	20
alert[0x17]	2197	1			T35	7		T96	1		T101	20
alert[0x18]	4800	1			T17	2		T62	1		T63	75
alert[0x19]	7683	1			T1	1		T59	1		T60	534
alert[0x1a]	5081	1			T36	3		T41	1		T63	271
alert[0x1b]	9337	1			T9	1		T60	18		T62	8
alert[0x1c]	9423	1			T17	26		T59	1		T41	5
alert[0x1d]	13488	1			T7	1		T8	1		T62	54
alert[0x1e]	6691	1			T36	5		T60	10		T62	2
alert[0x1f]	6515	1			T9	1		T41	1		T10	2
alert[0x20]	12551	1			T8	1		T62	3		T48	1
alert[0x21]	2629	1			T35	1		T17	1		T62	30
alert[0x22]	3055	1			T35	8		T17	6		T41	1
alert[0x23]	2594	1			T1	1		T60	718		T96	1
alert[0x24]	4073	1			T36	4		T96	1		T63	33
alert[0x25]	11818	1			T17	117		T59	1		T60	103
alert[0x26]	5636	1			T36	1		T8	1		T52	8
alert[0x27]	4828	1			T1	9		T60	251		T41	57
alert[0x28]	15002	1			T77	16		T63	38		T236	11
alert[0x29]	2574	1			T60	129		T63	20		T52	12
alert[0x2a]	15700	1			T9	1		T60	70		T63	209
alert[0x2b]	4405	1			T36	1		T9	2		T60	1324
alert[0x2c]	7437	1			T60	11		T117	1		T62	3
alert[0x2d]	3489	1			T9	1		T63	18		T48	1
alert[0x2e]	6644	1			T17	3		T9	1		T60	103
alert[0x2f]	9528	1			T1	7		T62	54		T52	24
alert[0x30]	4693	1			T18	3		T7	3		T9	1
alert[0x31]	7505	1			T35	10		T36	11		T9	1
alert[0x32]	6524	1			T60	17		T117	1		T62	40
alert[0x33]	1864	1			T17	3		T96	1		T62	10
alert[0x34]	4086	1			T8	1		T52	16		T65	7
alert[0x35]	8515	1			T17	34		T62	29		T44	3
alert[0x36]	3096	1			T9	2		T60	2		T52	25
alert[0x37]	4992	1			T77	1		T62	138		T63	11
alert[0x38]	6015	1			T63	47		T236	9		T48	1
alert[0x39]	3298	1			T62	64		T309	418		T310	1
alert[0x3a]	3986	1			T8	1		T9	1		T62	10
alert[0x3b]	9113	1			T8	1		T63	145		T236	1
alert[0x3c]	4851	1			T62	112		T63	129		T50	1
alert[0x3d]	6872	1			T60	1080		T41	17		T62	58
alert[0x3e]	4258	1			T1	9		T8	1		T60	91
alert[0x3f]	9581	1			T41	123		T77	2		T63	1116
alert[0x40]	6349	1			T10	1		T62	4		T88	17

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	107301	1			T1	21		T17	205		T36	25
class_i[0x1]	101341	1			T1	21		T4	2		T18	3
class_i[0x2]	117617	1			T7	5		T41	257		T10	3
class_i[0x3]	81628	1			T35	38		T17	11		T59	34

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

407195

1

T1

42

T35

38

T17

216

alert_ping_fail

692

1

T4

2

T7

5

T8

12

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4508	1			T77	1		T62	3		T63	38
alert_integrity_fail	alert[0x1]	3309	1			T60	121		T77	5		T101	1
alert_integrity_fail	alert[0x2]	5444	1			T60	255		T63	2		T309	16
alert_integrity_fail	alert[0x3]	10113	1			T17	6		T77	47		T63	12
alert_integrity_fail	alert[0x4]	2943	1			T41	16		T236	3		T65	85
alert_integrity_fail	alert[0x5]	6894	1			T60	457		T62	11		T63	6
alert_integrity_fail	alert[0x6]	3889	1			T236	8		T52	29		T88	47
alert_integrity_fail	alert[0x7]	10539	1			T62	55		T63	96		T52	10
alert_integrity_fail	alert[0x8]	4467	1			T59	1		T63	88		T88	33
alert_integrity_fail	alert[0x9]	4120	1			T41	2		T77	1		T63	255
alert_integrity_fail	alert[0xa]	3116	1			T35	12		T41	20		T236	6
alert_integrity_fail	alert[0xb]	7701	1			T1	3		T17	5		T60	434
alert_integrity_fail	alert[0xc]	3948	1			T59	32		T60	4		T62	175
alert_integrity_fail	alert[0xd]	5293	1			T60	396		T41	4		T62	24
alert_integrity_fail	alert[0xe]	3276	1			T1	12		T60	131		T41	1
alert_integrity_fail	alert[0xf]	5074	1			T63	58		T52	27		T90	72
alert_integrity_fail	alert[0x10]	5341	1			T60	105		T77	1		T62	30
alert_integrity_fail	alert[0x11]	3298	1			T17	13		T63	50		T44	10
alert_integrity_fail	alert[0x12]	4189	1			T60	4		T65	13		T92	27
alert_integrity_fail	alert[0x13]	15069	1			T60	47		T62	1		T63	1
alert_integrity_fail	alert[0x14]	1909	1			T62	3		T90	10		T66	32
alert_integrity_fail	alert[0x15]	8692	1			T60	313		T62	3		T52	204
alert_integrity_fail	alert[0x16]	11708	1			T60	20		T101	4		T65	1
alert_integrity_fail	alert[0x17]	2186	1			T35	7		T101	20		T62	895
alert_integrity_fail	alert[0x18]	4791	1			T17	2		T62	1		T63	75
alert_integrity_fail	alert[0x19]	7668	1			T1	1		T59	1		T60	534
alert_integrity_fail	alert[0x1a]	5074	1			T36	3		T41	1		T63	271
alert_integrity_fail	alert[0x1b]	9327	1			T60	18		T62	8		T52	17
alert_integrity_fail	alert[0x1c]	9411	1			T17	26		T59	1		T41	5
alert_integrity_fail	alert[0x1d]	13478	1			T62	54		T63	27		T52	75
alert_integrity_fail	alert[0x1e]	6683	1			T36	5		T60	10		T62	2
alert_integrity_fail	alert[0x1f]	6499	1			T41	1		T63	137		T236	51
alert_integrity_fail	alert[0x20]	12540	1			T62	3		T52	176		T65	1
alert_integrity_fail	alert[0x21]	2617	1			T35	1		T17	1		T62	30
alert_integrity_fail	alert[0x22]	3045	1			T35	8		T17	6		T41	1
alert_integrity_fail	alert[0x23]	2585	1			T1	1		T60	718		T62	290
alert_integrity_fail	alert[0x24]	4066	1			T36	4		T63	33		T236	6
alert_integrity_fail	alert[0x25]	11816	1			T17	117		T59	1		T60	103
alert_integrity_fail	alert[0x26]	5624	1			T36	1		T52	8		T90	15
alert_integrity_fail	alert[0x27]	4815	1			T1	9		T60	251		T41	57
alert_integrity_fail	alert[0x28]	14992	1			T77	16		T63	38		T236	11
alert_integrity_fail	alert[0x29]	2564	1			T60	129		T63	20		T52	12
alert_integrity_fail	alert[0x2a]	15687	1			T60	70		T63	209		T52	28
alert_integrity_fail	alert[0x2b]	4393	1			T36	1		T60	1324		T62	4
alert_integrity_fail	alert[0x2c]	7426	1			T60	11		T62	3		T272	2
alert_integrity_fail	alert[0x2d]	3477	1			T63	18		T311	483		T251	282
alert_integrity_fail	alert[0x2e]	6631	1			T17	3		T60	103		T41	4
alert_integrity_fail	alert[0x2f]	9514	1			T1	7		T62	54		T52	24
alert_integrity_fail	alert[0x30]	4677	1			T18	3		T60	17		T41	1
alert_integrity_fail	alert[0x31]	7493	1			T35	10		T36	11		T60	2
alert_integrity_fail	alert[0x32]	6512	1			T60	17		T62	40		T63	87
alert_integrity_fail	alert[0x33]	1859	1			T17	3		T62	10		T63	109
alert_integrity_fail	alert[0x34]	4079	1			T52	16		T65	7		T309	1
alert_integrity_fail	alert[0x35]	8512	1			T17	34		T62	29		T44	3
alert_integrity_fail	alert[0x36]	3089	1			T60	2		T52	25		T309	310
alert_integrity_fail	alert[0x37]	4978	1			T77	1		T62	138		T63	11
alert_integrity_fail	alert[0x38]	6007	1			T63	47		T236	9		T88	1
alert_integrity_fail	alert[0x39]	3295	1			T62	64		T309	418		T90	5
alert_integrity_fail	alert[0x3a]	3974	1			T62	10		T311	2		T119	8
alert_integrity_fail	alert[0x3b]	9104	1			T63	145		T236	1		T88	37
alert_integrity_fail	alert[0x3c]	4840	1			T62	112		T63	129		T52	10
alert_integrity_fail	alert[0x3d]	6865	1			T60	1080		T41	17		T62	58
alert_integrity_fail	alert[0x3e]	4247	1			T1	9		T60	91		T41	35
alert_integrity_fail	alert[0x3f]	9573	1			T41	123		T77	2		T63	1116
alert_integrity_fail	alert[0x40]	6342	1			T62	4		T88	17		T89	23
alert_ping_fail	alert[0x0]	8	1			T312	1		T313	1		T314	2
alert_ping_fail	alert[0x1]	10	1			T9	1		T96	1		T48	1
alert_ping_fail	alert[0x2]	11	1			T96	1		T315	1		T313	1
alert_ping_fail	alert[0x3]	9	1			T308	1		T316	1		T313	1
alert_ping_fail	alert[0x4]	9	1			T316	1		T317	1		T279	1
alert_ping_fail	alert[0x5]	20	1			T104	1		T50	1		T308	2
alert_ping_fail	alert[0x6]	16	1			T54	1		T318	1		T319	1
alert_ping_fail	alert[0x7]	9	1			T8	1		T48	1		T308	1
alert_ping_fail	alert[0x8]	18	1			T9	1		T47	1		T320	1
alert_ping_fail	alert[0x9]	12	1			T8	1		T10	1		T310	1
alert_ping_fail	alert[0xa]	12	1			T96	1		T321	1		T322	1
alert_ping_fail	alert[0xb]	9	1			T48	2		T323	1		T314	1
alert_ping_fail	alert[0xc]	14	1			T9	1		T48	1		T324	1
alert_ping_fail	alert[0xd]	9	1			T319	1		T315	1		T229	1
alert_ping_fail	alert[0xe]	12	1			T310	1		T316	1		T320	1
alert_ping_fail	alert[0xf]	9	1			T8	1		T9	1		T10	2
alert_ping_fail	alert[0x10]	6	1			T9	1		T10	1		T315	1
alert_ping_fail	alert[0x11]	5	1			T325	1		T279	1		T326	1
alert_ping_fail	alert[0x12]	12	1			T308	2		T317	1		T229	1
alert_ping_fail	alert[0x13]	12	1			T8	1		T9	1		T48	1
alert_ping_fail	alert[0x14]	19	1			T7	1		T10	1		T327	1
alert_ping_fail	alert[0x15]	9	1			T4	1		T8	1		T259	1
alert_ping_fail	alert[0x16]	21	1			T4	1		T9	1		T10	1
alert_ping_fail	alert[0x17]	11	1			T96	1		T48	1		T319	1
alert_ping_fail	alert[0x18]	9	1			T50	1		T315	1		T312	1
alert_ping_fail	alert[0x19]	15	1			T96	1		T48	1		T316	1
alert_ping_fail	alert[0x1a]	7	1			T320	1		T328	1		T329	1
alert_ping_fail	alert[0x1b]	10	1			T9	1		T308	2		T319	1
alert_ping_fail	alert[0x1c]	12	1			T310	1		T308	1		T316	1
alert_ping_fail	alert[0x1d]	10	1			T7	1		T8	1		T321	1
alert_ping_fail	alert[0x1e]	8	1			T321	1		T320	1		T315	1
alert_ping_fail	alert[0x1f]	16	1			T9	1		T10	2		T327	1
alert_ping_fail	alert[0x20]	11	1			T8	1		T48	1		T50	1
alert_ping_fail	alert[0x21]	12	1			T259	1		T50	1		T316	1
alert_ping_fail	alert[0x22]	10	1			T327	1		T330	1		T322	1
alert_ping_fail	alert[0x23]	9	1			T96	1		T315	1		T331	1
alert_ping_fail	alert[0x24]	7	1			T96	1		T319	2		T325	1
alert_ping_fail	alert[0x25]	2	1			T332	1		T333	1		-	-
alert_ping_fail	alert[0x26]	12	1			T8	1		T323	2		T324	1
alert_ping_fail	alert[0x27]	13	1			T117	1		T48	1		T316	1
alert_ping_fail	alert[0x28]	10	1			T325	1		T279	1		T314	1
alert_ping_fail	alert[0x29]	10	1			T269	3		T331	1		T326	1
alert_ping_fail	alert[0x2a]	13	1			T9	1		T47	1		T316	1
alert_ping_fail	alert[0x2b]	12	1			T9	2		T48	1		T50	1
alert_ping_fail	alert[0x2c]	11	1			T117	1		T54	1		T308	1
alert_ping_fail	alert[0x2d]	12	1			T9	1		T48	1		T308	1
alert_ping_fail	alert[0x2e]	13	1			T9	1		T50	1		T308	1
alert_ping_fail	alert[0x2f]	14	1			T316	1		T319	1		T317	1
alert_ping_fail	alert[0x30]	16	1			T7	3		T9	1		T104	1
alert_ping_fail	alert[0x31]	12	1			T9	1		T323	1		T331	1
alert_ping_fail	alert[0x32]	12	1			T117	1		T316	1		T315	1
alert_ping_fail	alert[0x33]	5	1			T96	1		T325	1		T324	1
alert_ping_fail	alert[0x34]	7	1			T8	1		T316	1		T319	1
alert_ping_fail	alert[0x35]	3	1			T314	1		T333	1		T334	1
alert_ping_fail	alert[0x36]	7	1			T9	2		T326	1		T314	1
alert_ping_fail	alert[0x37]	14	1			T308	2		T323	1		T279	1
alert_ping_fail	alert[0x38]	8	1			T48	1		T308	1		T323	1
alert_ping_fail	alert[0x39]	3	1			T310	1		T335	1		T336	1
alert_ping_fail	alert[0x3a]	12	1			T8	1		T9	1		T320	1
alert_ping_fail	alert[0x3b]	9	1			T8	1		T321	1		T320	1
alert_ping_fail	alert[0x3c]	11	1			T50	1		T319	1		T312	1
alert_ping_fail	alert[0x3d]	7	1			T316	1		T323	1		T314	1
alert_ping_fail	alert[0x3e]	11	1			T8	1		T320	1		T312	1
alert_ping_fail	alert[0x3f]	8	1			T321	1		T319	2		T331	2
alert_ping_fail	alert[0x40]	7	1			T10	1		T312	1		T323	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	107137	1			T1	21		T17	205		T36	25
alert_integrity_fail	class_i[0x1]	101144	1			T1	21		T18	3		T59	2
alert_integrity_fail	class_i[0x2]	117442	1			T41	257		T77	69		T101	17
alert_integrity_fail	class_i[0x3]	81472	1			T35	38		T17	11		T59	34
alert_ping_fail	class_i[0x0]	164	1			T8	1		T9	1		T10	2
alert_ping_fail	class_i[0x1]	197	1			T4	2		T8	10		T9	17
alert_ping_fail	class_i[0x2]	175	1			T7	5		T10	3		T117	3
alert_ping_fail	class_i[0x3]	156	1			T8	1		T9	1		T10	3