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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.68 99.99 98.66 100.00 100.00 100.00 99.38 99.72


Total test records in report: 849
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T773 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2445339926 Jan 07 01:41:46 PM PST 24 Jan 07 01:44:27 PM PST 24 4541939134 ps
T774 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1855845673 Jan 07 01:42:05 PM PST 24 Jan 07 01:42:21 PM PST 24 99747177 ps
T775 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3065696453 Jan 07 01:42:35 PM PST 24 Jan 07 01:42:56 PM PST 24 16354974 ps
T776 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2441815449 Jan 07 01:42:40 PM PST 24 Jan 07 01:43:05 PM PST 24 57143230 ps
T777 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.4160622598 Jan 07 01:41:57 PM PST 24 Jan 07 01:42:19 PM PST 24 904278286 ps
T778 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3123361121 Jan 07 01:42:01 PM PST 24 Jan 07 01:42:16 PM PST 24 379768087 ps
T779 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2977710944 Jan 07 01:41:55 PM PST 24 Jan 07 01:42:15 PM PST 24 82575995 ps
T147 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.890836865 Jan 07 01:41:59 PM PST 24 Jan 07 01:59:32 PM PST 24 30641116789 ps
T165 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1964857114 Jan 07 01:41:36 PM PST 24 Jan 07 01:49:42 PM PST 24 25348478512 ps
T152 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2688667456 Jan 07 01:42:16 PM PST 24 Jan 07 01:50:15 PM PST 24 49271949260 ps
T780 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1262607513 Jan 07 01:42:47 PM PST 24 Jan 07 01:43:40 PM PST 24 2162822870 ps
T781 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.262829167 Jan 07 01:42:01 PM PST 24 Jan 07 01:42:50 PM PST 24 1031797344 ps
T782 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1865767905 Jan 07 01:42:13 PM PST 24 Jan 07 01:42:25 PM PST 24 45651787 ps
T783 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.4290492639 Jan 07 01:42:07 PM PST 24 Jan 07 01:42:21 PM PST 24 21237849 ps
T784 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.89460542 Jan 07 01:41:29 PM PST 24 Jan 07 01:43:31 PM PST 24 26536634923 ps
T160 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.568640766 Jan 07 01:41:40 PM PST 24 Jan 07 01:51:01 PM PST 24 14796208113 ps
T785 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1814142282 Jan 07 01:42:12 PM PST 24 Jan 07 01:42:29 PM PST 24 305767904 ps
T786 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3354467364 Jan 07 01:41:31 PM PST 24 Jan 07 01:41:43 PM PST 24 38154406 ps
T146 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.682033625 Jan 07 01:42:41 PM PST 24 Jan 07 01:47:48 PM PST 24 18288366689 ps
T787 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3822498531 Jan 07 01:43:03 PM PST 24 Jan 07 01:43:18 PM PST 24 10855642 ps
T788 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1798411603 Jan 07 01:41:57 PM PST 24 Jan 07 01:42:13 PM PST 24 275973697 ps
T789 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.4167943440 Jan 07 01:42:14 PM PST 24 Jan 07 01:42:24 PM PST 24 11678963 ps
T790 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1721538983 Jan 07 01:41:37 PM PST 24 Jan 07 01:44:59 PM PST 24 13585464081 ps
T791 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1529389229 Jan 07 01:41:55 PM PST 24 Jan 07 01:42:26 PM PST 24 513357501 ps
T792 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3035815042 Jan 07 01:43:07 PM PST 24 Jan 07 01:43:20 PM PST 24 17476923 ps
T793 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3428728973 Jan 07 01:42:35 PM PST 24 Jan 07 01:42:55 PM PST 24 16262729 ps
T794 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1801121066 Jan 07 01:42:14 PM PST 24 Jan 07 01:42:24 PM PST 24 21542997 ps
T795 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3972768565 Jan 07 01:41:53 PM PST 24 Jan 07 01:42:10 PM PST 24 130869638 ps
T796 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.168433660 Jan 07 01:41:37 PM PST 24 Jan 07 01:42:47 PM PST 24 1085429796 ps
T797 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4250507227 Jan 07 01:41:41 PM PST 24 Jan 07 01:42:13 PM PST 24 253060251 ps
T187 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3553971588 Jan 07 01:41:24 PM PST 24 Jan 07 01:41:55 PM PST 24 157217500 ps
T798 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2318684383 Jan 07 01:41:44 PM PST 24 Jan 07 01:42:10 PM PST 24 260520085 ps
T799 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2621350875 Jan 07 01:42:16 PM PST 24 Jan 07 01:42:38 PM PST 24 382595084 ps
T800 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2707531820 Jan 07 01:42:27 PM PST 24 Jan 07 01:43:04 PM PST 24 422119251 ps
T801 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.240911497 Jan 07 01:41:36 PM PST 24 Jan 07 01:45:59 PM PST 24 22489273569 ps
T161 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.757781090 Jan 07 01:42:01 PM PST 24 Jan 07 01:43:58 PM PST 24 1614326156 ps
T802 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2186571889 Jan 07 01:41:29 PM PST 24 Jan 07 01:41:36 PM PST 24 9407685 ps
T803 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2901448944 Jan 07 01:42:13 PM PST 24 Jan 07 01:42:24 PM PST 24 7311475 ps
T804 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.718548986 Jan 07 01:42:13 PM PST 24 Jan 07 01:42:27 PM PST 24 184041005 ps
T805 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1120815954 Jan 07 01:42:37 PM PST 24 Jan 07 01:43:33 PM PST 24 4252603271 ps
T806 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2202686996 Jan 07 01:42:43 PM PST 24 Jan 07 01:43:04 PM PST 24 7143134 ps
T807 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.709873124 Jan 07 01:42:04 PM PST 24 Jan 07 01:42:14 PM PST 24 12654776 ps
T808 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2972156137 Jan 07 01:41:36 PM PST 24 Jan 07 01:42:06 PM PST 24 296355614 ps
T809 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3176052992 Jan 07 01:41:37 PM PST 24 Jan 07 01:42:08 PM PST 24 1124747305 ps
T178 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3146156116 Jan 07 01:41:46 PM PST 24 Jan 07 01:42:04 PM PST 24 116983304 ps
T810 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1744876511 Jan 07 01:41:54 PM PST 24 Jan 07 01:42:23 PM PST 24 680901179 ps
T811 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.181620128 Jan 07 01:42:00 PM PST 24 Jan 07 01:42:18 PM PST 24 255102689 ps
T133 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.459204423 Jan 07 01:42:32 PM PST 24 Jan 07 01:45:47 PM PST 24 6733008181 ps
T812 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1850818295 Jan 07 01:41:31 PM PST 24 Jan 07 01:41:43 PM PST 24 145445341 ps
T813 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2451660591 Jan 07 01:41:53 PM PST 24 Jan 07 01:43:49 PM PST 24 7426079958 ps
T157 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2221806946 Jan 07 01:41:41 PM PST 24 Jan 07 01:58:15 PM PST 24 17330748704 ps
T164 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2805458475 Jan 07 01:42:43 PM PST 24 Jan 07 01:44:39 PM PST 24 802795321 ps
T814 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3095507347 Jan 07 01:41:53 PM PST 24 Jan 07 01:42:05 PM PST 24 18833755 ps
T815 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.177812078 Jan 07 01:42:00 PM PST 24 Jan 07 01:42:19 PM PST 24 510536906 ps
T816 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2116329782 Jan 07 01:41:51 PM PST 24 Jan 07 01:42:10 PM PST 24 112450354 ps
T817 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1785181348 Jan 07 01:42:29 PM PST 24 Jan 07 01:42:47 PM PST 24 21121169 ps
T185 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2027328219 Jan 07 01:42:07 PM PST 24 Jan 07 01:42:18 PM PST 24 22031367 ps
T177 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3833922219 Jan 07 01:41:56 PM PST 24 Jan 07 01:42:10 PM PST 24 388857283 ps
T818 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2426702326 Jan 07 01:41:34 PM PST 24 Jan 07 01:47:44 PM PST 24 24795659436 ps
T819 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1321172451 Jan 07 01:43:00 PM PST 24 Jan 07 01:43:21 PM PST 24 73159223 ps
T820 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1763158445 Jan 07 01:41:36 PM PST 24 Jan 07 01:41:50 PM PST 24 37411262 ps
T166 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3765323231 Jan 07 01:41:47 PM PST 24 Jan 07 01:45:09 PM PST 24 5097156709 ps
T821 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2522771301 Jan 07 01:41:38 PM PST 24 Jan 07 01:41:52 PM PST 24 10897737 ps
T822 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3991635674 Jan 07 01:43:08 PM PST 24 Jan 07 01:43:21 PM PST 24 9204983 ps
T823 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1088678293 Jan 07 01:41:38 PM PST 24 Jan 07 01:42:07 PM PST 24 3007791806 ps
T824 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3490263507 Jan 07 01:42:32 PM PST 24 Jan 07 01:42:48 PM PST 24 13919330 ps
T168 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4239328801 Jan 07 01:41:27 PM PST 24 Jan 07 01:50:30 PM PST 24 17341658782 ps
T825 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2922154556 Jan 07 01:42:23 PM PST 24 Jan 07 01:42:45 PM PST 24 45341592 ps
T153 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.341039787 Jan 07 01:42:33 PM PST 24 Jan 07 01:47:28 PM PST 24 5306394681 ps
T826 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1841929248 Jan 07 01:41:28 PM PST 24 Jan 07 01:41:37 PM PST 24 75489641 ps
T827 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3293999385 Jan 07 01:42:06 PM PST 24 Jan 07 01:42:19 PM PST 24 147833682 ps
T828 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.951378662 Jan 07 01:42:10 PM PST 24 Jan 07 01:42:20 PM PST 24 11279655 ps
T829 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3781183110 Jan 07 01:41:36 PM PST 24 Jan 07 01:42:46 PM PST 24 2322771032 ps
T830 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3175580740 Jan 07 01:42:33 PM PST 24 Jan 07 01:42:54 PM PST 24 122244043 ps
T831 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.380313709 Jan 07 01:41:44 PM PST 24 Jan 07 01:42:08 PM PST 24 135888308 ps
T176 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3652138227 Jan 07 01:42:15 PM PST 24 Jan 07 01:43:02 PM PST 24 4441388200 ps
T832 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.151355063 Jan 07 01:42:17 PM PST 24 Jan 07 01:42:43 PM PST 24 488540605 ps
T833 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1915795812 Jan 07 01:43:14 PM PST 24 Jan 07 01:44:10 PM PST 24 1337363199 ps
T834 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1139172742 Jan 07 01:42:39 PM PST 24 Jan 07 01:43:01 PM PST 24 9927298 ps
T154 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1059572327 Jan 07 01:42:27 PM PST 24 Jan 07 01:44:16 PM PST 24 16952850212 ps
T835 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4178781857 Jan 07 01:42:09 PM PST 24 Jan 07 01:42:23 PM PST 24 33944236 ps
T836 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2397559317 Jan 07 01:42:11 PM PST 24 Jan 07 01:42:21 PM PST 24 41056625 ps
T837 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1239321298 Jan 07 01:42:29 PM PST 24 Jan 07 01:42:47 PM PST 24 6464859 ps
T838 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1414135892 Jan 07 01:42:13 PM PST 24 Jan 07 01:42:31 PM PST 24 555422055 ps
T839 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2343870406 Jan 07 01:42:28 PM PST 24 Jan 07 01:42:48 PM PST 24 27461697 ps
T840 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2588110350 Jan 07 01:41:53 PM PST 24 Jan 07 01:42:06 PM PST 24 11938215 ps
T841 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1233902897 Jan 07 01:41:52 PM PST 24 Jan 07 01:46:09 PM PST 24 3305721309 ps
T366 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3784105313 Jan 07 01:42:03 PM PST 24 Jan 07 01:47:09 PM PST 24 2543141082 ps
T842 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2619268643 Jan 07 01:42:12 PM PST 24 Jan 07 01:42:25 PM PST 24 44196855 ps
T843 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3030324323 Jan 07 01:41:52 PM PST 24 Jan 07 01:42:17 PM PST 24 166809441 ps
T844 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2053397614 Jan 07 01:42:13 PM PST 24 Jan 07 01:42:24 PM PST 24 9905383 ps
T159 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1686321845 Jan 07 01:42:11 PM PST 24 Jan 07 02:02:23 PM PST 24 63046203857 ps
T845 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.522393195 Jan 07 01:41:54 PM PST 24 Jan 07 01:42:08 PM PST 24 63670133 ps
T846 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.604705805 Jan 07 01:41:38 PM PST 24 Jan 07 01:42:28 PM PST 24 2198400635 ps
T847 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3432922640 Jan 07 01:41:30 PM PST 24 Jan 07 01:41:41 PM PST 24 203316899 ps
T848 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2111472819 Jan 07 01:42:11 PM PST 24 Jan 07 01:42:26 PM PST 24 67677763 ps
T849 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.817149150 Jan 07 01:41:38 PM PST 24 Jan 07 01:41:54 PM PST 24 51566973 ps
T175 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2224563422 Jan 07 01:42:00 PM PST 24 Jan 07 01:43:30 PM PST 24 4982557763 ps
T167 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2173445474 Jan 07 01:41:57 PM PST 24 Jan 07 01:52:12 PM PST 24 33347154343 ps

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2051248627
Short name T32
Test name
Test status
Simulation time 305260656 ps
CPU time 40.82 seconds
Started Jan 07 01:41:51 PM PST 24
Finished Jan 07 01:42:43 PM PST 24
Peak memory 236460 kb
Host smart-820c2bbd-5322-4e5e-b5e2-333e01f2a037
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2051248627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2051248627
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.912595967
Short name T1
Test name
Test status
Simulation time 13515432694 ps
CPU time 905.09 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 01:56:11 PM PST 24
Peak memory 266256 kb
Host smart-922cda19-16a2-40ea-bb50-4f4bf8e3fb87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912595967 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.912595967
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3800722487
Short name T14
Test name
Test status
Simulation time 13343207 ps
CPU time 1.67 seconds
Started Jan 07 01:43:08 PM PST 24
Finished Jan 07 01:43:22 PM PST 24
Peak memory 236520 kb
Host smart-f7aa2c76-b536-4562-81b3-86bb77ce2c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3800722487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3800722487
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.10373563
Short name T60
Test name
Test status
Simulation time 182901869469 ps
CPU time 2624.29 seconds
Started Jan 07 01:41:35 PM PST 24
Finished Jan 07 02:25:27 PM PST 24
Peak memory 288604 kb
Host smart-70e6085e-01cf-4140-9706-a4cc2d198b01
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10373563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_hand
ler_stress_all.10373563
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1385694566
Short name T46
Test name
Test status
Simulation time 747068986 ps
CPU time 10.95 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:41:18 PM PST 24
Peak memory 270288 kb
Host smart-a86f9953-9906-4167-a27f-c855d37f7d65
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1385694566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1385694566
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.516287407
Short name T34
Test name
Test status
Simulation time 9087395101 ps
CPU time 158.96 seconds
Started Jan 07 01:43:06 PM PST 24
Finished Jan 07 01:45:57 PM PST 24
Peak memory 256876 kb
Host smart-bc0bbadc-b852-491e-9234-ed63a573f192
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=516287407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.516287407
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.4129161013
Short name T18
Test name
Test status
Simulation time 395433799986 ps
CPU time 2576.93 seconds
Started Jan 07 01:40:31 PM PST 24
Finished Jan 07 02:23:54 PM PST 24
Peak memory 285188 kb
Host smart-0bbebd95-7a46-4d39-a146-8fda2cb8e4db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129161013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.4129161013
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.4128219018
Short name T16
Test name
Test status
Simulation time 30613160282 ps
CPU time 1384.13 seconds
Started Jan 07 01:42:09 PM PST 24
Finished Jan 07 02:05:22 PM PST 24
Peak memory 287012 kb
Host smart-3946a6ef-09da-4cd1-b101-4fd8716269de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128219018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.4128219018
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2596461089
Short name T33
Test name
Test status
Simulation time 6375954688 ps
CPU time 202.02 seconds
Started Jan 07 01:41:40 PM PST 24
Finished Jan 07 01:45:16 PM PST 24
Peak memory 265572 kb
Host smart-3ea14788-4afe-458b-ad6c-b07f5d499325
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2596461089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2596461089
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2370579747
Short name T63
Test name
Test status
Simulation time 21329692045 ps
CPU time 1403.76 seconds
Started Jan 07 01:40:25 PM PST 24
Finished Jan 07 02:04:12 PM PST 24
Peak memory 273088 kb
Host smart-1c1cc12c-be7a-4a2e-84ed-0b0aeeb5bf9c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370579747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2370579747
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.47520332
Short name T139
Test name
Test status
Simulation time 12226252322 ps
CPU time 1045.71 seconds
Started Jan 07 01:42:11 PM PST 24
Finished Jan 07 01:59:46 PM PST 24
Peak memory 265472 kb
Host smart-2a8ddfbc-fdc8-429a-b63c-590da1cb0ec7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47520332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.47520332
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1515434183
Short name T41
Test name
Test status
Simulation time 190405454132 ps
CPU time 2928.18 seconds
Started Jan 07 01:42:32 PM PST 24
Finished Jan 07 02:31:35 PM PST 24
Peak memory 289324 kb
Host smart-9b5723f4-ff14-42f2-bb44-59a5bdbce747
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515434183 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1515434183
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.890836865
Short name T147
Test name
Test status
Simulation time 30641116789 ps
CPU time 1043.57 seconds
Started Jan 07 01:41:59 PM PST 24
Finished Jan 07 01:59:32 PM PST 24
Peak memory 273048 kb
Host smart-80e1e0a0-16c3-4de6-998c-0644ec7101bb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890836865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.890836865
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2163669765
Short name T7
Test name
Test status
Simulation time 227685015694 ps
CPU time 2217.39 seconds
Started Jan 07 01:42:15 PM PST 24
Finished Jan 07 02:19:22 PM PST 24
Peak memory 281448 kb
Host smart-4cd4d521-a65b-4d6b-9d5d-2733b593c10d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163669765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2163669765
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3798603509
Short name T135
Test name
Test status
Simulation time 69708724480 ps
CPU time 1137.07 seconds
Started Jan 07 01:41:38 PM PST 24
Finished Jan 07 02:00:48 PM PST 24
Peak memory 265396 kb
Host smart-c71a3ee2-616e-4c14-924d-bc8ca07aa748
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798603509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3798603509
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.4024826374
Short name T9
Test name
Test status
Simulation time 13264848583 ps
CPU time 506.45 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 01:49:33 PM PST 24
Peak memory 247588 kb
Host smart-a6cc5db1-7f7b-41bb-8c5f-a82e7c9e45fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024826374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.4024826374
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3750074440
Short name T52
Test name
Test status
Simulation time 370513336057 ps
CPU time 5490.74 seconds
Started Jan 07 01:40:41 PM PST 24
Finished Jan 07 03:12:39 PM PST 24
Peak memory 321312 kb
Host smart-78fdb745-4dc7-4fcb-b207-18e645d38467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750074440 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3750074440
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3733058020
Short name T6
Test name
Test status
Simulation time 655836771 ps
CPU time 9.93 seconds
Started Jan 07 01:40:24 PM PST 24
Finished Jan 07 01:40:58 PM PST 24
Peak memory 240388 kb
Host smart-cac7b078-c3c0-472d-8c95-1fcfa022d80d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3733058020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3733058020
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2992472298
Short name T141
Test name
Test status
Simulation time 1649446612 ps
CPU time 232.04 seconds
Started Jan 07 01:41:50 PM PST 24
Finished Jan 07 01:45:54 PM PST 24
Peak memory 265344 kb
Host smart-aca36e97-ff33-4568-827d-a5174249b2dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2992472298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2992472298
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3163741469
Short name T259
Test name
Test status
Simulation time 49691941187 ps
CPU time 1778.26 seconds
Started Jan 07 01:40:48 PM PST 24
Finished Jan 07 02:10:52 PM PST 24
Peak memory 272712 kb
Host smart-f8d7df5b-1047-4ad4-94ed-7a9514d18fd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163741469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3163741469
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.54882353
Short name T65
Test name
Test status
Simulation time 350167260994 ps
CPU time 4382.43 seconds
Started Jan 07 01:41:01 PM PST 24
Finished Jan 07 02:54:21 PM PST 24
Peak memory 288992 kb
Host smart-0fb788c6-c47b-41c2-8e0a-b9676d01ab85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54882353 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.54882353
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2120000516
Short name T331
Test name
Test status
Simulation time 12110819843 ps
CPU time 474.57 seconds
Started Jan 07 01:41:27 PM PST 24
Finished Jan 07 01:49:27 PM PST 24
Peak memory 247624 kb
Host smart-0b944263-a680-4794-b3ee-aab5bb5adb7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120000516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2120000516
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.288727980
Short name T337
Test name
Test status
Simulation time 612460562470 ps
CPU time 2994.98 seconds
Started Jan 07 01:42:28 PM PST 24
Finished Jan 07 02:32:41 PM PST 24
Peak memory 288120 kb
Host smart-0608d1cc-4e3c-4cdf-92bc-7c878f428b82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288727980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.288727980
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1139014699
Short name T314
Test name
Test status
Simulation time 30237350546 ps
CPU time 639.09 seconds
Started Jan 07 01:41:24 PM PST 24
Finished Jan 07 01:52:09 PM PST 24
Peak memory 247296 kb
Host smart-bac3fb4f-c89e-4378-9331-72f12cb58817
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139014699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1139014699
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3034421351
Short name T69
Test name
Test status
Simulation time 132770561728 ps
CPU time 2144.04 seconds
Started Jan 07 01:41:27 PM PST 24
Finished Jan 07 02:17:17 PM PST 24
Peak memory 288756 kb
Host smart-5a7823d9-eb8e-45a9-93b7-08265c979dfe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034421351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3034421351
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3611868281
Short name T142
Test name
Test status
Simulation time 59938559726 ps
CPU time 1076.89 seconds
Started Jan 07 01:42:37 PM PST 24
Finished Jan 07 02:00:55 PM PST 24
Peak memory 271896 kb
Host smart-926e78ae-13af-4aab-8547-5794eeee8ff6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611868281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3611868281
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3874245945
Short name T30
Test name
Test status
Simulation time 96909427 ps
CPU time 2.93 seconds
Started Jan 07 01:41:29 PM PST 24
Finished Jan 07 01:41:37 PM PST 24
Peak memory 235432 kb
Host smart-eb25c1e8-ca3e-430b-a0c0-75f75bf482d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3874245945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3874245945
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2028973961
Short name T246
Test name
Test status
Simulation time 107289884127 ps
CPU time 6375.92 seconds
Started Jan 07 01:41:25 PM PST 24
Finished Jan 07 03:27:47 PM PST 24
Peak memory 338056 kb
Host smart-af6394a8-2f99-4af6-bf4c-1f5488f87d6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028973961 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2028973961
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1771092693
Short name T346
Test name
Test status
Simulation time 42399350447 ps
CPU time 2162.53 seconds
Started Jan 07 01:40:31 PM PST 24
Finished Jan 07 02:17:00 PM PST 24
Peak memory 286392 kb
Host smart-3b969e35-85b7-49d0-8f2f-ea5104613791
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771092693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1771092693
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4239328801
Short name T168
Test name
Test status
Simulation time 17341658782 ps
CPU time 537.49 seconds
Started Jan 07 01:41:27 PM PST 24
Finished Jan 07 01:50:30 PM PST 24
Peak memory 265552 kb
Host smart-9bb24ed7-0f5d-4f10-8160-eaa5e3995768
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239328801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.4239328801
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3052768287
Short name T328
Test name
Test status
Simulation time 18686897547 ps
CPU time 380.75 seconds
Started Jan 07 01:41:33 PM PST 24
Finished Jan 07 01:48:00 PM PST 24
Peak memory 248500 kb
Host smart-cca6122f-a3c3-48a5-a8b5-d156fbd396f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052768287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3052768287
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2209200446
Short name T234
Test name
Test status
Simulation time 8763514 ps
CPU time 1.51 seconds
Started Jan 07 01:42:03 PM PST 24
Finished Jan 07 01:42:13 PM PST 24
Peak memory 235700 kb
Host smart-77eb258f-08bd-48de-b82b-1ca8c52b9fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2209200446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2209200446
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1645911668
Short name T254
Test name
Test status
Simulation time 555534192045 ps
CPU time 2660.65 seconds
Started Jan 07 01:41:51 PM PST 24
Finished Jan 07 02:26:23 PM PST 24
Peak memory 289272 kb
Host smart-4909ca51-b220-4617-bf29-fc8c198d27d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645911668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1645911668
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1641468524
Short name T66
Test name
Test status
Simulation time 216560693931 ps
CPU time 1793.77 seconds
Started Jan 07 01:40:26 PM PST 24
Finished Jan 07 02:10:43 PM PST 24
Peak memory 288952 kb
Host smart-99f79b31-7858-43ef-8d9e-6d49acb447df
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641468524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1641468524
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2173445474
Short name T167
Test name
Test status
Simulation time 33347154343 ps
CPU time 604.75 seconds
Started Jan 07 01:41:57 PM PST 24
Finished Jan 07 01:52:12 PM PST 24
Peak memory 265524 kb
Host smart-26d82905-5eee-4547-847e-cf32a7396639
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173445474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2173445474
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.4232618019
Short name T318
Test name
Test status
Simulation time 58367529429 ps
CPU time 3173.8 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 02:33:54 PM PST 24
Peak memory 289060 kb
Host smart-8fddd116-b0a5-42df-b14b-eb5da07fce75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232618019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.4232618019
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.341039787
Short name T153
Test name
Test status
Simulation time 5306394681 ps
CPU time 281.16 seconds
Started Jan 07 01:42:33 PM PST 24
Finished Jan 07 01:47:28 PM PST 24
Peak memory 270264 kb
Host smart-8e3b02cf-1efb-4a60-9327-7cc0768e4f47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=341039787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.341039787
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.4287446757
Short name T351
Test name
Test status
Simulation time 52605469680 ps
CPU time 2768.64 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 02:28:17 PM PST 24
Peak memory 289276 kb
Host smart-5f9844cb-8f41-4f16-846b-3c07492ad381
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287446757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.4287446757
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.4171110612
Short name T39
Test name
Test status
Simulation time 594186481 ps
CPU time 32.37 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:41:40 PM PST 24
Peak memory 254140 kb
Host smart-1cb1dd36-d9cc-42da-818b-38be75b4819c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41711
10612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.4171110612
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.258056640
Short name T279
Test name
Test status
Simulation time 13061838075 ps
CPU time 508.31 seconds
Started Jan 07 01:40:56 PM PST 24
Finished Jan 07 01:49:44 PM PST 24
Peak memory 247312 kb
Host smart-a0303f74-336e-4ea3-ae2c-15ea1ab50ac8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258056640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.258056640
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2260212565
Short name T43
Test name
Test status
Simulation time 732801553796 ps
CPU time 2300.42 seconds
Started Jan 07 01:40:24 PM PST 24
Finished Jan 07 02:19:08 PM PST 24
Peak memory 289560 kb
Host smart-9c6ed781-d47d-4876-a26d-b33db735f3f5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260212565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2260212565
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3061266680
Short name T151
Test name
Test status
Simulation time 54160868391 ps
CPU time 1049.59 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 01:59:39 PM PST 24
Peak memory 265388 kb
Host smart-b86325af-7cb2-40ad-8275-067bc838016e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061266680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3061266680
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.459204423
Short name T133
Test name
Test status
Simulation time 6733008181 ps
CPU time 180.45 seconds
Started Jan 07 01:42:32 PM PST 24
Finished Jan 07 01:45:47 PM PST 24
Peak memory 265320 kb
Host smart-24818de0-b244-494c-9f65-a8f39a23300b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=459204423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.459204423
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2983499464
Short name T171
Test name
Test status
Simulation time 27849392 ps
CPU time 1.48 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 01:42:23 PM PST 24
Peak memory 235596 kb
Host smart-d2db19c4-bd98-4fa1-a58f-c29d442f3fc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2983499464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2983499464
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.175604694
Short name T357
Test name
Test status
Simulation time 88917651958 ps
CPU time 1617.98 seconds
Started Jan 07 01:40:29 PM PST 24
Finished Jan 07 02:07:52 PM PST 24
Peak memory 272816 kb
Host smart-14ed3813-bb38-41c6-89e8-f212a7ba475f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175604694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.175604694
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2486265832
Short name T96
Test name
Test status
Simulation time 25899551625 ps
CPU time 337.57 seconds
Started Jan 07 01:42:04 PM PST 24
Finished Jan 07 01:47:51 PM PST 24
Peak memory 247360 kb
Host smart-389f1885-624a-4837-9792-4a224e663f93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486265832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2486265832
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2256241365
Short name T297
Test name
Test status
Simulation time 230754047698 ps
CPU time 6172.72 seconds
Started Jan 07 01:40:35 PM PST 24
Finished Jan 07 03:23:54 PM PST 24
Peak memory 314224 kb
Host smart-aadf09ed-e8dc-4261-a4f9-248c51a63145
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256241365 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2256241365
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3411433007
Short name T113
Test name
Test status
Simulation time 83430446356 ps
CPU time 4382.82 seconds
Started Jan 07 01:40:27 PM PST 24
Finished Jan 07 02:53:53 PM PST 24
Peak memory 315700 kb
Host smart-c5887e76-357a-49dc-b855-1412f046c06c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411433007 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3411433007
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.265624712
Short name T71
Test name
Test status
Simulation time 30856529943 ps
CPU time 1848.83 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 02:12:25 PM PST 24
Peak memory 289304 kb
Host smart-b1c65212-0805-4ee9-b2ec-548febb9652b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265624712 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.265624712
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1843189666
Short name T40
Test name
Test status
Simulation time 109650273725 ps
CPU time 3003.38 seconds
Started Jan 07 01:40:23 PM PST 24
Finished Jan 07 02:30:51 PM PST 24
Peak memory 288724 kb
Host smart-a2b41fdb-64c5-4c57-bbbd-cafd7bb674ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843189666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1843189666
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3408031653
Short name T209
Test name
Test status
Simulation time 49876481 ps
CPU time 2.38 seconds
Started Jan 07 01:40:20 PM PST 24
Finished Jan 07 01:40:47 PM PST 24
Peak memory 248792 kb
Host smart-411f4424-e699-49ce-ac59-b449c4cc352f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3408031653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3408031653
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1944958928
Short name T202
Test name
Test status
Simulation time 48476322 ps
CPU time 2.55 seconds
Started Jan 07 01:40:41 PM PST 24
Finished Jan 07 01:41:11 PM PST 24
Peak memory 248840 kb
Host smart-f2b581b3-aa4a-4f61-9450-f0a8dbd78617
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1944958928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1944958928
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3948199625
Short name T208
Test name
Test status
Simulation time 19548767 ps
CPU time 2.97 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:41:10 PM PST 24
Peak memory 248924 kb
Host smart-08ae6753-661e-41f4-932c-264666f7e8fa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3948199625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3948199625
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1678083602
Short name T210
Test name
Test status
Simulation time 80563611 ps
CPU time 3.4 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 01:41:06 PM PST 24
Peak memory 248848 kb
Host smart-e2eeeab7-8113-4b4b-b1f7-a6cad9e0a752
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1678083602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1678083602
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2221806946
Short name T157
Test name
Test status
Simulation time 17330748704 ps
CPU time 979.31 seconds
Started Jan 07 01:41:41 PM PST 24
Finished Jan 07 01:58:15 PM PST 24
Peak memory 265400 kb
Host smart-47e10a30-3481-4f93-8ae9-0da94fa37515
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221806946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2221806946
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.805855359
Short name T104
Test name
Test status
Simulation time 157934061063 ps
CPU time 874.37 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 01:55:35 PM PST 24
Peak memory 272856 kb
Host smart-b36e3343-282f-4ddd-8285-5b9374afaa34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805855359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.805855359
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.4289162661
Short name T290
Test name
Test status
Simulation time 597224133 ps
CPU time 36.85 seconds
Started Jan 07 01:40:46 PM PST 24
Finished Jan 07 01:41:48 PM PST 24
Peak memory 248536 kb
Host smart-45a2c794-31e1-4648-9d20-b3274678dde0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42891
62661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.4289162661
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.995539225
Short name T73
Test name
Test status
Simulation time 35122753744 ps
CPU time 2479.01 seconds
Started Jan 07 01:41:28 PM PST 24
Finished Jan 07 02:22:53 PM PST 24
Peak memory 289700 kb
Host smart-579a1d36-b52f-4746-859c-8a1e25dfeb2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995539225 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.995539225
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2436075594
Short name T289
Test name
Test status
Simulation time 152198158 ps
CPU time 17.41 seconds
Started Jan 07 01:41:09 PM PST 24
Finished Jan 07 01:41:39 PM PST 24
Peak memory 255068 kb
Host smart-8c586643-0e7c-44cf-b477-06d60d30c449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24360
75594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2436075594
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.4071734227
Short name T248
Test name
Test status
Simulation time 95582299909 ps
CPU time 5465.3 seconds
Started Jan 07 01:41:26 PM PST 24
Finished Jan 07 03:12:37 PM PST 24
Peak memory 321168 kb
Host smart-5dd2ea11-85a1-48cf-af52-945f35673a72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071734227 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.4071734227
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1309472593
Short name T13
Test name
Test status
Simulation time 829364012 ps
CPU time 20.91 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 01:41:24 PM PST 24
Peak memory 277104 kb
Host smart-812ffb89-359a-4ddf-ad58-f9a67535c113
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1309472593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1309472593
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1574024522
Short name T174
Test name
Test status
Simulation time 979682716 ps
CPU time 69.88 seconds
Started Jan 07 01:42:01 PM PST 24
Finished Jan 07 01:43:20 PM PST 24
Peak memory 239368 kb
Host smart-900d5b66-c710-4a2c-9ee2-0d00483bc111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1574024522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1574024522
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3979848196
Short name T268
Test name
Test status
Simulation time 35405716562 ps
CPU time 773.24 seconds
Started Jan 07 01:40:32 PM PST 24
Finished Jan 07 01:53:52 PM PST 24
Peak memory 272600 kb
Host smart-03d01b4e-97e1-4ca4-bc17-48c9c94540aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979848196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3979848196
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1643194103
Short name T568
Test name
Test status
Simulation time 6572028739 ps
CPU time 264.75 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 01:45:30 PM PST 24
Peak memory 247256 kb
Host smart-4314ce6e-07fa-407a-976c-613d634f3d76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643194103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1643194103
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.994154884
Short name T332
Test name
Test status
Simulation time 11694133076 ps
CPU time 129.08 seconds
Started Jan 07 01:40:44 PM PST 24
Finished Jan 07 01:43:20 PM PST 24
Peak memory 247604 kb
Host smart-0347263b-3578-454a-84c4-4bbae27dbd41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994154884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.994154884
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.233203807
Short name T253
Test name
Test status
Simulation time 82879965022 ps
CPU time 2329.12 seconds
Started Jan 07 01:40:31 PM PST 24
Finished Jan 07 02:19:46 PM PST 24
Peak memory 284236 kb
Host smart-820182d8-6ad3-4bed-8d9b-43f5660e10d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233203807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.233203807
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.271489717
Short name T702
Test name
Test status
Simulation time 100493131347 ps
CPU time 2731.42 seconds
Started Jan 07 01:40:46 PM PST 24
Finished Jan 07 02:26:44 PM PST 24
Peak memory 288912 kb
Host smart-28d8bbd4-a39e-4a31-bdcb-9b2e51762953
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271489717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.271489717
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1874416386
Short name T310
Test name
Test status
Simulation time 9674958982 ps
CPU time 87.01 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 01:42:31 PM PST 24
Peak memory 246308 kb
Host smart-9496d412-661f-40f7-b204-e2d8b40e2d4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874416386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1874416386
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.572775198
Short name T293
Test name
Test status
Simulation time 66842007768 ps
CPU time 2922.71 seconds
Started Jan 07 01:40:47 PM PST 24
Finished Jan 07 02:29:56 PM PST 24
Peak memory 300640 kb
Host smart-4d3122a8-91a2-4f2c-a4ca-f8202039aa26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572775198 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.572775198
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.598568496
Short name T262
Test name
Test status
Simulation time 8124555227 ps
CPU time 240.45 seconds
Started Jan 07 01:40:53 PM PST 24
Finished Jan 07 01:45:15 PM PST 24
Peak memory 256792 kb
Host smart-d7bd40b8-6c91-4057-bba3-dac1b17cd81c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598568496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.598568496
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1490800268
Short name T286
Test name
Test status
Simulation time 248833221122 ps
CPU time 3582.53 seconds
Started Jan 07 01:41:11 PM PST 24
Finished Jan 07 02:41:06 PM PST 24
Peak memory 298128 kb
Host smart-b6f7c4b6-7cac-4e27-a838-8a18cc2513c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490800268 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1490800268
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3520517972
Short name T302
Test name
Test status
Simulation time 52682714645 ps
CPU time 2908.58 seconds
Started Jan 07 01:42:05 PM PST 24
Finished Jan 07 02:30:43 PM PST 24
Peak memory 288936 kb
Host smart-473149ef-a6cc-41ac-a5f7-12318aeefa5c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520517972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3520517972
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2221911271
Short name T74
Test name
Test status
Simulation time 304746561069 ps
CPU time 7166.26 seconds
Started Jan 07 01:42:07 PM PST 24
Finished Jan 07 03:41:42 PM PST 24
Peak memory 347108 kb
Host smart-ceb5b7b9-b014-45e0-9e60-39ea9cd79c14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221911271 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2221911271
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3631114272
Short name T255
Test name
Test status
Simulation time 1004329997826 ps
CPU time 3201.45 seconds
Started Jan 07 01:40:56 PM PST 24
Finished Jan 07 02:34:37 PM PST 24
Peak memory 288964 kb
Host smart-458dac75-b215-4b24-89e8-6956e318fd25
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631114272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3631114272
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1724381859
Short name T256
Test name
Test status
Simulation time 677576995 ps
CPU time 40.6 seconds
Started Jan 07 01:41:40 PM PST 24
Finished Jan 07 01:42:35 PM PST 24
Peak memory 255312 kb
Host smart-7db07560-e23f-416c-b1cb-1082985737c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17243
81859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1724381859
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3349888704
Short name T222
Test name
Test status
Simulation time 12305481744 ps
CPU time 1042.3 seconds
Started Jan 07 01:41:31 PM PST 24
Finished Jan 07 01:58:59 PM PST 24
Peak memory 271296 kb
Host smart-512c325f-54aa-48a3-9ea7-c97eca93f771
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349888704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3349888704
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1802048522
Short name T62
Test name
Test status
Simulation time 167788313805 ps
CPU time 2545.52 seconds
Started Jan 07 01:42:08 PM PST 24
Finished Jan 07 02:24:43 PM PST 24
Peak memory 289832 kb
Host smart-6a14c1a0-8892-4a30-a19e-1bb9bf1ebb1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802048522 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1802048522
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3490250838
Short name T137
Test name
Test status
Simulation time 43318110588 ps
CPU time 275.71 seconds
Started Jan 07 01:41:52 PM PST 24
Finished Jan 07 01:46:39 PM PST 24
Peak memory 266772 kb
Host smart-99fe6446-7603-4a03-a408-039b87375c25
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3490250838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3490250838
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1059572327
Short name T154
Test name
Test status
Simulation time 16952850212 ps
CPU time 89.67 seconds
Started Jan 07 01:42:27 PM PST 24
Finished Jan 07 01:44:16 PM PST 24
Peak memory 265344 kb
Host smart-f1619d49-4a3e-465c-95c5-7e1898a87adc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1059572327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1059572327
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1792485791
Short name T156
Test name
Test status
Simulation time 305913877 ps
CPU time 39.04 seconds
Started Jan 07 01:41:59 PM PST 24
Finished Jan 07 01:42:47 PM PST 24
Peak memory 240328 kb
Host smart-fe9783db-cb9d-4c9c-8ffa-c3c8f6968d56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1792485791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1792485791
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.4184155027
Short name T132
Test name
Test status
Simulation time 6111912601 ps
CPU time 192.17 seconds
Started Jan 07 01:41:53 PM PST 24
Finished Jan 07 01:45:16 PM PST 24
Peak memory 265404 kb
Host smart-e343fe32-c758-4578-b4a4-0fb884745f63
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4184155027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.4184155027
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.283936912
Short name T58
Test name
Test status
Simulation time 48315909832 ps
CPU time 183.33 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 01:44:08 PM PST 24
Peak memory 249924 kb
Host smart-4620cafa-cb26-442d-a56b-5ee7cd5d9e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28393
6912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.283936912
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2224563422
Short name T175
Test name
Test status
Simulation time 4982557763 ps
CPU time 81.52 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 01:43:30 PM PST 24
Peak memory 239312 kb
Host smart-b17d634b-d121-401c-99e9-010182d4d324
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2224563422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2224563422
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3372959441
Short name T28
Test name
Test status
Simulation time 103781525 ps
CPU time 2.53 seconds
Started Jan 07 01:42:02 PM PST 24
Finished Jan 07 01:42:14 PM PST 24
Peak memory 235524 kb
Host smart-b60967de-fcdc-44f2-a0b3-6599d4bc59d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3372959441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3372959441
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3553971588
Short name T187
Test name
Test status
Simulation time 157217500 ps
CPU time 25.63 seconds
Started Jan 07 01:41:24 PM PST 24
Finished Jan 07 01:41:55 PM PST 24
Peak memory 248568 kb
Host smart-0716067e-4ced-4e27-bbcb-1fab195e7f2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3553971588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3553971588
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.650373219
Short name T150
Test name
Test status
Simulation time 1176807951 ps
CPU time 115.89 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 01:44:05 PM PST 24
Peak memory 265224 kb
Host smart-fe5f2216-235b-4929-8cec-4b9cedea89bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=650373219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.650373219
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3833922219
Short name T177
Test name
Test status
Simulation time 388857283 ps
CPU time 3.43 seconds
Started Jan 07 01:41:56 PM PST 24
Finished Jan 07 01:42:10 PM PST 24
Peak memory 236788 kb
Host smart-1cf7f772-16a3-4a7b-828b-d9d19e474703
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3833922219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3833922219
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2027328219
Short name T185
Test name
Test status
Simulation time 22031367 ps
CPU time 2.34 seconds
Started Jan 07 01:42:07 PM PST 24
Finished Jan 07 01:42:18 PM PST 24
Peak memory 237524 kb
Host smart-fa848932-afc4-4a91-a6bf-ff0ce30714c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2027328219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2027328219
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3652138227
Short name T176
Test name
Test status
Simulation time 4441388200 ps
CPU time 35.73 seconds
Started Jan 07 01:42:15 PM PST 24
Finished Jan 07 01:43:02 PM PST 24
Peak memory 240396 kb
Host smart-7f100125-6e6b-431d-a6e9-ea4ecf696313
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3652138227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3652138227
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2805458475
Short name T164
Test name
Test status
Simulation time 802795321 ps
CPU time 96.06 seconds
Started Jan 07 01:42:43 PM PST 24
Finished Jan 07 01:44:39 PM PST 24
Peak memory 265332 kb
Host smart-1c7f4082-32f6-47f8-b778-aa94d32c4db8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2805458475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2805458475
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1612970034
Short name T181
Test name
Test status
Simulation time 83760505 ps
CPU time 2.12 seconds
Started Jan 07 01:43:07 PM PST 24
Finished Jan 07 01:43:21 PM PST 24
Peak memory 236288 kb
Host smart-7e0f2083-0d73-4309-9404-473b7ee7470d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1612970034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1612970034
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.4205740478
Short name T182
Test name
Test status
Simulation time 647104080 ps
CPU time 38.21 seconds
Started Jan 07 01:42:35 PM PST 24
Finished Jan 07 01:43:32 PM PST 24
Peak memory 240408 kb
Host smart-25fe403d-8ba1-4348-a80a-63759d5417b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4205740478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.4205740478
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3146156116
Short name T178
Test name
Test status
Simulation time 116983304 ps
CPU time 4.55 seconds
Started Jan 07 01:41:46 PM PST 24
Finished Jan 07 01:42:04 PM PST 24
Peak memory 236880 kb
Host smart-abc056a2-460e-44e4-a5af-0608ce28f962
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3146156116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3146156116
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.715362477
Short name T180
Test name
Test status
Simulation time 580511973 ps
CPU time 36.89 seconds
Started Jan 07 01:41:44 PM PST 24
Finished Jan 07 01:42:35 PM PST 24
Peak memory 244984 kb
Host smart-6cd6d73b-e51f-42b2-9ea4-273e73a6a3dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=715362477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.715362477
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1874918056
Short name T186
Test name
Test status
Simulation time 34975006 ps
CPU time 2.11 seconds
Started Jan 07 01:41:28 PM PST 24
Finished Jan 07 01:41:36 PM PST 24
Peak memory 236304 kb
Host smart-c4f584cb-968d-463b-89c6-fa5eec1d605c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1874918056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1874918056
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1584824129
Short name T184
Test name
Test status
Simulation time 602194721 ps
CPU time 21.69 seconds
Started Jan 07 01:41:29 PM PST 24
Finished Jan 07 01:41:56 PM PST 24
Peak memory 240428 kb
Host smart-852425a1-eca7-4c88-813e-78e0ce928c24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1584824129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1584824129
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2202038819
Short name T163
Test name
Test status
Simulation time 162096753 ps
CPU time 20.41 seconds
Started Jan 07 01:41:58 PM PST 24
Finished Jan 07 01:42:28 PM PST 24
Peak memory 248628 kb
Host smart-c76ad569-d8dd-4c63-a537-ad7b2e81e9b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2202038819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2202038819
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4177758698
Short name T183
Test name
Test status
Simulation time 180349901 ps
CPU time 22.23 seconds
Started Jan 07 01:42:26 PM PST 24
Finished Jan 07 01:43:08 PM PST 24
Peak memory 248568 kb
Host smart-5cd0e9a2-c62c-40e3-b4ba-0147802b7b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4177758698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.4177758698
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2668537906
Short name T37
Test name
Test status
Simulation time 220590937 ps
CPU time 10.19 seconds
Started Jan 07 01:40:31 PM PST 24
Finished Jan 07 01:41:07 PM PST 24
Peak memory 254068 kb
Host smart-216b4f10-0ce0-4dd8-9724-1cc8a64b399b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26685
37906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2668537906
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.230921388
Short name T38
Test name
Test status
Simulation time 152257056792 ps
CPU time 4238.74 seconds
Started Jan 07 01:41:59 PM PST 24
Finished Jan 07 02:52:47 PM PST 24
Peak memory 305224 kb
Host smart-ccf00cf7-7081-4cda-8ca6-5a650b0d5ef2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230921388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.230921388
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1233902897
Short name T841
Test name
Test status
Simulation time 3305721309 ps
CPU time 245.04 seconds
Started Jan 07 01:41:52 PM PST 24
Finished Jan 07 01:46:09 PM PST 24
Peak memory 240440 kb
Host smart-481ad3fa-9920-419d-96ca-f7e2c455f287
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1233902897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1233902897
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3681970406
Short name T753
Test name
Test status
Simulation time 3404946800 ps
CPU time 109.71 seconds
Started Jan 07 01:41:35 PM PST 24
Finished Jan 07 01:43:33 PM PST 24
Peak memory 236548 kb
Host smart-e2559daa-7995-42cb-aece-cb57c891e21d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3681970406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3681970406
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1482417158
Short name T742
Test name
Test status
Simulation time 37157654 ps
CPU time 4.11 seconds
Started Jan 07 01:41:53 PM PST 24
Finished Jan 07 01:42:08 PM PST 24
Peak memory 240420 kb
Host smart-ce14026a-dce9-4519-a745-d0614b0bc642
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1482417158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1482417158
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1325282666
Short name T127
Test name
Test status
Simulation time 37114241 ps
CPU time 4.34 seconds
Started Jan 07 01:41:29 PM PST 24
Finished Jan 07 01:41:39 PM PST 24
Peak memory 237456 kb
Host smart-8d47481b-4151-4510-bad1-bb5e25128de4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325282666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1325282666
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.177812078
Short name T815
Test name
Test status
Simulation time 510536906 ps
CPU time 9.81 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 01:42:19 PM PST 24
Peak memory 236480 kb
Host smart-d209941a-dff6-4451-a62f-8b4627913b81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=177812078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.177812078
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3065011619
Short name T739
Test name
Test status
Simulation time 13157219 ps
CPU time 1.28 seconds
Started Jan 07 01:41:32 PM PST 24
Finished Jan 07 01:41:40 PM PST 24
Peak memory 234584 kb
Host smart-e185826d-7876-4390-8f1a-52e1fd0506d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3065011619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3065011619
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1744876511
Short name T810
Test name
Test status
Simulation time 680901179 ps
CPU time 18.32 seconds
Started Jan 07 01:41:54 PM PST 24
Finished Jan 07 01:42:23 PM PST 24
Peak memory 243804 kb
Host smart-cd633891-4904-49a0-80b2-662f3c718626
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1744876511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1744876511
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.4282169966
Short name T143
Test name
Test status
Simulation time 7416061317 ps
CPU time 134.44 seconds
Started Jan 07 01:41:38 PM PST 24
Finished Jan 07 01:44:05 PM PST 24
Peak memory 257180 kb
Host smart-22a09104-d78e-4d59-a909-1ae343d4fd81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4282169966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.4282169966
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1964857114
Short name T165
Test name
Test status
Simulation time 25348478512 ps
CPU time 476.8 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 01:49:42 PM PST 24
Peak memory 267980 kb
Host smart-f8220969-1174-4bc0-9c54-df56d79c8342
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964857114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1964857114
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.922227651
Short name T758
Test name
Test status
Simulation time 241690564 ps
CPU time 8.74 seconds
Started Jan 07 01:41:39 PM PST 24
Finished Jan 07 01:42:01 PM PST 24
Peak memory 248672 kb
Host smart-8b757c27-a0d6-4219-bea6-2e894d43a015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=922227651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.922227651
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.168433660
Short name T796
Test name
Test status
Simulation time 1085429796 ps
CPU time 59.82 seconds
Started Jan 07 01:41:37 PM PST 24
Finished Jan 07 01:42:47 PM PST 24
Peak memory 240308 kb
Host smart-7653724e-36c7-4b72-96f4-b990df5e3a5a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=168433660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.168433660
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1721538983
Short name T790
Test name
Test status
Simulation time 13585464081 ps
CPU time 193.38 seconds
Started Jan 07 01:41:37 PM PST 24
Finished Jan 07 01:44:59 PM PST 24
Peak memory 235576 kb
Host smart-5322d699-2bcb-4ccd-8c96-06dc248ec7db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1721538983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1721538983
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3793888135
Short name T189
Test name
Test status
Simulation time 188158674 ps
CPU time 4.65 seconds
Started Jan 07 01:41:28 PM PST 24
Finished Jan 07 01:41:38 PM PST 24
Peak memory 240424 kb
Host smart-e3f099aa-9739-413f-9c22-6a4198b5ec07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3793888135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3793888135
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1850818295
Short name T812
Test name
Test status
Simulation time 145445341 ps
CPU time 6.21 seconds
Started Jan 07 01:41:31 PM PST 24
Finished Jan 07 01:41:43 PM PST 24
Peak memory 256128 kb
Host smart-2f04ca24-8bb4-41cf-bca2-ff072f1066c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850818295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1850818295
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3354467364
Short name T786
Test name
Test status
Simulation time 38154406 ps
CPU time 5.35 seconds
Started Jan 07 01:41:31 PM PST 24
Finished Jan 07 01:41:43 PM PST 24
Peak memory 236432 kb
Host smart-7f003b73-57dc-4375-bb19-43049938e93f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3354467364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3354467364
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2522771301
Short name T821
Test name
Test status
Simulation time 10897737 ps
CPU time 1.34 seconds
Started Jan 07 01:41:38 PM PST 24
Finished Jan 07 01:41:52 PM PST 24
Peak memory 236332 kb
Host smart-311d4ecc-9fe0-4c9c-aa81-c32984da7522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2522771301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2522771301
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3176052992
Short name T809
Test name
Test status
Simulation time 1124747305 ps
CPU time 21.71 seconds
Started Jan 07 01:41:37 PM PST 24
Finished Jan 07 01:42:08 PM PST 24
Peak memory 240420 kb
Host smart-3d26989d-f0d1-441f-8c8a-7aba6af1dfef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3176052992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3176052992
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2977710944
Short name T779
Test name
Test status
Simulation time 82575995 ps
CPU time 10.08 seconds
Started Jan 07 01:41:55 PM PST 24
Finished Jan 07 01:42:15 PM PST 24
Peak memory 247632 kb
Host smart-be7e94e7-4900-4c5e-8c11-5dc732222c7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2977710944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2977710944
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.522393195
Short name T845
Test name
Test status
Simulation time 63670133 ps
CPU time 3.99 seconds
Started Jan 07 01:41:54 PM PST 24
Finished Jan 07 01:42:08 PM PST 24
Peak memory 238276 kb
Host smart-01746cd0-3843-4046-81b9-eb3b3b660c85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522393195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.522393195
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.4251860534
Short name T751
Test name
Test status
Simulation time 33337008 ps
CPU time 5.61 seconds
Started Jan 07 01:42:19 PM PST 24
Finished Jan 07 01:42:40 PM PST 24
Peak memory 236440 kb
Host smart-598bc6ac-bf49-41ea-a78c-98dc834c0e93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4251860534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.4251860534
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.718845165
Short name T765
Test name
Test status
Simulation time 8864933 ps
CPU time 1.61 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 01:42:24 PM PST 24
Peak memory 236496 kb
Host smart-d8d495f3-cee6-4857-a8b0-88913f79e22d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=718845165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.718845165
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.922938638
Short name T770
Test name
Test status
Simulation time 450690532 ps
CPU time 12.49 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 01:42:22 PM PST 24
Peak memory 240396 kb
Host smart-7fe8e84e-6527-4d81-9578-fde97b47a559
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=922938638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.922938638
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1088678293
Short name T823
Test name
Test status
Simulation time 3007791806 ps
CPU time 17.97 seconds
Started Jan 07 01:41:38 PM PST 24
Finished Jan 07 01:42:07 PM PST 24
Peak memory 248612 kb
Host smart-3bbb0922-4453-4947-8527-9953adee9439
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1088678293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1088678293
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2111472819
Short name T848
Test name
Test status
Simulation time 67677763 ps
CPU time 6.53 seconds
Started Jan 07 01:42:11 PM PST 24
Finished Jan 07 01:42:26 PM PST 24
Peak memory 253096 kb
Host smart-3d52e77b-a7eb-477c-a3f5-798b2e94f2f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111472819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2111472819
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1798411603
Short name T788
Test name
Test status
Simulation time 275973697 ps
CPU time 6.2 seconds
Started Jan 07 01:41:57 PM PST 24
Finished Jan 07 01:42:13 PM PST 24
Peak memory 236480 kb
Host smart-209a2e10-7e10-421f-8a71-91d040309cac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1798411603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1798411603
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2397559317
Short name T836
Test name
Test status
Simulation time 41056625 ps
CPU time 1.38 seconds
Started Jan 07 01:42:11 PM PST 24
Finished Jan 07 01:42:21 PM PST 24
Peak memory 235600 kb
Host smart-7ec0b80e-4c4b-4dd8-9568-483cb55fff0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2397559317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2397559317
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1529389229
Short name T791
Test name
Test status
Simulation time 513357501 ps
CPU time 20.91 seconds
Started Jan 07 01:41:55 PM PST 24
Finished Jan 07 01:42:26 PM PST 24
Peak memory 244680 kb
Host smart-77fae0f6-846d-4f53-ade7-e80d59197e35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1529389229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1529389229
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.783891263
Short name T149
Test name
Test status
Simulation time 4754641137 ps
CPU time 642.23 seconds
Started Jan 07 01:42:03 PM PST 24
Finished Jan 07 01:52:54 PM PST 24
Peak memory 265540 kb
Host smart-014ad7f3-5fb6-499f-8816-a2f705e901d4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783891263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.783891263
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3216584058
Short name T741
Test name
Test status
Simulation time 63178349 ps
CPU time 6.77 seconds
Started Jan 07 01:41:40 PM PST 24
Finished Jan 07 01:42:02 PM PST 24
Peak memory 248712 kb
Host smart-fd41a306-e2d9-486c-bbe4-dbc28b6cc64d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3216584058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3216584058
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2621350875
Short name T799
Test name
Test status
Simulation time 382595084 ps
CPU time 7.2 seconds
Started Jan 07 01:42:16 PM PST 24
Finished Jan 07 01:42:38 PM PST 24
Peak memory 248672 kb
Host smart-b5ef3d30-eddf-426a-9cd0-fed8de13dce0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621350875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2621350875
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1855845673
Short name T774
Test name
Test status
Simulation time 99747177 ps
CPU time 7.13 seconds
Started Jan 07 01:42:05 PM PST 24
Finished Jan 07 01:42:21 PM PST 24
Peak memory 240376 kb
Host smart-6c80defa-f67c-49ef-b87f-9a0a8df8be63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1855845673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1855845673
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3030324323
Short name T843
Test name
Test status
Simulation time 166809441 ps
CPU time 13.56 seconds
Started Jan 07 01:41:52 PM PST 24
Finished Jan 07 01:42:17 PM PST 24
Peak memory 240440 kb
Host smart-c758f68f-7573-4b59-b892-51464c65b20a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3030324323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3030324323
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3166939991
Short name T158
Test name
Test status
Simulation time 4064740125 ps
CPU time 332.57 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 01:47:42 PM PST 24
Peak memory 267748 kb
Host smart-f0909295-19c0-4796-afcc-28d6004c85c8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166939991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3166939991
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.181620128
Short name T811
Test name
Test status
Simulation time 255102689 ps
CPU time 9.01 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 01:42:18 PM PST 24
Peak memory 248220 kb
Host smart-412402a7-71e4-4685-aa5f-a7eded8afbc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=181620128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.181620128
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.773053503
Short name T169
Test name
Test status
Simulation time 154352487 ps
CPU time 6.5 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 01:42:15 PM PST 24
Peak memory 256268 kb
Host smart-44beadf8-f923-4c00-91e0-890eecd305aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773053503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.773053503
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.718548986
Short name T804
Test name
Test status
Simulation time 184041005 ps
CPU time 4.9 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 01:42:27 PM PST 24
Peak memory 236464 kb
Host smart-1b3699f6-0b00-4997-b0ef-f94e6d05b1d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=718548986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.718548986
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3939033625
Short name T367
Test name
Test status
Simulation time 10092651 ps
CPU time 1.32 seconds
Started Jan 07 01:41:49 PM PST 24
Finished Jan 07 01:42:03 PM PST 24
Peak memory 234560 kb
Host smart-a0fe3f49-9be6-45a1-8999-bb2fde761163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3939033625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3939033625
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.905219458
Short name T768
Test name
Test status
Simulation time 652292649 ps
CPU time 25.16 seconds
Started Jan 07 01:42:10 PM PST 24
Finished Jan 07 01:42:44 PM PST 24
Peak memory 244696 kb
Host smart-98dfd7cc-9221-4f1a-bf83-891f70548c26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=905219458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.905219458
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2922154556
Short name T825
Test name
Test status
Simulation time 45341592 ps
CPU time 5.92 seconds
Started Jan 07 01:42:23 PM PST 24
Finished Jan 07 01:42:45 PM PST 24
Peak memory 248660 kb
Host smart-c9d07c84-4326-47b2-b89e-d5a707a95c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2922154556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2922154556
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1509709045
Short name T740
Test name
Test status
Simulation time 120186792 ps
CPU time 3.84 seconds
Started Jan 07 01:42:08 PM PST 24
Finished Jan 07 01:42:21 PM PST 24
Peak memory 240500 kb
Host smart-1102dddc-fe3e-4dc1-ad31-f07a5e90ca19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509709045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1509709045
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3620905732
Short name T162
Test name
Test status
Simulation time 54665103 ps
CPU time 4.83 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 01:42:27 PM PST 24
Peak memory 236468 kb
Host smart-cf5d0602-5350-400d-a79b-9617b9c0082e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3620905732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3620905732
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3449947383
Short name T738
Test name
Test status
Simulation time 10665048 ps
CPU time 1.38 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 01:42:10 PM PST 24
Peak memory 236504 kb
Host smart-d21ddff8-0bbf-4f77-8d3f-b32ab8a26453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3449947383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3449947383
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.4160622598
Short name T777
Test name
Test status
Simulation time 904278286 ps
CPU time 12.66 seconds
Started Jan 07 01:41:57 PM PST 24
Finished Jan 07 01:42:19 PM PST 24
Peak memory 244680 kb
Host smart-cc6ad78c-38a7-4fff-bfbb-d7d4cf839a23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4160622598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.4160622598
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1460284763
Short name T148
Test name
Test status
Simulation time 1501950880 ps
CPU time 101.41 seconds
Started Jan 07 01:41:59 PM PST 24
Finished Jan 07 01:43:49 PM PST 24
Peak memory 265240 kb
Host smart-522c94ee-6c00-48fa-8e5c-85583a737b63
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1460284763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1460284763
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1412347672
Short name T136
Test name
Test status
Simulation time 9716875759 ps
CPU time 638.38 seconds
Started Jan 07 01:41:56 PM PST 24
Finished Jan 07 01:52:45 PM PST 24
Peak memory 265276 kb
Host smart-729b27ec-7d02-4b1e-b279-44ad45701388
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412347672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1412347672
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1952686364
Short name T762
Test name
Test status
Simulation time 477358486 ps
CPU time 9.52 seconds
Started Jan 07 01:41:55 PM PST 24
Finished Jan 07 01:42:14 PM PST 24
Peak memory 248708 kb
Host smart-f7b97d5b-ef81-412b-9368-90ff06c07b04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1952686364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1952686364
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3293999385
Short name T827
Test name
Test status
Simulation time 147833682 ps
CPU time 4.31 seconds
Started Jan 07 01:42:06 PM PST 24
Finished Jan 07 01:42:19 PM PST 24
Peak memory 238584 kb
Host smart-c9f10acb-32ce-4dd6-b62f-d0052fb1a720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293999385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3293999385
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3175580740
Short name T830
Test name
Test status
Simulation time 122244043 ps
CPU time 4.97 seconds
Started Jan 07 01:42:33 PM PST 24
Finished Jan 07 01:42:54 PM PST 24
Peak memory 236480 kb
Host smart-95883b1c-b183-4f0b-aadd-63b8a8b02609
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3175580740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3175580740
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3490263507
Short name T824
Test name
Test status
Simulation time 13919330 ps
CPU time 1.35 seconds
Started Jan 07 01:42:32 PM PST 24
Finished Jan 07 01:42:48 PM PST 24
Peak memory 235676 kb
Host smart-09757cfe-9cdc-4091-870b-11d97fef90c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3490263507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3490263507
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.262829167
Short name T781
Test name
Test status
Simulation time 1031797344 ps
CPU time 40.02 seconds
Started Jan 07 01:42:01 PM PST 24
Finished Jan 07 01:42:50 PM PST 24
Peak memory 248644 kb
Host smart-8f49914b-7eca-4b9d-a0f9-c7c5ed544c22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=262829167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.262829167
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.757781090
Short name T161
Test name
Test status
Simulation time 1614326156 ps
CPU time 107.47 seconds
Started Jan 07 01:42:01 PM PST 24
Finished Jan 07 01:43:58 PM PST 24
Peak memory 265344 kb
Host smart-fa6a1de4-d14e-4ce2-a5f6-5d53f085b79d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=757781090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.757781090
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3784105313
Short name T366
Test name
Test status
Simulation time 2543141082 ps
CPU time 297.65 seconds
Started Jan 07 01:42:03 PM PST 24
Finished Jan 07 01:47:09 PM PST 24
Peak memory 265420 kb
Host smart-42df80d4-60a5-40c3-b619-2006892284dd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784105313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3784105313
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2025483423
Short name T749
Test name
Test status
Simulation time 649384911 ps
CPU time 10.14 seconds
Started Jan 07 01:42:02 PM PST 24
Finished Jan 07 01:42:22 PM PST 24
Peak memory 247832 kb
Host smart-ec0be300-b8d8-4a49-a05f-37898943734c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2025483423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2025483423
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3810649933
Short name T763
Test name
Test status
Simulation time 114031675 ps
CPU time 6.28 seconds
Started Jan 07 01:42:37 PM PST 24
Finished Jan 07 01:43:03 PM PST 24
Peak memory 251932 kb
Host smart-95189677-97a0-43a8-a2d4-82a06b9d28cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810649933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3810649933
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.151355063
Short name T832
Test name
Test status
Simulation time 488540605 ps
CPU time 10.34 seconds
Started Jan 07 01:42:17 PM PST 24
Finished Jan 07 01:42:43 PM PST 24
Peak memory 236436 kb
Host smart-64b2be12-3ec3-4664-a5fd-50020852f7d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=151355063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.151355063
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4058362802
Short name T750
Test name
Test status
Simulation time 6104470 ps
CPU time 1.39 seconds
Started Jan 07 01:42:15 PM PST 24
Finished Jan 07 01:42:25 PM PST 24
Peak memory 236504 kb
Host smart-1b309d38-d108-4073-bd17-caf1b6519f2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4058362802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.4058362802
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1120815954
Short name T805
Test name
Test status
Simulation time 4252603271 ps
CPU time 34.96 seconds
Started Jan 07 01:42:37 PM PST 24
Finished Jan 07 01:43:33 PM PST 24
Peak memory 244644 kb
Host smart-2d5c074c-17b8-4a64-afe6-5b08d4adf08e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1120815954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1120815954
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2688667456
Short name T152
Test name
Test status
Simulation time 49271949260 ps
CPU time 464.89 seconds
Started Jan 07 01:42:16 PM PST 24
Finished Jan 07 01:50:15 PM PST 24
Peak memory 267628 kb
Host smart-4cfd2699-902e-48b0-b4a1-95dbb7867c81
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688667456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2688667456
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.74967219
Short name T170
Test name
Test status
Simulation time 537231476 ps
CPU time 10.39 seconds
Started Jan 07 01:42:25 PM PST 24
Finished Jan 07 01:42:54 PM PST 24
Peak memory 252888 kb
Host smart-aec014c9-372a-4a24-a551-15686facbd6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=74967219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.74967219
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2812974238
Short name T772
Test name
Test status
Simulation time 27349500 ps
CPU time 5.87 seconds
Started Jan 07 01:43:04 PM PST 24
Finished Jan 07 01:43:23 PM PST 24
Peak memory 251768 kb
Host smart-d721ce3a-d663-4955-99b8-5c4830db92f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812974238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2812974238
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.297573162
Short name T31
Test name
Test status
Simulation time 97344835 ps
CPU time 7.6 seconds
Started Jan 07 01:42:41 PM PST 24
Finished Jan 07 01:43:09 PM PST 24
Peak memory 235516 kb
Host smart-3cdfb564-3044-4a9d-af87-cd2d3e8403b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=297573162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.297573162
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1279187693
Short name T172
Test name
Test status
Simulation time 8150851 ps
CPU time 1.45 seconds
Started Jan 07 01:42:35 PM PST 24
Finished Jan 07 01:42:56 PM PST 24
Peak memory 236480 kb
Host smart-c358bdfd-e993-4d69-be3d-3f0bb472e840
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1279187693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1279187693
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1915795812
Short name T833
Test name
Test status
Simulation time 1337363199 ps
CPU time 42.44 seconds
Started Jan 07 01:43:14 PM PST 24
Finished Jan 07 01:44:10 PM PST 24
Peak memory 244564 kb
Host smart-bf720e3b-b36e-4b31-b742-02a541d1c845
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1915795812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1915795812
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2421777248
Short name T130
Test name
Test status
Simulation time 18191557579 ps
CPU time 610.96 seconds
Started Jan 07 01:42:37 PM PST 24
Finished Jan 07 01:53:08 PM PST 24
Peak memory 269392 kb
Host smart-9ce62c83-b424-40c9-9428-31dd8b48b0a0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421777248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2421777248
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3197946459
Short name T173
Test name
Test status
Simulation time 99932054 ps
CPU time 7.98 seconds
Started Jan 07 01:42:32 PM PST 24
Finished Jan 07 01:42:55 PM PST 24
Peak memory 248656 kb
Host smart-a3bfc624-3640-4afe-a7dc-b4e186172411
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3197946459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3197946459
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1865767905
Short name T782
Test name
Test status
Simulation time 45651787 ps
CPU time 3.84 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 01:42:25 PM PST 24
Peak memory 237460 kb
Host smart-44fc4f8d-14ab-4c06-9185-9375769ec232
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865767905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1865767905
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1908095610
Short name T188
Test name
Test status
Simulation time 94154341 ps
CPU time 4.02 seconds
Started Jan 07 01:42:05 PM PST 24
Finished Jan 07 01:42:19 PM PST 24
Peak memory 235596 kb
Host smart-7b8cb30c-996b-4392-a9be-ae56ca93b5a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1908095610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1908095610
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3031179372
Short name T764
Test name
Test status
Simulation time 8121068 ps
CPU time 1.52 seconds
Started Jan 07 01:42:11 PM PST 24
Finished Jan 07 01:42:21 PM PST 24
Peak memory 236452 kb
Host smart-e8c20583-fc02-4453-accf-10801e8c3934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3031179372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3031179372
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1462287729
Short name T735
Test name
Test status
Simulation time 1869057210 ps
CPU time 19.34 seconds
Started Jan 07 01:42:36 PM PST 24
Finished Jan 07 01:43:15 PM PST 24
Peak memory 243560 kb
Host smart-f31a9325-1bfd-4a61-8510-165ee23f3b78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1462287729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1462287729
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.682033625
Short name T146
Test name
Test status
Simulation time 18288366689 ps
CPU time 287.32 seconds
Started Jan 07 01:42:41 PM PST 24
Finished Jan 07 01:47:48 PM PST 24
Peak memory 265396 kb
Host smart-11e132a5-c11b-4df9-aca0-4e146ff7ec10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=682033625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.682033625
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4169462998
Short name T144
Test name
Test status
Simulation time 14900064491 ps
CPU time 502.34 seconds
Started Jan 07 01:43:18 PM PST 24
Finished Jan 07 01:51:55 PM PST 24
Peak memory 265368 kb
Host smart-e6c7ae82-8217-4ab1-9d17-eaba34602d04
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169462998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.4169462998
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3728768643
Short name T761
Test name
Test status
Simulation time 121786152 ps
CPU time 7.06 seconds
Started Jan 07 01:42:30 PM PST 24
Finished Jan 07 01:42:53 PM PST 24
Peak memory 248644 kb
Host smart-1afd484a-06eb-4d5e-8def-0b4c88828c17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3728768643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3728768643
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2707531820
Short name T800
Test name
Test status
Simulation time 422119251 ps
CPU time 18.08 seconds
Started Jan 07 01:42:27 PM PST 24
Finished Jan 07 01:43:04 PM PST 24
Peak memory 240300 kb
Host smart-74df7d75-9865-4b88-bd58-9a814ef564c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2707531820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2707531820
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3749473381
Short name T766
Test name
Test status
Simulation time 23712656 ps
CPU time 4.03 seconds
Started Jan 07 01:42:31 PM PST 24
Finished Jan 07 01:42:51 PM PST 24
Peak memory 255760 kb
Host smart-d489a3df-9b14-4292-b869-c376d8598e88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749473381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3749473381
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1414135892
Short name T838
Test name
Test status
Simulation time 555422055 ps
CPU time 9.72 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 01:42:31 PM PST 24
Peak memory 236468 kb
Host smart-70507025-5928-4e7f-b067-ac79144d0bf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1414135892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1414135892
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.4167943440
Short name T789
Test name
Test status
Simulation time 11678963 ps
CPU time 1.36 seconds
Started Jan 07 01:42:14 PM PST 24
Finished Jan 07 01:42:24 PM PST 24
Peak memory 236460 kb
Host smart-e05a64bc-e8b6-4821-a79c-10acb9f73e9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4167943440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.4167943440
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.385772161
Short name T26
Test name
Test status
Simulation time 89308637 ps
CPU time 13.31 seconds
Started Jan 07 01:42:18 PM PST 24
Finished Jan 07 01:42:47 PM PST 24
Peak memory 244556 kb
Host smart-5b2b2376-6b7b-49ef-b06b-b0bac457fafd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=385772161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.385772161
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2635679465
Short name T138
Test name
Test status
Simulation time 1591121238 ps
CPU time 94.35 seconds
Started Jan 07 01:42:36 PM PST 24
Finished Jan 07 01:44:31 PM PST 24
Peak memory 256224 kb
Host smart-50cda86f-5119-462d-8cc1-2e566348b9dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2635679465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2635679465
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.871121827
Short name T757
Test name
Test status
Simulation time 54549644 ps
CPU time 8.04 seconds
Started Jan 07 01:42:12 PM PST 24
Finished Jan 07 01:42:29 PM PST 24
Peak memory 248692 kb
Host smart-796a6cec-a120-4467-bc8e-371803689a06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=871121827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.871121827
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3781183110
Short name T829
Test name
Test status
Simulation time 2322771032 ps
CPU time 62.25 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 01:42:46 PM PST 24
Peak memory 236648 kb
Host smart-51a031e3-8d93-48ed-a9f7-d681171e4e4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3781183110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3781183110
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2426702326
Short name T818
Test name
Test status
Simulation time 24795659436 ps
CPU time 362.3 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:47:44 PM PST 24
Peak memory 236512 kb
Host smart-fdaf28bb-f6e6-4c1f-b0aa-7062e5fb5733
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2426702326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2426702326
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1763158445
Short name T820
Test name
Test status
Simulation time 37411262 ps
CPU time 6.13 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 01:41:50 PM PST 24
Peak memory 240360 kb
Host smart-d7370082-0877-467d-bd95-1926dcefbdaf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1763158445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1763158445
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1841929248
Short name T826
Test name
Test status
Simulation time 75489641 ps
CPU time 3.46 seconds
Started Jan 07 01:41:28 PM PST 24
Finished Jan 07 01:41:37 PM PST 24
Peak memory 240464 kb
Host smart-d34038f1-7c17-4e5f-b148-181b365fbeaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841929248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1841929248
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1727153782
Short name T155
Test name
Test status
Simulation time 35822988 ps
CPU time 5.29 seconds
Started Jan 07 01:41:55 PM PST 24
Finished Jan 07 01:42:10 PM PST 24
Peak memory 236472 kb
Host smart-fae7cecd-a9d9-4bb5-b3aa-b3d97717df4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1727153782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1727153782
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2654516296
Short name T241
Test name
Test status
Simulation time 8138382 ps
CPU time 1.48 seconds
Started Jan 07 01:41:51 PM PST 24
Finished Jan 07 01:42:04 PM PST 24
Peak memory 236408 kb
Host smart-92a6cbcb-f5ac-40c9-a16b-53eaf699f967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2654516296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2654516296
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.604705805
Short name T846
Test name
Test status
Simulation time 2198400635 ps
CPU time 38.32 seconds
Started Jan 07 01:41:38 PM PST 24
Finished Jan 07 01:42:28 PM PST 24
Peak memory 244784 kb
Host smart-ad517fad-17a8-4757-8c13-bedf57da4652
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=604705805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.604705805
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2269487869
Short name T129
Test name
Test status
Simulation time 15776584838 ps
CPU time 130.44 seconds
Started Jan 07 01:41:31 PM PST 24
Finished Jan 07 01:43:47 PM PST 24
Peak memory 256664 kb
Host smart-83cf18de-2db7-493b-b448-684000368fa7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2269487869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2269487869
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2067753002
Short name T131
Test name
Test status
Simulation time 8992917250 ps
CPU time 330.54 seconds
Started Jan 07 01:41:54 PM PST 24
Finished Jan 07 01:47:35 PM PST 24
Peak memory 265420 kb
Host smart-a6c66f2c-a813-42d9-b515-efd63d326096
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067753002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2067753002
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2972156137
Short name T808
Test name
Test status
Simulation time 296355614 ps
CPU time 21.56 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 01:42:06 PM PST 24
Peak memory 247896 kb
Host smart-846221df-9e23-46d9-b164-aecad3eaf817
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2972156137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2972156137
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2343870406
Short name T839
Test name
Test status
Simulation time 27461697 ps
CPU time 1.99 seconds
Started Jan 07 01:42:28 PM PST 24
Finished Jan 07 01:42:48 PM PST 24
Peak memory 235640 kb
Host smart-fed8f157-7d71-43b5-91bd-54cb0893592e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2343870406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2343870406
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2882557103
Short name T748
Test name
Test status
Simulation time 7739316 ps
CPU time 1.31 seconds
Started Jan 07 01:42:16 PM PST 24
Finished Jan 07 01:42:31 PM PST 24
Peak memory 236428 kb
Host smart-e1f73395-da68-4b3e-a7a8-96e413425767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2882557103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2882557103
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3822498531
Short name T787
Test name
Test status
Simulation time 10855642 ps
CPU time 1.45 seconds
Started Jan 07 01:43:03 PM PST 24
Finished Jan 07 01:43:18 PM PST 24
Peak memory 234592 kb
Host smart-bf8d7a8d-fac7-4db6-b876-a4872c57fe3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3822498531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3822498531
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1216072763
Short name T192
Test name
Test status
Simulation time 6593141 ps
CPU time 1.45 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 01:42:24 PM PST 24
Peak memory 236532 kb
Host smart-46973d2e-ea47-40c8-955e-89df7f90e476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1216072763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1216072763
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3068702112
Short name T746
Test name
Test status
Simulation time 8186160 ps
CPU time 1.53 seconds
Started Jan 07 01:42:09 PM PST 24
Finished Jan 07 01:42:19 PM PST 24
Peak memory 234648 kb
Host smart-bcaab79f-93b6-4e56-81da-dae879ea4723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3068702112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3068702112
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1801121066
Short name T794
Test name
Test status
Simulation time 21542997 ps
CPU time 1.28 seconds
Started Jan 07 01:42:14 PM PST 24
Finished Jan 07 01:42:24 PM PST 24
Peak memory 235292 kb
Host smart-61e71d2b-d712-4f12-8b27-5f7b2d094560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1801121066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1801121066
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.568799970
Short name T760
Test name
Test status
Simulation time 11079126 ps
CPU time 1.33 seconds
Started Jan 07 01:42:39 PM PST 24
Finished Jan 07 01:43:02 PM PST 24
Peak memory 235540 kb
Host smart-d9972469-900d-4796-8d2f-36e49d596633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=568799970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.568799970
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2053397614
Short name T844
Test name
Test status
Simulation time 9905383 ps
CPU time 1.6 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 01:42:24 PM PST 24
Peak memory 236500 kb
Host smart-ba03e044-beb8-4c47-991b-9e6f3b09858c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2053397614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2053397614
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.4260029218
Short name T240
Test name
Test status
Simulation time 8149548 ps
CPU time 1.44 seconds
Started Jan 07 01:42:10 PM PST 24
Finished Jan 07 01:42:20 PM PST 24
Peak memory 236476 kb
Host smart-01bdf8f0-b2e0-4610-a457-aa8cb65d0009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4260029218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.4260029218
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3394867960
Short name T365
Test name
Test status
Simulation time 40354368 ps
CPU time 1.4 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 01:42:23 PM PST 24
Peak memory 236524 kb
Host smart-f6bc6e9c-6da7-475e-9715-003e4e2a01bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3394867960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3394867960
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.89460542
Short name T784
Test name
Test status
Simulation time 26536634923 ps
CPU time 117.24 seconds
Started Jan 07 01:41:29 PM PST 24
Finished Jan 07 01:43:31 PM PST 24
Peak memory 236576 kb
Host smart-e0e121e2-4233-4bd0-b186-a3064121a1fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=89460542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.89460542
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.240911497
Short name T801
Test name
Test status
Simulation time 22489273569 ps
CPU time 254.12 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 01:45:59 PM PST 24
Peak memory 236496 kb
Host smart-41c639dc-8f57-4cdc-b124-6b6521d2776b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=240911497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.240911497
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.916303273
Short name T752
Test name
Test status
Simulation time 53230693 ps
CPU time 5.13 seconds
Started Jan 07 01:41:32 PM PST 24
Finished Jan 07 01:41:44 PM PST 24
Peak memory 240296 kb
Host smart-4b18c0b4-889c-4de5-aa38-6ac900a6e4ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=916303273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.916303273
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2116329782
Short name T816
Test name
Test status
Simulation time 112450354 ps
CPU time 7.37 seconds
Started Jan 07 01:41:51 PM PST 24
Finished Jan 07 01:42:10 PM PST 24
Peak memory 251728 kb
Host smart-4181358b-d9e6-4ba3-93d7-75b622cb1c69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116329782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2116329782
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1573204033
Short name T755
Test name
Test status
Simulation time 113974830 ps
CPU time 4.94 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 01:41:40 PM PST 24
Peak memory 236492 kb
Host smart-32699574-e415-4d5a-9ccd-6c9d551c9f05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1573204033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1573204033
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2588110350
Short name T840
Test name
Test status
Simulation time 11938215 ps
CPU time 1.39 seconds
Started Jan 07 01:41:53 PM PST 24
Finished Jan 07 01:42:06 PM PST 24
Peak memory 235736 kb
Host smart-2ee360db-4273-41db-a8ce-2c449ac7404b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2588110350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2588110350
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.4036105582
Short name T190
Test name
Test status
Simulation time 186808509 ps
CPU time 23.11 seconds
Started Jan 07 01:41:35 PM PST 24
Finished Jan 07 01:42:07 PM PST 24
Peak memory 244620 kb
Host smart-192ce5c3-9faa-4e5f-8f01-38f89c1cb357
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4036105582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.4036105582
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.896460299
Short name T140
Test name
Test status
Simulation time 3567164801 ps
CPU time 92.76 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 01:43:42 PM PST 24
Peak memory 263580 kb
Host smart-4b422046-6a35-43bd-b161-a70d242f874a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=896460299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.896460299
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3432922640
Short name T847
Test name
Test status
Simulation time 203316899 ps
CPU time 5.31 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 01:41:41 PM PST 24
Peak memory 248556 kb
Host smart-129f965e-0f84-497a-baae-98ae96d3967a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3432922640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3432922640
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.951378662
Short name T828
Test name
Test status
Simulation time 11279655 ps
CPU time 1.37 seconds
Started Jan 07 01:42:10 PM PST 24
Finished Jan 07 01:42:20 PM PST 24
Peak memory 234468 kb
Host smart-88cf07f5-73ff-4a89-bad1-eebc24d6c476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=951378662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.951378662
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4081561073
Short name T737
Test name
Test status
Simulation time 26568286 ps
CPU time 2.19 seconds
Started Jan 07 01:43:05 PM PST 24
Finished Jan 07 01:43:20 PM PST 24
Peak memory 236368 kb
Host smart-097bf7e4-f46d-4bb4-afc0-6df9ad8d63d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4081561073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.4081561073
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2757635040
Short name T363
Test name
Test status
Simulation time 8855562 ps
CPU time 1.48 seconds
Started Jan 07 01:42:17 PM PST 24
Finished Jan 07 01:42:33 PM PST 24
Peak memory 236504 kb
Host smart-065d1aa6-9d26-4474-bccc-58059cec37f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2757635040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2757635040
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.413317048
Short name T767
Test name
Test status
Simulation time 8054162 ps
CPU time 1.47 seconds
Started Jan 07 01:42:16 PM PST 24
Finished Jan 07 01:42:28 PM PST 24
Peak memory 236408 kb
Host smart-9db00702-98ab-4ea5-86a6-8570bab126c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=413317048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.413317048
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2901448944
Short name T803
Test name
Test status
Simulation time 7311475 ps
CPU time 1.39 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 01:42:24 PM PST 24
Peak memory 234536 kb
Host smart-42ef1516-1ea0-413e-85c7-bce36606c356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2901448944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2901448944
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.886410757
Short name T369
Test name
Test status
Simulation time 66974054 ps
CPU time 1.33 seconds
Started Jan 07 01:42:10 PM PST 24
Finished Jan 07 01:42:20 PM PST 24
Peak memory 236268 kb
Host smart-4179c0d6-daf7-40a7-9ee3-67869f0ff4c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=886410757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.886410757
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.230384247
Short name T364
Test name
Test status
Simulation time 14013445 ps
CPU time 1.32 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 01:42:24 PM PST 24
Peak memory 235620 kb
Host smart-01d1ad19-d536-487c-859d-807c3571ee7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=230384247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.230384247
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1139172742
Short name T834
Test name
Test status
Simulation time 9927298 ps
CPU time 1.6 seconds
Started Jan 07 01:42:39 PM PST 24
Finished Jan 07 01:43:01 PM PST 24
Peak memory 236496 kb
Host smart-44811dd3-2ee2-424a-a9df-70fa8431dc54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1139172742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1139172742
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1785181348
Short name T817
Test name
Test status
Simulation time 21121169 ps
CPU time 1.37 seconds
Started Jan 07 01:42:29 PM PST 24
Finished Jan 07 01:42:47 PM PST 24
Peak memory 236520 kb
Host smart-3fa5eb92-112a-4587-9519-27863a64091b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1785181348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1785181348
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2445339926
Short name T773
Test name
Test status
Simulation time 4541939134 ps
CPU time 147.42 seconds
Started Jan 07 01:41:46 PM PST 24
Finished Jan 07 01:44:27 PM PST 24
Peak memory 239424 kb
Host smart-98e3e34e-387f-4120-9e75-6769e4f5515c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2445339926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2445339926
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2451660591
Short name T813
Test name
Test status
Simulation time 7426079958 ps
CPU time 105.02 seconds
Started Jan 07 01:41:53 PM PST 24
Finished Jan 07 01:43:49 PM PST 24
Peak memory 236456 kb
Host smart-003d82ac-7f03-4702-a1f4-743361410e14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2451660591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2451660591
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.817149150
Short name T849
Test name
Test status
Simulation time 51566973 ps
CPU time 5.11 seconds
Started Jan 07 01:41:38 PM PST 24
Finished Jan 07 01:41:54 PM PST 24
Peak memory 240412 kb
Host smart-161b2920-e428-4adb-a007-442b0273ecdb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=817149150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.817149150
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.4290492639
Short name T783
Test name
Test status
Simulation time 21237849 ps
CPU time 4.39 seconds
Started Jan 07 01:42:07 PM PST 24
Finished Jan 07 01:42:21 PM PST 24
Peak memory 240688 kb
Host smart-87980799-de06-4ead-8f16-191c581d5dc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290492639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.4290492639
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.380313709
Short name T831
Test name
Test status
Simulation time 135888308 ps
CPU time 9.65 seconds
Started Jan 07 01:41:44 PM PST 24
Finished Jan 07 01:42:08 PM PST 24
Peak memory 236436 kb
Host smart-dbd35163-8bda-4ee6-8c9e-6470ba4e8d3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=380313709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.380313709
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2186571889
Short name T802
Test name
Test status
Simulation time 9407685 ps
CPU time 1.51 seconds
Started Jan 07 01:41:29 PM PST 24
Finished Jan 07 01:41:36 PM PST 24
Peak memory 236520 kb
Host smart-ca7bf176-1db1-4a88-8b43-28ee531a6d1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2186571889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2186571889
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2318684383
Short name T798
Test name
Test status
Simulation time 260520085 ps
CPU time 12.05 seconds
Started Jan 07 01:41:44 PM PST 24
Finished Jan 07 01:42:10 PM PST 24
Peak memory 244648 kb
Host smart-fee1baef-eb73-4967-b6b8-e3663080240d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2318684383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2318684383
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.182289480
Short name T128
Test name
Test status
Simulation time 6220439167 ps
CPU time 597.13 seconds
Started Jan 07 01:41:35 PM PST 24
Finished Jan 07 01:51:41 PM PST 24
Peak memory 265284 kb
Host smart-6f6979fd-acc5-4d8b-982d-07c35b3cf842
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182289480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.182289480
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1253108991
Short name T126
Test name
Test status
Simulation time 986787622 ps
CPU time 7.41 seconds
Started Jan 07 01:41:39 PM PST 24
Finished Jan 07 01:41:58 PM PST 24
Peak memory 252792 kb
Host smart-f109ac16-a513-459e-b28f-f52f46a49c69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1253108991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1253108991
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3428728973
Short name T793
Test name
Test status
Simulation time 16262729 ps
CPU time 1.21 seconds
Started Jan 07 01:42:35 PM PST 24
Finished Jan 07 01:42:55 PM PST 24
Peak memory 236484 kb
Host smart-89c4bf9b-a3c0-4785-844e-b65da411a35d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3428728973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3428728973
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.598926472
Short name T736
Test name
Test status
Simulation time 26060710 ps
CPU time 1.24 seconds
Started Jan 07 01:42:44 PM PST 24
Finished Jan 07 01:43:05 PM PST 24
Peak memory 235636 kb
Host smart-e30d87c1-f5bd-44db-a6ec-647b7bec82fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=598926472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.598926472
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1838894689
Short name T747
Test name
Test status
Simulation time 9451430 ps
CPU time 1.47 seconds
Started Jan 07 01:42:29 PM PST 24
Finished Jan 07 01:42:47 PM PST 24
Peak memory 236512 kb
Host smart-e76bc723-4532-4cac-8fea-41db35077f1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1838894689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1838894689
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3991635674
Short name T822
Test name
Test status
Simulation time 9204983 ps
CPU time 1.33 seconds
Started Jan 07 01:43:08 PM PST 24
Finished Jan 07 01:43:21 PM PST 24
Peak memory 234620 kb
Host smart-8ad38394-3551-4cae-825f-60b40eeacf1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3991635674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3991635674
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.157834189
Short name T368
Test name
Test status
Simulation time 9001911 ps
CPU time 1.5 seconds
Started Jan 07 01:43:06 PM PST 24
Finished Jan 07 01:43:20 PM PST 24
Peak memory 234628 kb
Host smart-9515ae48-7f0a-4bef-b3ec-34ba98a47b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=157834189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.157834189
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2044052991
Short name T362
Test name
Test status
Simulation time 12435846 ps
CPU time 1.61 seconds
Started Jan 07 01:43:07 PM PST 24
Finished Jan 07 01:43:21 PM PST 24
Peak memory 235684 kb
Host smart-f9d21f46-a002-4159-b20d-f2002a24253f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2044052991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2044052991
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3565938318
Short name T771
Test name
Test status
Simulation time 7945150 ps
CPU time 1.33 seconds
Started Jan 07 01:43:00 PM PST 24
Finished Jan 07 01:43:17 PM PST 24
Peak memory 236488 kb
Host smart-05328810-2aea-4da7-af8f-c33f539025f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3565938318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3565938318
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3035815042
Short name T792
Test name
Test status
Simulation time 17476923 ps
CPU time 1.31 seconds
Started Jan 07 01:43:07 PM PST 24
Finished Jan 07 01:43:20 PM PST 24
Peak memory 234640 kb
Host smart-a23ebaed-33e3-48a3-af30-e69f88804671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3035815042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3035815042
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2202686996
Short name T806
Test name
Test status
Simulation time 7143134 ps
CPU time 1.41 seconds
Started Jan 07 01:42:43 PM PST 24
Finished Jan 07 01:43:04 PM PST 24
Peak memory 236400 kb
Host smart-5af3e4f7-dd3c-42a4-8817-09360db149d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2202686996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2202686996
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.650630133
Short name T27
Test name
Test status
Simulation time 30910194 ps
CPU time 5.87 seconds
Started Jan 07 01:42:05 PM PST 24
Finished Jan 07 01:42:20 PM PST 24
Peak memory 252364 kb
Host smart-6a68097a-fb77-405c-8136-956003bf834a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650630133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.650630133
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3972768565
Short name T795
Test name
Test status
Simulation time 130869638 ps
CPU time 5.82 seconds
Started Jan 07 01:41:53 PM PST 24
Finished Jan 07 01:42:10 PM PST 24
Peak memory 238472 kb
Host smart-164caab7-3342-4c81-ac52-b7329c8d4116
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3972768565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3972768565
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3095507347
Short name T814
Test name
Test status
Simulation time 18833755 ps
CPU time 1.46 seconds
Started Jan 07 01:41:53 PM PST 24
Finished Jan 07 01:42:05 PM PST 24
Peak memory 236504 kb
Host smart-c2b3799b-ca91-467b-922e-004ffaacb2f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3095507347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3095507347
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4250507227
Short name T797
Test name
Test status
Simulation time 253060251 ps
CPU time 17.94 seconds
Started Jan 07 01:41:41 PM PST 24
Finished Jan 07 01:42:13 PM PST 24
Peak memory 240296 kb
Host smart-7eb8d7f8-fba1-41e8-87e6-c25e30e68be7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4250507227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.4250507227
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3335012645
Short name T145
Test name
Test status
Simulation time 3869613831 ps
CPU time 140.73 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:44:12 PM PST 24
Peak memory 256972 kb
Host smart-995e7f6a-7fa8-4e73-9268-dc370fd0c676
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3335012645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3335012645
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.568640766
Short name T160
Test name
Test status
Simulation time 14796208113 ps
CPU time 547.17 seconds
Started Jan 07 01:41:40 PM PST 24
Finished Jan 07 01:51:01 PM PST 24
Peak memory 265560 kb
Host smart-fc19cffa-1c1e-41d2-b163-28fcfc5f1b35
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568640766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.568640766
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3123361121
Short name T778
Test name
Test status
Simulation time 379768087 ps
CPU time 6.33 seconds
Started Jan 07 01:42:01 PM PST 24
Finished Jan 07 01:42:16 PM PST 24
Peak memory 248700 kb
Host smart-7a328b7f-1eea-4ded-b931-d03c10029cbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3123361121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3123361121
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2619268643
Short name T842
Test name
Test status
Simulation time 44196855 ps
CPU time 4.31 seconds
Started Jan 07 01:42:12 PM PST 24
Finished Jan 07 01:42:25 PM PST 24
Peak memory 238708 kb
Host smart-45031d85-5cc2-481b-ad71-c6d8d6a7798a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619268643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2619268643
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1128160542
Short name T754
Test name
Test status
Simulation time 493374731 ps
CPU time 9.6 seconds
Started Jan 07 01:42:27 PM PST 24
Finished Jan 07 01:42:55 PM PST 24
Peak memory 240408 kb
Host smart-84f38a46-9c38-43c2-9a22-508dd50c9966
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1128160542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1128160542
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3249540155
Short name T361
Test name
Test status
Simulation time 12646092 ps
CPU time 1.49 seconds
Started Jan 07 01:42:29 PM PST 24
Finished Jan 07 01:42:47 PM PST 24
Peak memory 236476 kb
Host smart-3d5424e9-f921-4ead-8662-9ec0b977376e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3249540155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3249540155
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.252080212
Short name T744
Test name
Test status
Simulation time 5586233540 ps
CPU time 39.03 seconds
Started Jan 07 01:42:10 PM PST 24
Finished Jan 07 01:42:59 PM PST 24
Peak memory 243872 kb
Host smart-4dd08cfe-b29a-4125-9b94-63adeab41fd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=252080212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.252080212
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3765323231
Short name T166
Test name
Test status
Simulation time 5097156709 ps
CPU time 189.17 seconds
Started Jan 07 01:41:47 PM PST 24
Finished Jan 07 01:45:09 PM PST 24
Peak memory 265288 kb
Host smart-32d41f8b-c3d3-46b2-958b-61e64c50e9c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3765323231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3765323231
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1814142282
Short name T785
Test name
Test status
Simulation time 305767904 ps
CPU time 9.14 seconds
Started Jan 07 01:42:12 PM PST 24
Finished Jan 07 01:42:29 PM PST 24
Peak memory 248536 kb
Host smart-d0d6f216-2da1-487d-919e-8c9744dcee0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1814142282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1814142282
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1762935678
Short name T179
Test name
Test status
Simulation time 20980748 ps
CPU time 3.79 seconds
Started Jan 07 01:42:34 PM PST 24
Finished Jan 07 01:42:55 PM PST 24
Peak memory 241228 kb
Host smart-c7d18760-0014-4e98-a756-9ad874e12367
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762935678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1762935678
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4178781857
Short name T835
Test name
Test status
Simulation time 33944236 ps
CPU time 4.87 seconds
Started Jan 07 01:42:09 PM PST 24
Finished Jan 07 01:42:23 PM PST 24
Peak memory 235480 kb
Host smart-82a9f049-6fbc-4104-9150-148fe04b36e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4178781857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4178781857
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1239321298
Short name T837
Test name
Test status
Simulation time 6464859 ps
CPU time 1.39 seconds
Started Jan 07 01:42:29 PM PST 24
Finished Jan 07 01:42:47 PM PST 24
Peak memory 236428 kb
Host smart-8eefa111-ca45-413d-8eee-75de12a14997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1239321298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1239321298
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1262607513
Short name T780
Test name
Test status
Simulation time 2162822870 ps
CPU time 31.9 seconds
Started Jan 07 01:42:47 PM PST 24
Finished Jan 07 01:43:40 PM PST 24
Peak memory 248604 kb
Host smart-0e4e716b-da33-4d3b-b8aa-684e7c732d75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1262607513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1262607513
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1686321845
Short name T159
Test name
Test status
Simulation time 63046203857 ps
CPU time 1203.25 seconds
Started Jan 07 01:42:11 PM PST 24
Finished Jan 07 02:02:23 PM PST 24
Peak memory 265476 kb
Host smart-346b1ff3-fd99-41d0-8f64-a52db4e9dd4d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686321845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1686321845
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1321172451
Short name T819
Test name
Test status
Simulation time 73159223 ps
CPU time 5.64 seconds
Started Jan 07 01:43:00 PM PST 24
Finished Jan 07 01:43:21 PM PST 24
Peak memory 247524 kb
Host smart-b15f9c14-090e-4a8d-afcb-89c3b440386a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1321172451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1321172451
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2441815449
Short name T776
Test name
Test status
Simulation time 57143230 ps
CPU time 3.76 seconds
Started Jan 07 01:42:40 PM PST 24
Finished Jan 07 01:43:05 PM PST 24
Peak memory 238192 kb
Host smart-0add30b4-b42a-4c51-8bc5-a538ebf3f23d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441815449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2441815449
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2342607681
Short name T191
Test name
Test status
Simulation time 91487178 ps
CPU time 8.28 seconds
Started Jan 07 01:43:04 PM PST 24
Finished Jan 07 01:43:26 PM PST 24
Peak memory 240304 kb
Host smart-767896af-d692-4c12-aeb1-82877b69157e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2342607681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2342607681
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3065696453
Short name T775
Test name
Test status
Simulation time 16354974 ps
CPU time 1.81 seconds
Started Jan 07 01:42:35 PM PST 24
Finished Jan 07 01:42:56 PM PST 24
Peak memory 235688 kb
Host smart-335364f5-cb11-46ec-9b43-0b7e5e2a71f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3065696453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3065696453
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1408578747
Short name T759
Test name
Test status
Simulation time 171015485 ps
CPU time 11.66 seconds
Started Jan 07 01:42:43 PM PST 24
Finished Jan 07 01:43:15 PM PST 24
Peak memory 244692 kb
Host smart-1790ce42-56a5-4d33-8be7-746ba35e3a13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1408578747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1408578747
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.4276025611
Short name T769
Test name
Test status
Simulation time 875861903 ps
CPU time 20.28 seconds
Started Jan 07 01:43:03 PM PST 24
Finished Jan 07 01:43:37 PM PST 24
Peak memory 248728 kb
Host smart-694b110c-087a-4925-a6ac-3a3e01befe96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4276025611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.4276025611
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.104729739
Short name T29
Test name
Test status
Simulation time 39128420 ps
CPU time 3.52 seconds
Started Jan 07 01:42:27 PM PST 24
Finished Jan 07 01:42:49 PM PST 24
Peak memory 236420 kb
Host smart-89ad774f-4896-4447-86f1-66f832134371
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=104729739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.104729739
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2655933663
Short name T237
Test name
Test status
Simulation time 241355833 ps
CPU time 7.24 seconds
Started Jan 07 01:41:57 PM PST 24
Finished Jan 07 01:42:14 PM PST 24
Peak memory 243320 kb
Host smart-4effd7ab-ccaf-4421-b3cd-d31d4cc331ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655933663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2655933663
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.350096997
Short name T743
Test name
Test status
Simulation time 64407501 ps
CPU time 3.47 seconds
Started Jan 07 01:41:57 PM PST 24
Finished Jan 07 01:42:10 PM PST 24
Peak memory 235624 kb
Host smart-187cd9c0-a44c-4108-bec9-d8c47910bbf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=350096997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.350096997
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.709873124
Short name T807
Test name
Test status
Simulation time 12654776 ps
CPU time 1.2 seconds
Started Jan 07 01:42:04 PM PST 24
Finished Jan 07 01:42:14 PM PST 24
Peak memory 235628 kb
Host smart-f03cc1b1-fae4-4efc-835a-6efccc391b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=709873124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.709873124
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.135057562
Short name T756
Test name
Test status
Simulation time 326363368 ps
CPU time 18.46 seconds
Started Jan 07 01:42:07 PM PST 24
Finished Jan 07 01:42:34 PM PST 24
Peak memory 244700 kb
Host smart-801cbb77-8726-4ddc-99b1-482dd937c8c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=135057562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.135057562
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1050062719
Short name T134
Test name
Test status
Simulation time 1140573208 ps
CPU time 118.1 seconds
Started Jan 07 01:41:56 PM PST 24
Finished Jan 07 01:44:03 PM PST 24
Peak memory 257316 kb
Host smart-76bcc440-c9bd-48bb-93b5-49c23560fd6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1050062719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1050062719
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.416101708
Short name T745
Test name
Test status
Simulation time 205401928 ps
CPU time 13.83 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 01:42:23 PM PST 24
Peak memory 246316 kb
Host smart-453e1762-e658-4b72-8f2c-1275b5cc1292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=416101708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.416101708
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3394907406
Short name T533
Test name
Test status
Simulation time 62659287340 ps
CPU time 1755.66 seconds
Started Jan 07 01:40:28 PM PST 24
Finished Jan 07 02:10:09 PM PST 24
Peak memory 281376 kb
Host smart-5950c94d-f91c-4984-b83f-fd3c2f9d413b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394907406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3394907406
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1375716065
Short name T381
Test name
Test status
Simulation time 13000994555 ps
CPU time 98.21 seconds
Started Jan 07 01:40:25 PM PST 24
Finished Jan 07 01:42:27 PM PST 24
Peak memory 256768 kb
Host smart-35265766-b7c0-4376-a0cb-88d890de4ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13757
16065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1375716065
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3554950581
Short name T91
Test name
Test status
Simulation time 4636944677 ps
CPU time 75.31 seconds
Started Jan 07 01:40:21 PM PST 24
Finished Jan 07 01:42:02 PM PST 24
Peak memory 254984 kb
Host smart-8f36c94d-597b-42af-a33e-7dcbc4098486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35549
50581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3554950581
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1095086917
Short name T355
Test name
Test status
Simulation time 57326697405 ps
CPU time 1823.99 seconds
Started Jan 07 01:40:29 PM PST 24
Finished Jan 07 02:11:18 PM PST 24
Peak memory 283996 kb
Host smart-41ffc001-26a7-4fd9-9be3-28e29bd249e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095086917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1095086917
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3338590974
Short name T76
Test name
Test status
Simulation time 13577225813 ps
CPU time 968.37 seconds
Started Jan 07 01:40:33 PM PST 24
Finished Jan 07 01:57:07 PM PST 24
Peak memory 271268 kb
Host smart-91679c54-0685-4f11-ab76-66768661b755
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338590974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3338590974
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2335475252
Short name T426
Test name
Test status
Simulation time 6009675518 ps
CPU time 63.75 seconds
Started Jan 07 01:40:24 PM PST 24
Finished Jan 07 01:41:51 PM PST 24
Peak memory 247600 kb
Host smart-ee2c2526-bafa-462f-b0a1-a8bffb7d2322
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335475252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2335475252
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3988437202
Short name T598
Test name
Test status
Simulation time 1134967519 ps
CPU time 26.78 seconds
Started Jan 07 01:40:26 PM PST 24
Finished Jan 07 01:41:16 PM PST 24
Peak memory 248628 kb
Host smart-96517781-5e3e-40b7-a51a-b9c46add173a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39884
37202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3988437202
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3333763267
Short name T225
Test name
Test status
Simulation time 272172116 ps
CPU time 28.48 seconds
Started Jan 07 01:40:25 PM PST 24
Finished Jan 07 01:41:17 PM PST 24
Peak memory 256040 kb
Host smart-887edf86-2705-4017-8015-1e03a2033c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33337
63267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3333763267
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3779438632
Short name T116
Test name
Test status
Simulation time 232343907 ps
CPU time 15.99 seconds
Started Jan 07 01:40:20 PM PST 24
Finished Jan 07 01:41:01 PM PST 24
Peak memory 248572 kb
Host smart-a3fe1e59-57d7-4418-a07b-a4a029d1d391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37794
38632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3779438632
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.496358290
Short name T546
Test name
Test status
Simulation time 57610273 ps
CPU time 7.92 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 01:41:08 PM PST 24
Peak memory 248544 kb
Host smart-345b1a84-732c-450d-84d5-d4cae681ad30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49635
8290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.496358290
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1902958213
Short name T239
Test name
Test status
Simulation time 14207388559 ps
CPU time 904.82 seconds
Started Jan 07 01:40:24 PM PST 24
Finished Jan 07 01:55:53 PM PST 24
Peak memory 272952 kb
Host smart-2ca464e2-507f-4c90-9f88-cd686808cbec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902958213 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1902958213
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.4127531212
Short name T119
Test name
Test status
Simulation time 24556006075 ps
CPU time 1474.48 seconds
Started Jan 07 01:40:31 PM PST 24
Finished Jan 07 02:05:32 PM PST 24
Peak memory 273292 kb
Host smart-08b6fe18-e1b6-468f-a965-fb584061e166
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127531212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.4127531212
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2345144987
Short name T447
Test name
Test status
Simulation time 1138059956 ps
CPU time 14.31 seconds
Started Jan 07 01:40:29 PM PST 24
Finished Jan 07 01:41:09 PM PST 24
Peak memory 240444 kb
Host smart-f7eb823a-2090-4dd5-9106-977c1614485f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2345144987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2345144987
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3762106948
Short name T629
Test name
Test status
Simulation time 886634423 ps
CPU time 13.37 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 01:41:20 PM PST 24
Peak memory 248240 kb
Host smart-d23f7e4c-8cfd-426f-afb3-c1623932e830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37621
06948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3762106948
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1223109480
Short name T655
Test name
Test status
Simulation time 3930973014 ps
CPU time 163.98 seconds
Started Jan 07 01:40:30 PM PST 24
Finished Jan 07 01:43:39 PM PST 24
Peak memory 247292 kb
Host smart-a2919ccc-7fa3-49a0-95d6-1afdcbe8af97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223109480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1223109480
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1021462157
Short name T258
Test name
Test status
Simulation time 1398383554 ps
CPU time 24.31 seconds
Started Jan 07 01:40:23 PM PST 24
Finished Jan 07 01:41:11 PM PST 24
Peak memory 248644 kb
Host smart-4544adb4-9e0c-4e8e-8266-2d66c854ea24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10214
62157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1021462157
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.4242685906
Short name T436
Test name
Test status
Simulation time 161178961 ps
CPU time 5.61 seconds
Started Jan 07 01:40:24 PM PST 24
Finished Jan 07 01:40:53 PM PST 24
Peak memory 252356 kb
Host smart-67577e89-b38c-41ba-b1f4-196bd633a3eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42426
85906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.4242685906
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1330952968
Short name T11
Test name
Test status
Simulation time 509683554 ps
CPU time 27.83 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:41:35 PM PST 24
Peak memory 274260 kb
Host smart-4b1552ce-8471-46f1-a0c6-e34f10f77091
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1330952968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1330952968
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.539487822
Short name T291
Test name
Test status
Simulation time 1438544565 ps
CPU time 16.67 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 01:41:22 PM PST 24
Peak memory 254176 kb
Host smart-b83c9edc-4d0b-43f8-96ad-af44e03041f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53948
7822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.539487822
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2101546094
Short name T721
Test name
Test status
Simulation time 124716111 ps
CPU time 9.04 seconds
Started Jan 07 01:40:25 PM PST 24
Finished Jan 07 01:40:57 PM PST 24
Peak memory 240480 kb
Host smart-afc731d8-3527-4d9d-805f-5ffa807b3ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21015
46094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2101546094
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2464080485
Short name T306
Test name
Test status
Simulation time 17684946228 ps
CPU time 1040.83 seconds
Started Jan 07 01:40:31 PM PST 24
Finished Jan 07 01:58:18 PM PST 24
Peak memory 273376 kb
Host smart-c24443ca-ac2c-47b5-af7d-0d69bc6e16c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464080485 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2464080485
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2853257164
Short name T197
Test name
Test status
Simulation time 157449280 ps
CPU time 3.15 seconds
Started Jan 07 01:40:28 PM PST 24
Finished Jan 07 01:40:53 PM PST 24
Peak memory 248948 kb
Host smart-8712a2d0-3b8d-419c-b2b1-8cbb07a2ab6e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2853257164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2853257164
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.110144896
Short name T714
Test name
Test status
Simulation time 5733570033 ps
CPU time 575.44 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 01:50:36 PM PST 24
Peak memory 272688 kb
Host smart-f73384ee-07e7-4c4c-814e-374641204bd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110144896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.110144896
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3480360722
Short name T235
Test name
Test status
Simulation time 2067318957 ps
CPU time 41.82 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 01:41:51 PM PST 24
Peak memory 248520 kb
Host smart-01f24034-7e87-4f3a-90e0-e09813242d7c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3480360722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3480360722
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2634920315
Short name T604
Test name
Test status
Simulation time 2142953875 ps
CPU time 67.56 seconds
Started Jan 07 01:40:44 PM PST 24
Finished Jan 07 01:42:18 PM PST 24
Peak memory 256288 kb
Host smart-dc406feb-b4d2-4db4-af0b-d4be065c77a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26349
20315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2634920315
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2626320631
Short name T288
Test name
Test status
Simulation time 11635144863 ps
CPU time 49.5 seconds
Started Jan 07 01:40:32 PM PST 24
Finished Jan 07 01:41:47 PM PST 24
Peak memory 255104 kb
Host smart-c5ca5834-8994-4b90-aeb8-95dcf7e1845d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26263
20631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2626320631
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3758190052
Short name T513
Test name
Test status
Simulation time 20906409067 ps
CPU time 1258.02 seconds
Started Jan 07 01:40:27 PM PST 24
Finished Jan 07 02:01:48 PM PST 24
Peak memory 272296 kb
Host smart-707aa354-ad48-4af4-a002-babaa9446cf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758190052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3758190052
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.458250544
Short name T580
Test name
Test status
Simulation time 27618133398 ps
CPU time 1830.33 seconds
Started Jan 07 01:40:46 PM PST 24
Finished Jan 07 02:11:42 PM PST 24
Peak memory 288820 kb
Host smart-555e70df-90f9-465b-8b95-f0cc492bdcb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458250544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.458250544
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.344156686
Short name T638
Test name
Test status
Simulation time 28078216352 ps
CPU time 376.67 seconds
Started Jan 07 01:40:33 PM PST 24
Finished Jan 07 01:47:16 PM PST 24
Peak memory 247584 kb
Host smart-6187efce-f633-48a8-8fb1-196f44d7d5d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344156686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.344156686
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1164413821
Short name T380
Test name
Test status
Simulation time 202430102 ps
CPU time 6.15 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 01:41:11 PM PST 24
Peak memory 256812 kb
Host smart-3962a5a1-ff52-493c-9279-bd2307cc15c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11644
13821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1164413821
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.861548187
Short name T728
Test name
Test status
Simulation time 1180921117 ps
CPU time 66.17 seconds
Started Jan 07 01:40:29 PM PST 24
Finished Jan 07 01:42:01 PM PST 24
Peak memory 248664 kb
Host smart-44fcdab8-5069-4df3-b4d2-a43c9f7dacc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86154
8187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.861548187
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2920739131
Short name T500
Test name
Test status
Simulation time 581293514 ps
CPU time 15.69 seconds
Started Jan 07 01:40:41 PM PST 24
Finished Jan 07 01:41:24 PM PST 24
Peak memory 255700 kb
Host smart-3a485604-a698-4b72-8193-bab74e516942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29207
39131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2920739131
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1710286293
Short name T423
Test name
Test status
Simulation time 1080373225 ps
CPU time 20.97 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:41:28 PM PST 24
Peak memory 248780 kb
Host smart-9a4e3935-4e6f-4d2f-8d97-45ae552c0a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17102
86293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1710286293
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1987420642
Short name T711
Test name
Test status
Simulation time 22290609601 ps
CPU time 1321.88 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 02:03:06 PM PST 24
Peak memory 272648 kb
Host smart-5d15b491-0bc4-4993-a366-6318329ee170
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987420642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1987420642
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2405808154
Short name T528
Test name
Test status
Simulation time 973778222736 ps
CPU time 3861.77 seconds
Started Jan 07 01:40:46 PM PST 24
Finished Jan 07 02:45:34 PM PST 24
Peak memory 304036 kb
Host smart-e83406c8-02aa-4bd4-8738-81e601f72471
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405808154 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2405808154
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.949270096
Short name T433
Test name
Test status
Simulation time 40695457656 ps
CPU time 2136.22 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 02:16:46 PM PST 24
Peak memory 288300 kb
Host smart-81008071-ffad-4338-b8ad-276a3c171214
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949270096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.949270096
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.4202196873
Short name T661
Test name
Test status
Simulation time 189203716 ps
CPU time 9.39 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 01:41:14 PM PST 24
Peak memory 240464 kb
Host smart-9c3e0f88-45aa-4c56-ade0-93ae92c4a694
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4202196873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.4202196873
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3576736051
Short name T535
Test name
Test status
Simulation time 192164509 ps
CPU time 6.96 seconds
Started Jan 07 01:40:26 PM PST 24
Finished Jan 07 01:40:56 PM PST 24
Peak memory 240108 kb
Host smart-13b5c1d2-cd62-4c83-b3d8-4ec6440a72e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35767
36051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3576736051
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.4204418699
Short name T726
Test name
Test status
Simulation time 202642976 ps
CPU time 7.17 seconds
Started Jan 07 01:40:42 PM PST 24
Finished Jan 07 01:41:16 PM PST 24
Peak memory 240552 kb
Host smart-24718a52-d9b6-4a26-842a-ba13af61eead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42044
18699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.4204418699
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.591766669
Short name T359
Test name
Test status
Simulation time 7692336775 ps
CPU time 696.25 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:52:44 PM PST 24
Peak memory 272632 kb
Host smart-70d222fd-20eb-4a0d-a165-dbe7a3e2092a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591766669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.591766669
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2013451871
Short name T467
Test name
Test status
Simulation time 10470913106 ps
CPU time 823.02 seconds
Started Jan 07 01:40:47 PM PST 24
Finished Jan 07 01:54:56 PM PST 24
Peak memory 272772 kb
Host smart-fe86c3ed-5f0e-4adf-89b8-84b9f03873c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013451871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2013451871
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3959146645
Short name T555
Test name
Test status
Simulation time 808495199 ps
CPU time 12.64 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 01:41:19 PM PST 24
Peak memory 252380 kb
Host smart-e9864675-0a10-4996-9c02-1766acdeda6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39591
46645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3959146645
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2270867670
Short name T692
Test name
Test status
Simulation time 1090439155 ps
CPU time 59.41 seconds
Started Jan 07 01:40:36 PM PST 24
Finished Jan 07 01:42:02 PM PST 24
Peak memory 254700 kb
Host smart-b82481db-9f48-46f7-9cf9-a98d79de90c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22708
67670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2270867670
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.849719032
Short name T499
Test name
Test status
Simulation time 1222925676 ps
CPU time 14.97 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 01:41:24 PM PST 24
Peak memory 252900 kb
Host smart-f698746a-2e8a-4b99-981f-59d88bf29387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84971
9032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.849719032
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2145994445
Short name T403
Test name
Test status
Simulation time 17766567 ps
CPU time 3.06 seconds
Started Jan 07 01:40:41 PM PST 24
Finished Jan 07 01:41:11 PM PST 24
Peak memory 240440 kb
Host smart-e2573949-f102-40cb-9223-2e4676e24d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21459
94445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2145994445
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2076049844
Short name T82
Test name
Test status
Simulation time 86221367023 ps
CPU time 2049.32 seconds
Started Jan 07 01:40:45 PM PST 24
Finished Jan 07 02:15:20 PM PST 24
Peak memory 288880 kb
Host smart-b68ab33f-8f1e-4580-b3bb-3969e2bcf9ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076049844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2076049844
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2167581227
Short name T548
Test name
Test status
Simulation time 54319846401 ps
CPU time 1212.24 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 02:01:18 PM PST 24
Peak memory 283204 kb
Host smart-c3bb7163-af8e-4c3d-ad74-f13acfc99192
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167581227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2167581227
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1150091710
Short name T515
Test name
Test status
Simulation time 391740227 ps
CPU time 17.55 seconds
Started Jan 07 01:40:18 PM PST 24
Finished Jan 07 01:41:01 PM PST 24
Peak memory 240240 kb
Host smart-a8045e99-7430-45be-9b89-1f9ccae02c09
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1150091710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1150091710
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.197425927
Short name T521
Test name
Test status
Simulation time 2916915499 ps
CPU time 113.08 seconds
Started Jan 07 01:40:32 PM PST 24
Finished Jan 07 01:42:51 PM PST 24
Peak memory 249608 kb
Host smart-2d80c579-e82f-4c39-b0c0-d44e5d27e3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19742
5927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.197425927
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1516675735
Short name T474
Test name
Test status
Simulation time 1710723059 ps
CPU time 64.57 seconds
Started Jan 07 01:40:27 PM PST 24
Finished Jan 07 01:41:54 PM PST 24
Peak memory 254260 kb
Host smart-406509ce-1044-40fb-bcfe-5b657fbae1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15166
75735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1516675735
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1089574141
Short name T219
Test name
Test status
Simulation time 17996854856 ps
CPU time 1387.52 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 02:04:08 PM PST 24
Peak memory 289024 kb
Host smart-a06093d7-98d8-4bd8-8f24-6dc110715e3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089574141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1089574141
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2493602009
Short name T449
Test name
Test status
Simulation time 111220614 ps
CPU time 4.62 seconds
Started Jan 07 01:40:47 PM PST 24
Finished Jan 07 01:41:17 PM PST 24
Peak memory 240488 kb
Host smart-60e3dde7-a8c0-4c10-a767-a515c9fcbd36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24936
02009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2493602009
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2891426858
Short name T492
Test name
Test status
Simulation time 937431149 ps
CPU time 44.81 seconds
Started Jan 07 01:40:28 PM PST 24
Finished Jan 07 01:41:38 PM PST 24
Peak memory 248292 kb
Host smart-bf1cfddc-4fbc-4942-bcc7-59b4760b6e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28914
26858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2891426858
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2775528966
Short name T307
Test name
Test status
Simulation time 506746740 ps
CPU time 17.59 seconds
Started Jan 07 01:40:28 PM PST 24
Finished Jan 07 01:41:11 PM PST 24
Peak memory 254108 kb
Host smart-466d333e-6f59-45cb-8616-b2e6cafa6843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27755
28966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2775528966
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.666619400
Short name T371
Test name
Test status
Simulation time 1048173782 ps
CPU time 56.74 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 01:42:04 PM PST 24
Peak memory 256692 kb
Host smart-109aef98-fc9f-4e71-baa7-855f62d8ce03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66661
9400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.666619400
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3591152298
Short name T597
Test name
Test status
Simulation time 41164328306 ps
CPU time 2060.04 seconds
Started Jan 07 01:40:27 PM PST 24
Finished Jan 07 02:15:10 PM PST 24
Peak memory 288148 kb
Host smart-e343b896-1876-42f0-9eaf-0320274c7d38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591152298 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3591152298
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1077656380
Short name T199
Test name
Test status
Simulation time 97038105 ps
CPU time 3.11 seconds
Started Jan 07 01:40:48 PM PST 24
Finished Jan 07 01:41:16 PM PST 24
Peak memory 248876 kb
Host smart-f2d68b4c-49dd-4051-8476-a18249e6f66c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1077656380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1077656380
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3930984935
Short name T272
Test name
Test status
Simulation time 68526673556 ps
CPU time 1458.98 seconds
Started Jan 07 01:40:29 PM PST 24
Finished Jan 07 02:05:14 PM PST 24
Peak memory 289048 kb
Host smart-aacee963-6a58-4f05-95fe-89ec8a38beea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930984935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3930984935
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3489036147
Short name T501
Test name
Test status
Simulation time 4262927918 ps
CPU time 30.62 seconds
Started Jan 07 01:40:27 PM PST 24
Finished Jan 07 01:41:20 PM PST 24
Peak memory 240484 kb
Host smart-14484a17-bb07-47f8-bc59-fe30d7b1cc14
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3489036147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3489036147
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.933051221
Short name T514
Test name
Test status
Simulation time 12787364762 ps
CPU time 181.44 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 01:44:11 PM PST 24
Peak memory 256484 kb
Host smart-b046fa1c-18d2-4eb9-ad1a-4ff14afb5ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93305
1221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.933051221
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2883170521
Short name T507
Test name
Test status
Simulation time 212490485 ps
CPU time 14.69 seconds
Started Jan 07 01:40:42 PM PST 24
Finished Jan 07 01:41:23 PM PST 24
Peak memory 248280 kb
Host smart-d2610e16-929b-44af-85aa-d01a56b15a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28831
70521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2883170521
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.544036525
Short name T354
Test name
Test status
Simulation time 12817677115 ps
CPU time 922.27 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 01:56:26 PM PST 24
Peak memory 282352 kb
Host smart-49766788-801c-4803-b3cc-63d6a00bda11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544036525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.544036525
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2892960939
Short name T438
Test name
Test status
Simulation time 16818278832 ps
CPU time 1223.54 seconds
Started Jan 07 01:40:44 PM PST 24
Finished Jan 07 02:01:34 PM PST 24
Peak memory 286500 kb
Host smart-3420e99d-6b92-44c1-8999-d7ece80d46bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892960939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2892960939
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3926202573
Short name T313
Test name
Test status
Simulation time 2641381861 ps
CPU time 106.93 seconds
Started Jan 07 01:40:35 PM PST 24
Finished Jan 07 01:42:48 PM PST 24
Peak memory 246528 kb
Host smart-fe56f310-f523-4263-8f7b-83b4c787141c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926202573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3926202573
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.4022611020
Short name T475
Test name
Test status
Simulation time 166411839 ps
CPU time 13.13 seconds
Started Jan 07 01:40:24 PM PST 24
Finished Jan 07 01:41:00 PM PST 24
Peak memory 248680 kb
Host smart-30eeb46e-6728-4621-8c8f-3d61c5426fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40226
11020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.4022611020
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1136681641
Short name T379
Test name
Test status
Simulation time 3649742787 ps
CPU time 55.95 seconds
Started Jan 07 01:40:30 PM PST 24
Finished Jan 07 01:41:52 PM PST 24
Peak memory 247228 kb
Host smart-cc756945-6d50-436f-b6e4-99d44aa39b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11366
81641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1136681641
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.319161223
Short name T296
Test name
Test status
Simulation time 155200376 ps
CPU time 12.44 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 01:41:22 PM PST 24
Peak memory 247748 kb
Host smart-0504f33a-3aea-464e-a29d-b39fa32c2cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31916
1223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.319161223
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3608191343
Short name T672
Test name
Test status
Simulation time 183429377 ps
CPU time 6.87 seconds
Started Jan 07 01:40:45 PM PST 24
Finished Jan 07 01:41:18 PM PST 24
Peak memory 248664 kb
Host smart-28c7bf1a-517d-46a3-ae71-d379b4f0418c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36081
91343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3608191343
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2962295433
Short name T631
Test name
Test status
Simulation time 515760473 ps
CPU time 29.93 seconds
Started Jan 07 01:40:42 PM PST 24
Finished Jan 07 01:41:39 PM PST 24
Peak memory 248756 kb
Host smart-b21f3146-8802-47b2-9b28-434ecc9867d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962295433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2962295433
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.825759134
Short name T657
Test name
Test status
Simulation time 249440798527 ps
CPU time 2454.94 seconds
Started Jan 07 01:40:36 PM PST 24
Finished Jan 07 02:21:57 PM PST 24
Peak memory 285964 kb
Host smart-c82b8821-78ed-43fe-bc7b-7323d58ea1f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825759134 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.825759134
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.777584013
Short name T206
Test name
Test status
Simulation time 33353442 ps
CPU time 2.23 seconds
Started Jan 07 01:40:44 PM PST 24
Finished Jan 07 01:41:12 PM PST 24
Peak memory 248920 kb
Host smart-c8e77cb4-8611-40f5-9671-faa40208d9b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=777584013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.777584013
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1147970788
Short name T679
Test name
Test status
Simulation time 26536612271 ps
CPU time 1590.5 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 02:07:38 PM PST 24
Peak memory 272804 kb
Host smart-6807d538-82f9-4ad6-84f0-97d2a89bb669
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147970788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1147970788
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2658149787
Short name T434
Test name
Test status
Simulation time 2004948765 ps
CPU time 11 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 01:41:21 PM PST 24
Peak memory 252472 kb
Host smart-44671754-1ce0-4c4a-893a-cd967e99ed46
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2658149787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2658149787
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3793275960
Short name T562
Test name
Test status
Simulation time 705831139 ps
CPU time 13.27 seconds
Started Jan 07 01:40:45 PM PST 24
Finished Jan 07 01:41:24 PM PST 24
Peak memory 255196 kb
Host smart-1d8895d3-afac-41eb-837c-84c818fa03a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37932
75960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3793275960
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2564985744
Short name T626
Test name
Test status
Simulation time 1988190554 ps
CPU time 35.54 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 01:41:36 PM PST 24
Peak memory 254504 kb
Host smart-52f2eef9-e11b-4436-b63a-9c7efe7f6072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25649
85744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2564985744
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1669326169
Short name T4
Test name
Test status
Simulation time 98628617967 ps
CPU time 1481.02 seconds
Started Jan 07 01:40:41 PM PST 24
Finished Jan 07 02:05:49 PM PST 24
Peak memory 272304 kb
Host smart-27e9c8c5-26c2-434a-a62b-14708542ce50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669326169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1669326169
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.81201906
Short name T333
Test name
Test status
Simulation time 23696683278 ps
CPU time 460.83 seconds
Started Jan 07 01:40:33 PM PST 24
Finished Jan 07 01:48:40 PM PST 24
Peak memory 247604 kb
Host smart-511cd5a3-d58f-4886-a8a3-b9a8a8afd138
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81201906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.81201906
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1640825870
Short name T257
Test name
Test status
Simulation time 2642898248 ps
CPU time 42.84 seconds
Started Jan 07 01:40:30 PM PST 24
Finished Jan 07 01:41:39 PM PST 24
Peak memory 248892 kb
Host smart-41c36907-83fd-41ed-ba57-43ac71b592a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16408
25870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1640825870
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3877670651
Short name T519
Test name
Test status
Simulation time 4311287905 ps
CPU time 52.9 seconds
Started Jan 07 01:40:48 PM PST 24
Finished Jan 07 01:42:06 PM PST 24
Peak memory 254584 kb
Host smart-bd7f430f-ba7a-480d-8bf0-7cab7a6fda14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38776
70651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3877670651
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2488947435
Short name T552
Test name
Test status
Simulation time 3228011098 ps
CPU time 48.75 seconds
Started Jan 07 01:40:28 PM PST 24
Finished Jan 07 01:41:42 PM PST 24
Peak memory 255848 kb
Host smart-5916caea-2aa6-493c-871c-cb1988608547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24889
47435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2488947435
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3176240994
Short name T697
Test name
Test status
Simulation time 54497953 ps
CPU time 2.71 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 01:41:13 PM PST 24
Peak memory 240384 kb
Host smart-a97121f9-3017-4b6c-94d4-c957084181c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31762
40994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3176240994
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.951514818
Short name T287
Test name
Test status
Simulation time 243020873472 ps
CPU time 2783.69 seconds
Started Jan 07 01:40:42 PM PST 24
Finished Jan 07 02:27:33 PM PST 24
Peak memory 289704 kb
Host smart-a8256ae9-e576-4b1f-9833-874d95d4d008
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951514818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.951514818
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.4254569037
Short name T557
Test name
Test status
Simulation time 129586172157 ps
CPU time 7311.22 seconds
Started Jan 07 01:40:41 PM PST 24
Finished Jan 07 03:43:00 PM PST 24
Peak memory 335592 kb
Host smart-caeb99f5-3c8b-408f-99cc-d353aeb6ac34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254569037 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.4254569037
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1038419737
Short name T212
Test name
Test status
Simulation time 45343805 ps
CPU time 3.57 seconds
Started Jan 07 01:40:36 PM PST 24
Finished Jan 07 01:41:06 PM PST 24
Peak memory 248884 kb
Host smart-d597fad0-72d6-4435-8964-dd010185849a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1038419737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1038419737
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2990068001
Short name T275
Test name
Test status
Simulation time 36770732855 ps
CPU time 894.6 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 01:55:55 PM PST 24
Peak memory 284532 kb
Host smart-aa9a115e-90ad-4ada-88f1-3e05268809f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990068001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2990068001
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.4228899494
Short name T385
Test name
Test status
Simulation time 530427417 ps
CPU time 18.5 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 01:41:23 PM PST 24
Peak memory 240476 kb
Host smart-c4f07783-5e05-4f3d-9571-0ff540ea72b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4228899494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4228899494
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.996126691
Short name T479
Test name
Test status
Simulation time 1762810635 ps
CPU time 70.77 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:42:18 PM PST 24
Peak memory 255868 kb
Host smart-951f4f10-dbe8-4d95-9995-0c03c67d5921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99612
6691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.996126691
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.244004202
Short name T79
Test name
Test status
Simulation time 313654689869 ps
CPU time 2130.2 seconds
Started Jan 07 01:40:31 PM PST 24
Finished Jan 07 02:16:27 PM PST 24
Peak memory 281516 kb
Host smart-81b29ce4-c429-4dc2-b8db-7f8e7991d7b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244004202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.244004202
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2636818436
Short name T681
Test name
Test status
Simulation time 89348441074 ps
CPU time 452.16 seconds
Started Jan 07 01:40:41 PM PST 24
Finished Jan 07 01:48:40 PM PST 24
Peak memory 246664 kb
Host smart-158a348b-97bc-4ffd-a3d6-93ceed6dd741
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636818436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2636818436
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.11194132
Short name T600
Test name
Test status
Simulation time 4182584684 ps
CPU time 45.93 seconds
Started Jan 07 01:40:44 PM PST 24
Finished Jan 07 01:41:56 PM PST 24
Peak memory 248672 kb
Host smart-8700cb6c-8e3a-4523-af0d-d1443da13578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11194
132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.11194132
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.4134254382
Short name T615
Test name
Test status
Simulation time 468409117 ps
CPU time 30.48 seconds
Started Jan 07 01:40:32 PM PST 24
Finished Jan 07 01:41:29 PM PST 24
Peak memory 247504 kb
Host smart-dc58cc53-e1d4-4d45-b03c-8fa22ee567fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41342
54382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.4134254382
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1494490619
Short name T593
Test name
Test status
Simulation time 68755701 ps
CPU time 6.76 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 01:41:11 PM PST 24
Peak memory 246944 kb
Host smart-c4b8f97a-4d46-4d30-b5b3-b81cac7290f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14944
90619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1494490619
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.4261860849
Short name T608
Test name
Test status
Simulation time 416706510 ps
CPU time 25.98 seconds
Started Jan 07 01:40:58 PM PST 24
Finished Jan 07 01:41:42 PM PST 24
Peak memory 248592 kb
Host smart-e67ac642-b616-4d4f-a73a-d7bb77813e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42618
60849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.4261860849
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3034979626
Short name T92
Test name
Test status
Simulation time 87418629904 ps
CPU time 2578.21 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 02:24:05 PM PST 24
Peak memory 289712 kb
Host smart-f3742837-5c12-434c-9a74-03e435f80810
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034979626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3034979626
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3212440249
Short name T94
Test name
Test status
Simulation time 47618870697 ps
CPU time 3155.85 seconds
Started Jan 07 01:40:26 PM PST 24
Finished Jan 07 02:33:25 PM PST 24
Peak memory 298284 kb
Host smart-cc6d1baf-6f36-42a4-ab22-1999bc9d9c32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212440249 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3212440249
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1296800706
Short name T193
Test name
Test status
Simulation time 18043276 ps
CPU time 2.7 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:41:10 PM PST 24
Peak memory 248816 kb
Host smart-9cc67725-4296-4b56-8b22-1b21d9bc108b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1296800706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1296800706
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.656639344
Short name T612
Test name
Test status
Simulation time 2921743274 ps
CPU time 34.49 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 01:41:39 PM PST 24
Peak memory 240472 kb
Host smart-f30fca6e-84e4-41c4-98bb-92bcd29a4da2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=656639344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.656639344
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1178301951
Short name T276
Test name
Test status
Simulation time 1821232920 ps
CPU time 26.69 seconds
Started Jan 07 01:40:49 PM PST 24
Finished Jan 07 01:41:40 PM PST 24
Peak memory 255332 kb
Host smart-bb283289-7c35-4a83-bb8b-11c0a82f061c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11783
01951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1178301951
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.656019646
Short name T441
Test name
Test status
Simulation time 2873294573 ps
CPU time 20.68 seconds
Started Jan 07 01:40:29 PM PST 24
Finished Jan 07 01:41:16 PM PST 24
Peak memory 248344 kb
Host smart-829c3b3a-9f90-4ca3-8d43-e066510b0392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65601
9646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.656019646
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2471862589
Short name T350
Test name
Test status
Simulation time 88249876114 ps
CPU time 2377.99 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 02:20:42 PM PST 24
Peak memory 289476 kb
Host smart-4572ad93-9929-457f-8082-e873731b02b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471862589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2471862589
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1716035884
Short name T486
Test name
Test status
Simulation time 124521471797 ps
CPU time 1872.2 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 02:12:16 PM PST 24
Peak memory 286452 kb
Host smart-2cbd0ffa-872e-42b8-8cbc-7bf20a1bd0e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716035884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1716035884
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2241276960
Short name T415
Test name
Test status
Simulation time 1143791924 ps
CPU time 36.76 seconds
Started Jan 07 01:40:42 PM PST 24
Finished Jan 07 01:41:46 PM PST 24
Peak memory 255400 kb
Host smart-3d9dc519-77db-403c-91bb-26cd8022eb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22412
76960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2241276960
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2687665103
Short name T660
Test name
Test status
Simulation time 2683382657 ps
CPU time 33.05 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 01:41:38 PM PST 24
Peak memory 255088 kb
Host smart-68cfda99-1464-4f40-a345-78bc446e5a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26876
65103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2687665103
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3247534130
Short name T527
Test name
Test status
Simulation time 5000214022 ps
CPU time 47.86 seconds
Started Jan 07 01:40:33 PM PST 24
Finished Jan 07 01:41:47 PM PST 24
Peak memory 254880 kb
Host smart-bc344c05-70a1-4333-94d0-ef0c39475fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32475
34130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3247534130
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1190868347
Short name T570
Test name
Test status
Simulation time 773832787 ps
CPU time 15.45 seconds
Started Jan 07 01:40:35 PM PST 24
Finished Jan 07 01:41:16 PM PST 24
Peak memory 248752 kb
Host smart-c2268cb1-5812-4222-878c-7f65e301ae66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11908
68347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1190868347
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3009040674
Short name T468
Test name
Test status
Simulation time 22888944246 ps
CPU time 1479.53 seconds
Started Jan 07 01:40:41 PM PST 24
Finished Jan 07 02:05:48 PM PST 24
Peak memory 273328 kb
Host smart-a6fcaa98-bf78-4898-be32-6b4cb35587c8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009040674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3009040674
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.786133256
Short name T207
Test name
Test status
Simulation time 169764127 ps
CPU time 3.23 seconds
Started Jan 07 01:40:45 PM PST 24
Finished Jan 07 01:41:15 PM PST 24
Peak memory 248916 kb
Host smart-9aacc519-2e32-408d-937d-b84a29c96f10
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=786133256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.786133256
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3097202760
Short name T419
Test name
Test status
Simulation time 867750738 ps
CPU time 10.99 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 01:41:18 PM PST 24
Peak memory 240472 kb
Host smart-4a005d12-8903-4345-8a7f-4bf9d4fd9a5c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3097202760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3097202760
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1975902773
Short name T416
Test name
Test status
Simulation time 5192536973 ps
CPU time 130.46 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 01:43:15 PM PST 24
Peak memory 256816 kb
Host smart-b6f1c68c-3c1c-44c7-a8bc-6fc9c21b84d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19759
02773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1975902773
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.812776200
Short name T553
Test name
Test status
Simulation time 42790659462 ps
CPU time 2207.08 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 02:17:54 PM PST 24
Peak memory 287528 kb
Host smart-50a2fff9-1248-4137-882f-e30eea9c6ef0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812776200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.812776200
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.76748821
Short name T701
Test name
Test status
Simulation time 61297900231 ps
CPU time 414.45 seconds
Started Jan 07 01:40:48 PM PST 24
Finished Jan 07 01:48:08 PM PST 24
Peak memory 247576 kb
Host smart-9fc8bcb2-cf1e-455c-80dd-672032a9f89f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76748821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.76748821
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3550285576
Short name T375
Test name
Test status
Simulation time 501317592 ps
CPU time 8.84 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 01:41:12 PM PST 24
Peak memory 251496 kb
Host smart-a3d2ab55-175f-4025-8881-8d239583cc5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35502
85576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3550285576
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3871504702
Short name T704
Test name
Test status
Simulation time 254864539 ps
CPU time 3.85 seconds
Started Jan 07 01:40:36 PM PST 24
Finished Jan 07 01:41:06 PM PST 24
Peak memory 238736 kb
Host smart-3e539b96-16b4-483f-a8df-44bc8f0bcf69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38715
04702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3871504702
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3795114582
Short name T305
Test name
Test status
Simulation time 1824954126 ps
CPU time 30.4 seconds
Started Jan 07 01:40:35 PM PST 24
Finished Jan 07 01:41:31 PM PST 24
Peak memory 254356 kb
Host smart-ede49123-beb3-40f0-beac-961287d724fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37951
14582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3795114582
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2537202046
Short name T448
Test name
Test status
Simulation time 758873449 ps
CPU time 42.68 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 01:41:47 PM PST 24
Peak memory 248704 kb
Host smart-6f68f63b-189b-4b47-8009-9ae2c0635458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25372
02046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2537202046
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.618466575
Short name T675
Test name
Test status
Simulation time 29606240731 ps
CPU time 1290.95 seconds
Started Jan 07 01:40:33 PM PST 24
Finished Jan 07 02:02:30 PM PST 24
Peak memory 288900 kb
Host smart-a73cc586-d9d1-496c-817f-3f77a421bd1c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618466575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.618466575
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1381768651
Short name T195
Test name
Test status
Simulation time 19569192 ps
CPU time 2.52 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 01:41:08 PM PST 24
Peak memory 248932 kb
Host smart-72ce68b8-ec6a-4657-b35a-f3bf440d72b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1381768651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1381768651
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1506350425
Short name T435
Test name
Test status
Simulation time 155176328448 ps
CPU time 2022.09 seconds
Started Jan 07 01:40:29 PM PST 24
Finished Jan 07 02:14:36 PM PST 24
Peak memory 282244 kb
Host smart-119bfec3-d6d5-44b3-97be-955a01dc6ec5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506350425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1506350425
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2175999939
Short name T466
Test name
Test status
Simulation time 1558486648 ps
CPU time 20.95 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:41:28 PM PST 24
Peak memory 240448 kb
Host smart-97f66f2a-065e-4cf3-9bb4-0b0aab4bc81b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2175999939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2175999939
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1886750773
Short name T464
Test name
Test status
Simulation time 3333439174 ps
CPU time 30.48 seconds
Started Jan 07 01:40:27 PM PST 24
Finished Jan 07 01:41:20 PM PST 24
Peak memory 248652 kb
Host smart-c7fbf2b3-714a-425a-a54d-9a5cf70d6d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18867
50773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1886750773
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2095616323
Short name T656
Test name
Test status
Simulation time 2176136770 ps
CPU time 34.17 seconds
Started Jan 07 01:40:41 PM PST 24
Finished Jan 07 01:41:43 PM PST 24
Peak memory 254516 kb
Host smart-e1331bc9-46a4-4bed-988b-7cd98b85c60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20956
16323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2095616323
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.726056822
Short name T344
Test name
Test status
Simulation time 78143400849 ps
CPU time 1235.65 seconds
Started Jan 07 01:40:50 PM PST 24
Finished Jan 07 02:01:51 PM PST 24
Peak memory 272528 kb
Host smart-fe3455af-4839-493a-bc1c-84a0e27991e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726056822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.726056822
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2431719965
Short name T118
Test name
Test status
Simulation time 150502491619 ps
CPU time 2323.39 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 02:19:47 PM PST 24
Peak memory 286808 kb
Host smart-19276967-d356-4b8b-b529-b073112685da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431719965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2431719965
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.4004085728
Short name T556
Test name
Test status
Simulation time 7783990785 ps
CPU time 320.76 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 01:46:30 PM PST 24
Peak memory 247564 kb
Host smart-0502d2ea-7ab7-4114-aff3-a8021658dc7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004085728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.4004085728
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3386398451
Short name T650
Test name
Test status
Simulation time 677132574 ps
CPU time 40.3 seconds
Started Jan 07 01:40:51 PM PST 24
Finished Jan 07 01:41:55 PM PST 24
Peak memory 255380 kb
Host smart-569e1223-1431-4afb-b1de-4cfd4128c090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33863
98451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3386398451
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3499593793
Short name T520
Test name
Test status
Simulation time 1352665390 ps
CPU time 20.64 seconds
Started Jan 07 01:40:23 PM PST 24
Finished Jan 07 01:41:07 PM PST 24
Peak memory 246908 kb
Host smart-52d2ff59-2a11-450a-9479-885229e0d923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34995
93793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3499593793
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1405933080
Short name T498
Test name
Test status
Simulation time 1486910716 ps
CPU time 31.42 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 01:41:41 PM PST 24
Peak memory 255312 kb
Host smart-95f71f20-b497-4f81-9434-1dd66a91ef87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14059
33080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1405933080
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2786682770
Short name T442
Test name
Test status
Simulation time 3302082865 ps
CPU time 42.53 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 01:41:52 PM PST 24
Peak memory 248708 kb
Host smart-98b9958c-5d97-4671-83ef-15b4285cbeda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27866
82770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2786682770
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3429468351
Short name T481
Test name
Test status
Simulation time 234247975726 ps
CPU time 947.88 seconds
Started Jan 07 01:40:41 PM PST 24
Finished Jan 07 01:56:56 PM PST 24
Peak memory 281836 kb
Host smart-baafb4cf-c74b-4fbd-9250-2dae90524ee1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429468351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3429468351
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1467251799
Short name T658
Test name
Test status
Simulation time 50572269770 ps
CPU time 4601.53 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 02:57:51 PM PST 24
Peak memory 354032 kb
Host smart-043d7c74-e1b9-40e9-b529-16199c3214ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467251799 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1467251799
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2656336866
Short name T198
Test name
Test status
Simulation time 46555187 ps
CPU time 3.84 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 01:41:09 PM PST 24
Peak memory 248936 kb
Host smart-909211b0-6f01-4d9e-a865-b5667f809b8d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2656336866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2656336866
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1723356750
Short name T680
Test name
Test status
Simulation time 28219073292 ps
CPU time 1734.99 seconds
Started Jan 07 01:40:29 PM PST 24
Finished Jan 07 02:09:50 PM PST 24
Peak memory 285100 kb
Host smart-e7e435cb-5045-40a1-b450-71a4caa65897
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723356750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1723356750
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2518557780
Short name T559
Test name
Test status
Simulation time 515989142 ps
CPU time 24.46 seconds
Started Jan 07 01:40:28 PM PST 24
Finished Jan 07 01:41:18 PM PST 24
Peak memory 248644 kb
Host smart-99493431-963d-404e-85e3-a5d76adf29ed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2518557780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2518557780
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.216896881
Short name T243
Test name
Test status
Simulation time 4479205314 ps
CPU time 236.69 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 01:44:57 PM PST 24
Peak memory 255972 kb
Host smart-2c7585bb-9306-42ed-806f-5856bc0e75df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21689
6881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.216896881
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.870834277
Short name T625
Test name
Test status
Simulation time 1188812870 ps
CPU time 31.48 seconds
Started Jan 07 01:40:45 PM PST 24
Finished Jan 07 01:41:42 PM PST 24
Peak memory 254456 kb
Host smart-c49b09aa-fadb-4274-96e3-b10ce3c98a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87083
4277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.870834277
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.197003841
Short name T347
Test name
Test status
Simulation time 41269729275 ps
CPU time 1249.76 seconds
Started Jan 07 01:40:50 PM PST 24
Finished Jan 07 02:02:04 PM PST 24
Peak memory 289344 kb
Host smart-4a9f6480-c73d-4251-94ed-1fc67bc97540
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197003841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.197003841
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1313830963
Short name T717
Test name
Test status
Simulation time 15105639984 ps
CPU time 1196.08 seconds
Started Jan 07 01:40:47 PM PST 24
Finished Jan 07 02:01:08 PM PST 24
Peak memory 288748 kb
Host smart-62639230-eafa-4b41-a6a3-9f5ddbba9b7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313830963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1313830963
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.511872805
Short name T705
Test name
Test status
Simulation time 2136067715 ps
CPU time 19.09 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 01:41:24 PM PST 24
Peak memory 248604 kb
Host smart-10274573-a11d-480b-a35d-2e1692bda7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51187
2805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.511872805
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.371553506
Short name T496
Test name
Test status
Simulation time 589584740 ps
CPU time 33.38 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 01:41:39 PM PST 24
Peak memory 255544 kb
Host smart-a87841b7-4d9b-4720-a9dd-08b08284618c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37155
3506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.371553506
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.987890462
Short name T370
Test name
Test status
Simulation time 517016091 ps
CPU time 22.96 seconds
Started Jan 07 01:40:36 PM PST 24
Finished Jan 07 01:41:25 PM PST 24
Peak memory 255304 kb
Host smart-124657f2-4801-4b33-90eb-58acfcd2901e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98789
0462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.987890462
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2906880097
Short name T56
Test name
Test status
Simulation time 27662758046 ps
CPU time 812.86 seconds
Started Jan 07 01:40:35 PM PST 24
Finished Jan 07 01:54:34 PM PST 24
Peak memory 257024 kb
Host smart-63d53022-5bf0-4d6d-889e-c372eecb280a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906880097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2906880097
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3321477742
Short name T211
Test name
Test status
Simulation time 32415197 ps
CPU time 3.37 seconds
Started Jan 07 01:40:42 PM PST 24
Finished Jan 07 01:41:12 PM PST 24
Peak memory 248928 kb
Host smart-6f68494c-8966-489d-a15b-ea47ef7b8603
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3321477742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3321477742
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3237565956
Short name T107
Test name
Test status
Simulation time 18952332429 ps
CPU time 1653.72 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 02:08:38 PM PST 24
Peak memory 289624 kb
Host smart-401ff850-1ad5-48fd-a07c-d0c9e8458bbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237565956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3237565956
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3193005200
Short name T51
Test name
Test status
Simulation time 1071452026 ps
CPU time 45.59 seconds
Started Jan 07 01:40:28 PM PST 24
Finished Jan 07 01:41:39 PM PST 24
Peak memory 248612 kb
Host smart-d52ed6de-d72e-4f2e-9ca3-024cfe49fbd8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3193005200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3193005200
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3437132811
Short name T526
Test name
Test status
Simulation time 2828113905 ps
CPU time 63.11 seconds
Started Jan 07 01:40:35 PM PST 24
Finished Jan 07 01:42:05 PM PST 24
Peak memory 248112 kb
Host smart-bdcaecc7-6373-4520-855e-e64cbef9aad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34371
32811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3437132811
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.4003749657
Short name T613
Test name
Test status
Simulation time 1490912295 ps
CPU time 19.18 seconds
Started Jan 07 01:40:33 PM PST 24
Finished Jan 07 01:41:18 PM PST 24
Peak memory 254620 kb
Host smart-a68faaa4-9914-42c5-b730-09ec85d211a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40037
49657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.4003749657
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.4140081582
Short name T648
Test name
Test status
Simulation time 60510392030 ps
CPU time 1667.17 seconds
Started Jan 07 01:40:23 PM PST 24
Finished Jan 07 02:08:34 PM PST 24
Peak memory 267116 kb
Host smart-c3f4458c-7814-43b1-a47d-ce4bd6ba921c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140081582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.4140081582
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1264078400
Short name T387
Test name
Test status
Simulation time 26353008081 ps
CPU time 1283.83 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 02:02:29 PM PST 24
Peak memory 289148 kb
Host smart-a7cae777-cfaa-49a9-a605-77e602a9e0a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264078400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1264078400
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3951239376
Short name T315
Test name
Test status
Simulation time 29258369829 ps
CPU time 593.34 seconds
Started Jan 07 01:40:30 PM PST 24
Finished Jan 07 01:50:49 PM PST 24
Peak memory 247552 kb
Host smart-f386f38c-1885-42bb-af3e-7f1b52a408ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951239376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3951239376
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.87841647
Short name T565
Test name
Test status
Simulation time 229289051 ps
CPU time 25.31 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 01:41:29 PM PST 24
Peak memory 248592 kb
Host smart-270ef62a-4a12-4927-9263-041b6d8028cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87841
647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.87841647
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.4172718418
Short name T720
Test name
Test status
Simulation time 2720416479 ps
CPU time 48.51 seconds
Started Jan 07 01:40:50 PM PST 24
Finished Jan 07 01:42:03 PM PST 24
Peak memory 255936 kb
Host smart-74ef7001-2365-4e01-b934-219f7c725061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41727
18418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.4172718418
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.866335074
Short name T45
Test name
Test status
Simulation time 1386877004 ps
CPU time 20.24 seconds
Started Jan 07 01:40:36 PM PST 24
Finished Jan 07 01:41:23 PM PST 24
Peak memory 276716 kb
Host smart-c3eac890-1116-443f-9832-17c6afe117f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=866335074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.866335074
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2930112104
Short name T495
Test name
Test status
Simulation time 10340765250 ps
CPU time 53.01 seconds
Started Jan 07 01:40:53 PM PST 24
Finished Jan 07 01:42:08 PM PST 24
Peak memory 255476 kb
Host smart-e89b9767-79b6-4980-b1f0-6d876678ad5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29301
12104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2930112104
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1842392951
Short name T454
Test name
Test status
Simulation time 251888559 ps
CPU time 25.63 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 01:41:26 PM PST 24
Peak memory 248556 kb
Host smart-230e8158-cbff-4b2f-ba9a-09c349f3b85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18423
92951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1842392951
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3520589846
Short name T461
Test name
Test status
Simulation time 34488970031 ps
CPU time 766.57 seconds
Started Jan 07 01:40:36 PM PST 24
Finished Jan 07 01:53:50 PM PST 24
Peak memory 270212 kb
Host smart-93900ffd-3ed2-4626-bd56-0411eec9e8f5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520589846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3520589846
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.3955714866
Short name T215
Test name
Test status
Simulation time 87383562570 ps
CPU time 2237.71 seconds
Started Jan 07 01:40:23 PM PST 24
Finished Jan 07 02:18:05 PM PST 24
Peak memory 322040 kb
Host smart-651efa1c-acb8-4f87-b62a-8717f162a1fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955714866 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.3955714866
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.4087863787
Short name T61
Test name
Test status
Simulation time 43772279920 ps
CPU time 973.84 seconds
Started Jan 07 01:41:01 PM PST 24
Finished Jan 07 01:57:32 PM PST 24
Peak memory 272484 kb
Host smart-80e8127c-526d-4076-97db-eddfb7ab5b46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087863787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.4087863787
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3344450408
Short name T644
Test name
Test status
Simulation time 9210102799 ps
CPU time 155.37 seconds
Started Jan 07 01:40:51 PM PST 24
Finished Jan 07 01:43:50 PM PST 24
Peak memory 256908 kb
Host smart-719aadad-0131-4dc0-983f-92a4ff0313a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33444
50408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3344450408
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.641503276
Short name T458
Test name
Test status
Simulation time 170543314 ps
CPU time 10.81 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 01:41:11 PM PST 24
Peak memory 252672 kb
Host smart-31ed8fc0-964f-4da2-b274-ed9f09385e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64150
3276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.641503276
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3788024821
Short name T327
Test name
Test status
Simulation time 83285845902 ps
CPU time 2337.59 seconds
Started Jan 07 01:41:35 PM PST 24
Finished Jan 07 02:20:41 PM PST 24
Peak memory 281672 kb
Host smart-7d6647f4-87bc-4d5c-a93e-aa357aed5c68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788024821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3788024821
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.770487666
Short name T602
Test name
Test status
Simulation time 65190377688 ps
CPU time 1305.33 seconds
Started Jan 07 01:40:57 PM PST 24
Finished Jan 07 02:03:01 PM PST 24
Peak memory 289260 kb
Host smart-6e7a729a-fd57-42e7-a61f-4dae090ec079
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770487666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.770487666
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.867871447
Short name T321
Test name
Test status
Simulation time 15934211447 ps
CPU time 186.26 seconds
Started Jan 07 01:41:31 PM PST 24
Finished Jan 07 01:44:44 PM PST 24
Peak memory 247576 kb
Host smart-cf87d417-524b-4d62-bdc0-b1c5a10d09d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867871447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.867871447
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1907924
Short name T20
Test name
Test status
Simulation time 1265411876 ps
CPU time 62.11 seconds
Started Jan 07 01:40:47 PM PST 24
Finished Jan 07 01:42:15 PM PST 24
Peak memory 248592 kb
Host smart-8c7d3c46-40ef-42ef-b994-907ccb472349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19079
24 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1907924
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3313779299
Short name T105
Test name
Test status
Simulation time 176329668 ps
CPU time 10.97 seconds
Started Jan 07 01:40:59 PM PST 24
Finished Jan 07 01:41:27 PM PST 24
Peak memory 251944 kb
Host smart-f065a28e-5455-4f72-8ff4-eb22d3e0e29e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33137
79299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3313779299
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2709729019
Short name T700
Test name
Test status
Simulation time 39080765 ps
CPU time 4.28 seconds
Started Jan 07 01:40:46 PM PST 24
Finished Jan 07 01:41:16 PM PST 24
Peak memory 249156 kb
Host smart-4c6c5785-f699-45c3-b123-0c88e67f9205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27097
29019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2709729019
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.800884594
Short name T516
Test name
Test status
Simulation time 1936802779 ps
CPU time 32.37 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 01:41:37 PM PST 24
Peak memory 255268 kb
Host smart-b53eff8f-6c95-42e5-8107-30b2f0ee4c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80088
4594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.800884594
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.534796095
Short name T518
Test name
Test status
Simulation time 57988034252 ps
CPU time 1187.47 seconds
Started Jan 07 01:41:02 PM PST 24
Finished Jan 07 02:01:06 PM PST 24
Peak memory 288760 kb
Host smart-64a182ea-afee-4d2c-b038-81449f97ce7b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534796095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.534796095
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3316025575
Short name T497
Test name
Test status
Simulation time 10671906122 ps
CPU time 619.94 seconds
Started Jan 07 01:41:25 PM PST 24
Finished Jan 07 01:51:51 PM PST 24
Peak memory 267956 kb
Host smart-3e787fbd-a5c1-4cbd-bd20-41f4a3afde16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316025575 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3316025575
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3485180971
Short name T3
Test name
Test status
Simulation time 137947885115 ps
CPU time 2092.96 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 02:16:29 PM PST 24
Peak memory 283896 kb
Host smart-2ebb603d-877c-4af0-aaaf-eba106b91f47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485180971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3485180971
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.331574097
Short name T80
Test name
Test status
Simulation time 7735898720 ps
CPU time 149.1 seconds
Started Jan 07 01:41:03 PM PST 24
Finished Jan 07 01:43:49 PM PST 24
Peak memory 250752 kb
Host smart-63a7eb0a-37b8-4a71-8dd1-619ff9288566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33157
4097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.331574097
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.4210306706
Short name T530
Test name
Test status
Simulation time 747224988 ps
CPU time 44.1 seconds
Started Jan 07 01:40:47 PM PST 24
Finished Jan 07 01:41:57 PM PST 24
Peak memory 248208 kb
Host smart-0d6e70ea-f382-45cb-a447-ecd37b5a0574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42103
06706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.4210306706
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.964479247
Short name T455
Test name
Test status
Simulation time 20524265784 ps
CPU time 1158.11 seconds
Started Jan 07 01:40:53 PM PST 24
Finished Jan 07 02:00:34 PM PST 24
Peak memory 272964 kb
Host smart-0992336c-7931-48b0-83d2-1d165659265b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964479247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.964479247
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1824785159
Short name T334
Test name
Test status
Simulation time 91608675999 ps
CPU time 301.29 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:46:43 PM PST 24
Peak memory 247596 kb
Host smart-71cc4539-de33-4211-b686-a274194d3326
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824785159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1824785159
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2302308193
Short name T587
Test name
Test status
Simulation time 2130793679 ps
CPU time 34.31 seconds
Started Jan 07 01:41:03 PM PST 24
Finished Jan 07 01:41:53 PM PST 24
Peak memory 255164 kb
Host smart-b1ea7a82-aab4-42c8-bdbc-79fa67b1f901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23023
08193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2302308193
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.46465641
Short name T109
Test name
Test status
Simulation time 1211966500 ps
CPU time 26.94 seconds
Started Jan 07 01:41:27 PM PST 24
Finished Jan 07 01:41:59 PM PST 24
Peak memory 254740 kb
Host smart-bce75913-301b-40cb-8743-de54d2383380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46465
641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.46465641
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2241334550
Short name T23
Test name
Test status
Simulation time 504029964 ps
CPU time 31.92 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 01:42:08 PM PST 24
Peak memory 248628 kb
Host smart-a498f37d-22cd-4136-b76a-d48b107e590d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22413
34550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2241334550
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1848446463
Short name T734
Test name
Test status
Simulation time 13413510694 ps
CPU time 1139.26 seconds
Started Jan 07 01:41:32 PM PST 24
Finished Jan 07 02:00:38 PM PST 24
Peak memory 289088 kb
Host smart-7b7968c1-12f4-4080-af8e-af4970138c87
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848446463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1848446463
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.646167481
Short name T688
Test name
Test status
Simulation time 77898524587 ps
CPU time 4730.56 seconds
Started Jan 07 01:41:29 PM PST 24
Finished Jan 07 03:00:26 PM PST 24
Peak memory 314340 kb
Host smart-5119cb20-26ea-44f4-b4af-07724dc705c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646167481 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.646167481
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1185934989
Short name T75
Test name
Test status
Simulation time 60602138923 ps
CPU time 1946.36 seconds
Started Jan 07 01:41:06 PM PST 24
Finished Jan 07 02:13:48 PM PST 24
Peak memory 273044 kb
Host smart-205dabb2-c33e-472f-8970-8d36623c5bfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185934989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1185934989
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1890586584
Short name T395
Test name
Test status
Simulation time 635872927 ps
CPU time 38.54 seconds
Started Jan 07 01:41:32 PM PST 24
Finished Jan 07 01:42:17 PM PST 24
Peak memory 248620 kb
Host smart-5011da0e-da46-4757-b72e-09ed503dc62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18905
86584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1890586584
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4123319611
Short name T25
Test name
Test status
Simulation time 494331021 ps
CPU time 19.75 seconds
Started Jan 07 01:41:07 PM PST 24
Finished Jan 07 01:41:41 PM PST 24
Peak memory 254104 kb
Host smart-2730c09c-1174-4a91-9233-cba2471342e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41233
19611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4123319611
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3577661002
Short name T590
Test name
Test status
Simulation time 133926717490 ps
CPU time 1725.25 seconds
Started Jan 07 01:41:00 PM PST 24
Finished Jan 07 02:10:03 PM PST 24
Peak memory 272412 kb
Host smart-070303e6-bf14-4929-96d6-84376632c4b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577661002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3577661002
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2886662630
Short name T404
Test name
Test status
Simulation time 27147331889 ps
CPU time 1718.35 seconds
Started Jan 07 01:41:27 PM PST 24
Finished Jan 07 02:10:11 PM PST 24
Peak memory 288936 kb
Host smart-6b920271-8025-4a45-988d-6f8e4dbf5f22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886662630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2886662630
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2192680220
Short name T312
Test name
Test status
Simulation time 7698096934 ps
CPU time 309.16 seconds
Started Jan 07 01:41:05 PM PST 24
Finished Jan 07 01:46:29 PM PST 24
Peak memory 246336 kb
Host smart-94ea72b3-4856-442a-84e1-698c5a3a46b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192680220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2192680220
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.529884346
Short name T534
Test name
Test status
Simulation time 990547931 ps
CPU time 14.93 seconds
Started Jan 07 01:40:48 PM PST 24
Finished Jan 07 01:41:28 PM PST 24
Peak memory 248724 kb
Host smart-f74463f9-a0c9-4090-b591-217790cc7eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52988
4346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.529884346
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3443763944
Short name T574
Test name
Test status
Simulation time 241127386 ps
CPU time 20.25 seconds
Started Jan 07 01:41:10 PM PST 24
Finished Jan 07 01:41:42 PM PST 24
Peak memory 254724 kb
Host smart-16576d0e-32aa-4142-870d-0cb3ca91d6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34437
63944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3443763944
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3827154845
Short name T59
Test name
Test status
Simulation time 1000749785 ps
CPU time 28.4 seconds
Started Jan 07 01:41:32 PM PST 24
Finished Jan 07 01:42:07 PM PST 24
Peak memory 255464 kb
Host smart-820fffc5-3627-470b-80ac-e75262203cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38271
54845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3827154845
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1696709497
Short name T731
Test name
Test status
Simulation time 61743292 ps
CPU time 4.25 seconds
Started Jan 07 01:40:55 PM PST 24
Finished Jan 07 01:41:20 PM PST 24
Peak memory 248560 kb
Host smart-121a8a95-3fc0-495f-8d18-1c07c48936db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16967
09497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1696709497
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.324604336
Short name T670
Test name
Test status
Simulation time 61291583010 ps
CPU time 1060.74 seconds
Started Jan 07 01:40:56 PM PST 24
Finished Jan 07 01:58:56 PM PST 24
Peak memory 273088 kb
Host smart-f9aea149-798a-4200-90a3-f07bdaa5d154
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324604336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.324604336
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2762118420
Short name T49
Test name
Test status
Simulation time 1265573548 ps
CPU time 96.77 seconds
Started Jan 07 01:41:28 PM PST 24
Finished Jan 07 01:43:10 PM PST 24
Peak memory 256224 kb
Host smart-3d914745-20fa-4ece-9d33-fe3514db1034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27621
18420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2762118420
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.796556118
Short name T578
Test name
Test status
Simulation time 278644109 ps
CPU time 14.38 seconds
Started Jan 07 01:40:46 PM PST 24
Finished Jan 07 01:41:26 PM PST 24
Peak memory 247932 kb
Host smart-70c600ee-ffe7-42e1-80d7-aea8bb1ae976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79655
6118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.796556118
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.412848361
Short name T716
Test name
Test status
Simulation time 48269026779 ps
CPU time 2616.1 seconds
Started Jan 07 01:40:51 PM PST 24
Finished Jan 07 02:24:51 PM PST 24
Peak memory 285196 kb
Host smart-ee663d7a-0b0b-48d1-ba28-ddd3a289139a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412848361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.412848361
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1454075164
Short name T284
Test name
Test status
Simulation time 8665352664 ps
CPU time 731.81 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:53:53 PM PST 24
Peak memory 272776 kb
Host smart-a1b82847-63f8-44af-bfb0-364bdf782a69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454075164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1454075164
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2272134835
Short name T323
Test name
Test status
Simulation time 89365324882 ps
CPU time 455.99 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:49:17 PM PST 24
Peak memory 246820 kb
Host smart-f2ac7d5d-222f-4541-b208-7f54487835e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272134835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2272134835
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1050553465
Short name T217
Test name
Test status
Simulation time 324127323 ps
CPU time 28.17 seconds
Started Jan 07 01:41:02 PM PST 24
Finished Jan 07 01:41:47 PM PST 24
Peak memory 248660 kb
Host smart-e0f530bb-a983-4a99-8e99-53c8df5b5924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10505
53465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1050553465
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3874400126
Short name T384
Test name
Test status
Simulation time 392461811 ps
CPU time 13.89 seconds
Started Jan 07 01:41:29 PM PST 24
Finished Jan 07 01:41:48 PM PST 24
Peak memory 254300 kb
Host smart-9d4b5fdb-dc64-4d9e-9502-62e4bd098476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38744
00126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3874400126
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.137515077
Short name T668
Test name
Test status
Simulation time 805981414 ps
CPU time 25.65 seconds
Started Jan 07 01:40:48 PM PST 24
Finished Jan 07 01:41:39 PM PST 24
Peak memory 254908 kb
Host smart-f68f8ae9-c497-475c-97fe-f151f5b74657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13751
5077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.137515077
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2455457762
Short name T707
Test name
Test status
Simulation time 112172508 ps
CPU time 10.46 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 01:41:20 PM PST 24
Peak memory 248652 kb
Host smart-246f738f-0abc-40a8-8208-caa1e303bb2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24554
57762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2455457762
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1873316830
Short name T664
Test name
Test status
Simulation time 112601298 ps
CPU time 5.76 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:41:47 PM PST 24
Peak memory 240564 kb
Host smart-70323f90-0551-4146-ac57-a00d071a7452
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873316830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1873316830
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2628028057
Short name T676
Test name
Test status
Simulation time 106305089635 ps
CPU time 1547.07 seconds
Started Jan 07 01:41:03 PM PST 24
Finished Jan 07 02:07:06 PM PST 24
Peak memory 272768 kb
Host smart-b8726d52-1b71-4691-94a0-3e16f48349de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628028057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2628028057
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.522725907
Short name T459
Test name
Test status
Simulation time 448654571 ps
CPU time 8.04 seconds
Started Jan 07 01:41:05 PM PST 24
Finished Jan 07 01:41:29 PM PST 24
Peak memory 240208 kb
Host smart-4a442fce-b8b5-499e-84e0-0032750d6c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52272
5907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.522725907
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1214316819
Short name T431
Test name
Test status
Simulation time 832867745 ps
CPU time 41.97 seconds
Started Jan 07 01:41:07 PM PST 24
Finished Jan 07 01:42:03 PM PST 24
Peak memory 254708 kb
Host smart-4d64a86d-e18f-4a17-b7b4-73a55b544bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12143
16819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1214316819
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3699136939
Short name T342
Test name
Test status
Simulation time 75462818299 ps
CPU time 1456.53 seconds
Started Jan 07 01:41:32 PM PST 24
Finished Jan 07 02:05:55 PM PST 24
Peak memory 286388 kb
Host smart-c6a78215-4af0-4499-aade-4a267d774384
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699136939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3699136939
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2406149123
Short name T78
Test name
Test status
Simulation time 134876780315 ps
CPU time 2725.2 seconds
Started Jan 07 01:41:06 PM PST 24
Finished Jan 07 02:26:46 PM PST 24
Peak memory 289160 kb
Host smart-9a50573f-aba6-4178-84fd-a4df92b8b7fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406149123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2406149123
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3872313332
Short name T540
Test name
Test status
Simulation time 135917228 ps
CPU time 13.43 seconds
Started Jan 07 01:40:58 PM PST 24
Finished Jan 07 01:41:29 PM PST 24
Peak memory 248684 kb
Host smart-ed8bdfe2-3b42-49d3-b0bd-2ca7dfeb82e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38723
13332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3872313332
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2649057746
Short name T437
Test name
Test status
Simulation time 499779416 ps
CPU time 28.12 seconds
Started Jan 07 01:41:02 PM PST 24
Finished Jan 07 01:41:47 PM PST 24
Peak memory 254312 kb
Host smart-de9f383e-967d-4479-84ff-7d98e344caa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26490
57746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2649057746
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2428764742
Short name T571
Test name
Test status
Simulation time 3689171693 ps
CPU time 44.57 seconds
Started Jan 07 01:40:51 PM PST 24
Finished Jan 07 01:41:59 PM PST 24
Peak memory 255112 kb
Host smart-4539cd08-86a0-43b4-bc2d-1c80a06a80ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24287
64742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2428764742
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2652810795
Short name T641
Test name
Test status
Simulation time 1666721197 ps
CPU time 57.95 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 01:42:33 PM PST 24
Peak memory 248564 kb
Host smart-137760bc-6756-4fd5-8111-22e201cffb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26528
10795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2652810795
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3874810427
Short name T112
Test name
Test status
Simulation time 32709271135 ps
CPU time 1967.13 seconds
Started Jan 07 01:41:04 PM PST 24
Finished Jan 07 02:14:07 PM PST 24
Peak memory 287352 kb
Host smart-a20c88fa-cc32-431a-ba6e-df93fdf51d7e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874810427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3874810427
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3296920171
Short name T586
Test name
Test status
Simulation time 127117444370 ps
CPU time 1568.68 seconds
Started Jan 07 01:41:33 PM PST 24
Finished Jan 07 02:07:48 PM PST 24
Peak memory 273012 kb
Host smart-b0a620e3-133a-4a8c-94f7-fe4125060f25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296920171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3296920171
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1227605827
Short name T250
Test name
Test status
Simulation time 25500520957 ps
CPU time 145.39 seconds
Started Jan 07 01:41:25 PM PST 24
Finished Jan 07 01:43:56 PM PST 24
Peak memory 256884 kb
Host smart-9f6bae9f-2a33-4cf9-9629-38443e806808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12276
05827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1227605827
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.4266808784
Short name T444
Test name
Test status
Simulation time 845686369 ps
CPU time 24.1 seconds
Started Jan 07 01:41:26 PM PST 24
Finished Jan 07 01:41:55 PM PST 24
Peak memory 254148 kb
Host smart-a16f6016-857a-4e12-8cf4-86f2039856d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42668
08784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4266808784
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2146723062
Short name T652
Test name
Test status
Simulation time 27499605155 ps
CPU time 682.47 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:53:04 PM PST 24
Peak memory 265108 kb
Host smart-7be38e0a-5498-4474-9335-e69a26d7aadf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146723062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2146723062
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2843838431
Short name T614
Test name
Test status
Simulation time 15767873961 ps
CPU time 1354.46 seconds
Started Jan 07 01:41:44 PM PST 24
Finished Jan 07 02:04:33 PM PST 24
Peak memory 286544 kb
Host smart-ff1c39f8-8683-42e6-abfa-9f6c503197da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843838431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2843838431
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1534543264
Short name T213
Test name
Test status
Simulation time 818484972 ps
CPU time 12.74 seconds
Started Jan 07 01:41:31 PM PST 24
Finished Jan 07 01:41:50 PM PST 24
Peak memory 254460 kb
Host smart-a0a61d9a-5fad-48d8-bad3-6f8f45006ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15345
43264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1534543264
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1810115514
Short name T124
Test name
Test status
Simulation time 471157943 ps
CPU time 10.03 seconds
Started Jan 07 01:41:33 PM PST 24
Finished Jan 07 01:41:49 PM PST 24
Peak memory 248184 kb
Host smart-13c15fe4-c565-43b9-9cc6-9dd63a945eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18101
15514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1810115514
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2181551337
Short name T383
Test name
Test status
Simulation time 125235521 ps
CPU time 4.02 seconds
Started Jan 07 01:41:03 PM PST 24
Finished Jan 07 01:41:23 PM PST 24
Peak memory 250528 kb
Host smart-04ed07d5-675c-41c2-a1c4-6532fb42ab21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21815
51337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2181551337
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1000970597
Short name T517
Test name
Test status
Simulation time 242989548 ps
CPU time 10.52 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 01:41:46 PM PST 24
Peak memory 248708 kb
Host smart-990f3e5e-4aa5-4512-8b32-be8947068b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10009
70597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1000970597
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3637416428
Short name T706
Test name
Test status
Simulation time 442261888957 ps
CPU time 3433.78 seconds
Started Jan 07 01:41:33 PM PST 24
Finished Jan 07 02:38:53 PM PST 24
Peak memory 305688 kb
Host smart-226b01c1-8b6b-464f-b2c1-ef8a5553d487
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637416428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3637416428
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1547699853
Short name T90
Test name
Test status
Simulation time 175009017019 ps
CPU time 2842.59 seconds
Started Jan 07 01:41:55 PM PST 24
Finished Jan 07 02:29:28 PM PST 24
Peak memory 305808 kb
Host smart-47091840-1e28-4e27-882e-9394e04db371
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547699853 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1547699853
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3020049893
Short name T274
Test name
Test status
Simulation time 60988622976 ps
CPU time 1846.22 seconds
Started Jan 07 01:41:26 PM PST 24
Finished Jan 07 02:12:18 PM PST 24
Peak memory 269096 kb
Host smart-8450c5f2-1354-4e4c-a2a7-942f7ba319fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020049893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3020049893
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2444559102
Short name T573
Test name
Test status
Simulation time 9218953622 ps
CPU time 93.16 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 01:43:08 PM PST 24
Peak memory 248760 kb
Host smart-0cd4fff3-6f25-423d-8a8d-68697b681cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24445
59102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2444559102
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1324261635
Short name T599
Test name
Test status
Simulation time 89597024 ps
CPU time 10.25 seconds
Started Jan 07 01:41:31 PM PST 24
Finished Jan 07 01:41:48 PM PST 24
Peak memory 254084 kb
Host smart-efde0a8f-6cb9-487e-b872-8a188efa74e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13242
61635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1324261635
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1386915357
Short name T338
Test name
Test status
Simulation time 199661682866 ps
CPU time 1596.18 seconds
Started Jan 07 01:41:52 PM PST 24
Finished Jan 07 02:08:40 PM PST 24
Peak memory 289184 kb
Host smart-761ccca0-2230-4cce-8f23-2929565e96e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386915357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1386915357
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1758321370
Short name T405
Test name
Test status
Simulation time 38708036435 ps
CPU time 2192.41 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 02:18:42 PM PST 24
Peak memory 273052 kb
Host smart-ea8ab24f-7370-4a8a-ad3a-4fcc5478a7a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758321370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1758321370
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.601654281
Short name T510
Test name
Test status
Simulation time 4381514830 ps
CPU time 173 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 01:44:38 PM PST 24
Peak memory 248632 kb
Host smart-e5ff81cc-1f1d-4d0f-8cfd-029b3e412910
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601654281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.601654281
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.906381106
Short name T484
Test name
Test status
Simulation time 464143634 ps
CPU time 35.93 seconds
Started Jan 07 01:41:40 PM PST 24
Finished Jan 07 01:42:30 PM PST 24
Peak memory 255320 kb
Host smart-826e168c-9712-4967-874a-ca8eb271da6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90638
1106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.906381106
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2182432964
Short name T22
Test name
Test status
Simulation time 636682816 ps
CPU time 14.83 seconds
Started Jan 07 01:41:32 PM PST 24
Finished Jan 07 01:41:53 PM PST 24
Peak memory 255032 kb
Host smart-28204f3d-9e38-483e-b54e-dac090eb1d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21824
32964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2182432964
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3520914293
Short name T2
Test name
Test status
Simulation time 60953800 ps
CPU time 2.8 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 01:42:12 PM PST 24
Peak memory 238696 kb
Host smart-f8a296c5-d8ee-4591-8bf9-8257e0c17fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35209
14293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3520914293
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.690550314
Short name T493
Test name
Test status
Simulation time 2802614280 ps
CPU time 30.57 seconds
Started Jan 07 01:41:35 PM PST 24
Finished Jan 07 01:42:14 PM PST 24
Peak memory 248756 kb
Host smart-8ebe5558-3238-4a32-a8a1-012f03e3f27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69055
0314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.690550314
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1883258581
Short name T309
Test name
Test status
Simulation time 12137141987 ps
CPU time 918.19 seconds
Started Jan 07 01:41:54 PM PST 24
Finished Jan 07 01:57:23 PM PST 24
Peak memory 282912 kb
Host smart-88defaf4-ec68-408b-b805-adbb07cde331
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883258581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1883258581
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.733476322
Short name T264
Test name
Test status
Simulation time 1400880961 ps
CPU time 116.64 seconds
Started Jan 07 01:41:59 PM PST 24
Finished Jan 07 01:44:05 PM PST 24
Peak memory 256192 kb
Host smart-cce6683c-6f0e-4ad1-95b4-2910502b76f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73347
6322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.733476322
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.4142883518
Short name T665
Test name
Test status
Simulation time 978814991 ps
CPU time 55.18 seconds
Started Jan 07 01:41:33 PM PST 24
Finished Jan 07 01:42:34 PM PST 24
Peak memory 248604 kb
Host smart-7c8e3c6c-f9a8-4c1a-822a-f84af0d994d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41428
83518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.4142883518
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.199696299
Short name T689
Test name
Test status
Simulation time 141508393673 ps
CPU time 2004.79 seconds
Started Jan 07 01:42:26 PM PST 24
Finished Jan 07 02:16:10 PM PST 24
Peak memory 272772 kb
Host smart-7b9c9b6c-db64-4ded-8afc-6a0cb4943e08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199696299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.199696299
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.4011994579
Short name T227
Test name
Test status
Simulation time 221531507546 ps
CPU time 1305.32 seconds
Started Jan 07 01:43:00 PM PST 24
Finished Jan 07 02:05:01 PM PST 24
Peak memory 272956 kb
Host smart-20b303f6-72d7-434f-999b-6dff120192b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011994579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.4011994579
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.324408083
Short name T488
Test name
Test status
Simulation time 24029678046 ps
CPU time 207.8 seconds
Started Jan 07 01:42:15 PM PST 24
Finished Jan 07 01:45:52 PM PST 24
Peak memory 247292 kb
Host smart-2abe7b30-f96b-4d3e-8208-c76836935984
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324408083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.324408083
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2335808810
Short name T397
Test name
Test status
Simulation time 1074339648 ps
CPU time 28.02 seconds
Started Jan 07 01:41:40 PM PST 24
Finished Jan 07 01:42:22 PM PST 24
Peak memory 248592 kb
Host smart-33026336-c876-4300-bc2f-4de4c8f08923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23358
08810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2335808810
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1488990913
Short name T603
Test name
Test status
Simulation time 215227279 ps
CPU time 18.11 seconds
Started Jan 07 01:41:38 PM PST 24
Finished Jan 07 01:42:09 PM PST 24
Peak memory 255392 kb
Host smart-b8685dc6-3fac-4bd7-90ae-ee314848abd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14889
90913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1488990913
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1744356014
Short name T394
Test name
Test status
Simulation time 3443022304 ps
CPU time 19.49 seconds
Started Jan 07 01:42:05 PM PST 24
Finished Jan 07 01:42:34 PM PST 24
Peak memory 248664 kb
Host smart-4e9e9778-4109-40b0-a065-7a82dfc0f80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17443
56014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1744356014
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1309316429
Short name T228
Test name
Test status
Simulation time 231200201 ps
CPU time 6.32 seconds
Started Jan 07 01:41:35 PM PST 24
Finished Jan 07 01:41:49 PM PST 24
Peak memory 248624 kb
Host smart-7c5888a0-8706-47fe-a28d-91b1328889b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13093
16429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1309316429
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.985780046
Short name T522
Test name
Test status
Simulation time 7216749389 ps
CPU time 419.26 seconds
Started Jan 07 01:42:17 PM PST 24
Finished Jan 07 01:49:31 PM PST 24
Peak memory 255252 kb
Host smart-7629bfdd-1d95-4a87-90e1-2b02a075d1b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985780046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.985780046
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2441498553
Short name T292
Test name
Test status
Simulation time 83613815565 ps
CPU time 4625.11 seconds
Started Jan 07 01:42:30 PM PST 24
Finished Jan 07 02:59:52 PM PST 24
Peak memory 305468 kb
Host smart-cbb2766e-fe91-486d-b7f6-800037b0ba39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441498553 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2441498553
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.196974854
Short name T418
Test name
Test status
Simulation time 28566337122 ps
CPU time 1089.36 seconds
Started Jan 07 01:42:41 PM PST 24
Finished Jan 07 02:01:10 PM PST 24
Peak memory 281532 kb
Host smart-0150430b-b2bb-4e26-ae0b-f41cc55f56b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196974854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.196974854
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1061817311
Short name T409
Test name
Test status
Simulation time 1421171009 ps
CPU time 79.07 seconds
Started Jan 07 01:42:38 PM PST 24
Finished Jan 07 01:44:18 PM PST 24
Peak memory 256152 kb
Host smart-4c6ad7ac-6fe7-4e6d-942d-5747d5d3de30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10618
17311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1061817311
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.934001192
Short name T621
Test name
Test status
Simulation time 4978891672 ps
CPU time 29.59 seconds
Started Jan 07 01:42:25 PM PST 24
Finished Jan 07 01:43:13 PM PST 24
Peak memory 248696 kb
Host smart-79c8c94f-9089-4bfc-846b-07f97d016261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93400
1192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.934001192
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2699796767
Short name T696
Test name
Test status
Simulation time 103654073846 ps
CPU time 1389.13 seconds
Started Jan 07 01:42:36 PM PST 24
Finished Jan 07 02:06:05 PM PST 24
Peak memory 265072 kb
Host smart-b70117f9-5683-4316-8a50-d12c9648eaee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699796767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2699796767
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.4121644167
Short name T8
Test name
Test status
Simulation time 20928837692 ps
CPU time 210.43 seconds
Started Jan 07 01:42:33 PM PST 24
Finished Jan 07 01:46:18 PM PST 24
Peak memory 247588 kb
Host smart-22b851da-b59f-4ae5-bb78-2e8d782f75de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121644167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4121644167
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1402552439
Short name T509
Test name
Test status
Simulation time 285714926 ps
CPU time 22.4 seconds
Started Jan 07 01:43:12 PM PST 24
Finished Jan 07 01:43:48 PM PST 24
Peak memory 255384 kb
Host smart-72757806-ee1c-4f9b-8578-6fb486d27aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14025
52439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1402552439
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3451256264
Short name T566
Test name
Test status
Simulation time 655779817 ps
CPU time 28.53 seconds
Started Jan 07 01:42:15 PM PST 24
Finished Jan 07 01:42:53 PM PST 24
Peak memory 248264 kb
Host smart-7fb209a8-8f06-4dad-8d78-7dfe7eca995f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34512
56264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3451256264
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3509164131
Short name T295
Test name
Test status
Simulation time 5562731125 ps
CPU time 60.69 seconds
Started Jan 07 01:42:23 PM PST 24
Finished Jan 07 01:43:39 PM PST 24
Peak memory 256032 kb
Host smart-9d0d3a4f-5ab7-42a5-890d-0be90f3f50bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35091
64131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3509164131
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2902697030
Short name T392
Test name
Test status
Simulation time 1132600585 ps
CPU time 19.29 seconds
Started Jan 07 01:42:10 PM PST 24
Finished Jan 07 01:42:38 PM PST 24
Peak memory 248760 kb
Host smart-039d7b20-6857-460d-a104-2e62d7a1953b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29026
97030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2902697030
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.550525943
Short name T589
Test name
Test status
Simulation time 75137886804 ps
CPU time 1080.78 seconds
Started Jan 07 01:41:00 PM PST 24
Finished Jan 07 01:59:18 PM PST 24
Peak memory 272084 kb
Host smart-4bcd3ff9-d8fc-4b6d-b086-386d08ffbeac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550525943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.550525943
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.4207279797
Short name T723
Test name
Test status
Simulation time 133668230 ps
CPU time 3.77 seconds
Started Jan 07 01:41:23 PM PST 24
Finished Jan 07 01:41:32 PM PST 24
Peak memory 239532 kb
Host smart-2f0a0dbe-4944-4986-a1c6-967f4368ea80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42072
79797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.4207279797
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.8904732
Short name T640
Test name
Test status
Simulation time 742688314 ps
CPU time 16.87 seconds
Started Jan 07 01:41:25 PM PST 24
Finished Jan 07 01:41:48 PM PST 24
Peak memory 248492 kb
Host smart-5e86ed2e-f36d-4923-8640-66bf7eae751a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89047
32 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.8904732
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1332158338
Short name T54
Test name
Test status
Simulation time 108433149768 ps
CPU time 1691.05 seconds
Started Jan 07 01:41:19 PM PST 24
Finished Jan 07 02:09:37 PM PST 24
Peak memory 273228 kb
Host smart-393fc960-cf83-4cb7-99e9-146001a15ae4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332158338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1332158338
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1617936122
Short name T460
Test name
Test status
Simulation time 27754662889 ps
CPU time 635.39 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:52:17 PM PST 24
Peak memory 273292 kb
Host smart-fa7e14c0-ae5b-4458-ab38-fa6ea20c4d37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617936122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1617936122
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3905056725
Short name T642
Test name
Test status
Simulation time 427849502 ps
CPU time 32.22 seconds
Started Jan 07 01:41:29 PM PST 24
Finished Jan 07 01:42:07 PM PST 24
Peak memory 248600 kb
Host smart-0b1eb6f4-9e7e-47e3-99cc-908bd3ece8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39050
56725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3905056725
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1008166257
Short name T722
Test name
Test status
Simulation time 3651226036 ps
CPU time 18.4 seconds
Started Jan 07 01:40:59 PM PST 24
Finished Jan 07 01:41:35 PM PST 24
Peak memory 255620 kb
Host smart-6045aa1f-45dc-41e7-ba3c-4dff993177cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10081
66257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1008166257
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.219653349
Short name T101
Test name
Test status
Simulation time 3034875031 ps
CPU time 43.77 seconds
Started Jan 07 01:41:24 PM PST 24
Finished Jan 07 01:42:17 PM PST 24
Peak memory 254836 kb
Host smart-5c9b12f8-3cf3-4305-ad55-86104bc08fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21965
3349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.219653349
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3866886495
Short name T226
Test name
Test status
Simulation time 3344695974 ps
CPU time 45.27 seconds
Started Jan 07 01:41:20 PM PST 24
Finished Jan 07 01:42:11 PM PST 24
Peak memory 248732 kb
Host smart-d29b206b-7527-40d3-98dd-40c551037f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38668
86495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3866886495
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2327890731
Short name T110
Test name
Test status
Simulation time 17092087732 ps
CPU time 403.78 seconds
Started Jan 07 01:41:33 PM PST 24
Finished Jan 07 01:48:23 PM PST 24
Peak memory 265012 kb
Host smart-0899cc11-d5f0-424a-a4bc-d4b0fb184553
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327890731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2327890731
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1512160239
Short name T503
Test name
Test status
Simulation time 3801023999 ps
CPU time 385.16 seconds
Started Jan 07 01:41:06 PM PST 24
Finished Jan 07 01:47:46 PM PST 24
Peak memory 268352 kb
Host smart-6706f640-af78-430a-955a-4cdf01b8cd67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512160239 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1512160239
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3806194788
Short name T203
Test name
Test status
Simulation time 39108688 ps
CPU time 2.27 seconds
Started Jan 07 01:40:27 PM PST 24
Finished Jan 07 01:40:52 PM PST 24
Peak memory 248792 kb
Host smart-9f8087f9-bca5-4159-9e31-c812a88012b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3806194788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3806194788
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.4011045602
Short name T407
Test name
Test status
Simulation time 71155682663 ps
CPU time 2197 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 02:17:42 PM PST 24
Peak memory 289488 kb
Host smart-0765f2a4-24e1-458a-a82a-27731dd165a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011045602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.4011045602
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1005879332
Short name T220
Test name
Test status
Simulation time 2560586050 ps
CPU time 61.33 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:42:09 PM PST 24
Peak memory 240448 kb
Host smart-c71b499b-ac72-4cf1-94d3-597ca519c342
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1005879332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1005879332
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3278945374
Short name T561
Test name
Test status
Simulation time 979796943 ps
CPU time 28.82 seconds
Started Jan 07 01:40:36 PM PST 24
Finished Jan 07 01:41:31 PM PST 24
Peak memory 256132 kb
Host smart-ab54c193-9475-41da-b93b-b05c0c36e570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32789
45374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3278945374
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.977961375
Short name T93
Test name
Test status
Simulation time 3247586844 ps
CPU time 31.35 seconds
Started Jan 07 01:40:26 PM PST 24
Finished Jan 07 01:41:20 PM PST 24
Peak memory 247216 kb
Host smart-69196ee6-e488-4937-aa34-d92a824515fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97796
1375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.977961375
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.8470600
Short name T483
Test name
Test status
Simulation time 55476515072 ps
CPU time 3166.67 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 02:33:52 PM PST 24
Peak memory 288648 kb
Host smart-b0949aa5-b087-4a0a-a82f-15f38738ea33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8470600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.8470600
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.138118819
Short name T335
Test name
Test status
Simulation time 10843639247 ps
CPU time 452.02 seconds
Started Jan 07 01:40:36 PM PST 24
Finished Jan 07 01:48:35 PM PST 24
Peak memory 247316 kb
Host smart-35e90cf5-392c-4a50-8ea5-deb9a320d5a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138118819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.138118819
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1137443452
Short name T577
Test name
Test status
Simulation time 956379627 ps
CPU time 50.65 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 01:41:54 PM PST 24
Peak memory 248676 kb
Host smart-da85d124-0a94-46ff-bf82-5527f4f1bb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11374
43452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1137443452
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2175619247
Short name T72
Test name
Test status
Simulation time 504434633 ps
CPU time 26.4 seconds
Started Jan 07 01:40:21 PM PST 24
Finished Jan 07 01:41:12 PM PST 24
Peak memory 254184 kb
Host smart-c82b0b25-efab-47c2-8ccb-0d2f12eb9c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21756
19247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2175619247
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3228608429
Short name T12
Test name
Test status
Simulation time 847780126 ps
CPU time 13.29 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 01:41:13 PM PST 24
Peak memory 277884 kb
Host smart-7d659100-32a4-49f8-a5b7-b3747dd0dee3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3228608429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3228608429
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1529063695
Short name T57
Test name
Test status
Simulation time 910057833 ps
CPU time 33.01 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:41:40 PM PST 24
Peak memory 248548 kb
Host smart-c58856b7-2a4b-4273-8709-6df3b6e2f6fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15290
63695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1529063695
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.588593968
Short name T406
Test name
Test status
Simulation time 62153299 ps
CPU time 7.42 seconds
Started Jan 07 01:40:31 PM PST 24
Finished Jan 07 01:41:04 PM PST 24
Peak memory 248700 kb
Host smart-acf43ed1-6576-4ff1-96fd-11bd99f308f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58859
3968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.588593968
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2969562176
Short name T36
Test name
Test status
Simulation time 75719759193 ps
CPU time 510.74 seconds
Started Jan 07 01:40:30 PM PST 24
Finished Jan 07 01:49:27 PM PST 24
Peak memory 256868 kb
Host smart-fe8df033-acd9-4243-8594-60d3a3c2a248
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969562176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2969562176
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.2997442278
Short name T634
Test name
Test status
Simulation time 149097890656 ps
CPU time 3406.95 seconds
Started Jan 07 01:40:29 PM PST 24
Finished Jan 07 02:37:42 PM PST 24
Peak memory 305716 kb
Host smart-4bb2f533-49bf-4f32-a562-943ec7f81239
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997442278 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2997442278
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.935287213
Short name T512
Test name
Test status
Simulation time 249491515340 ps
CPU time 1374.9 seconds
Started Jan 07 01:41:07 PM PST 24
Finished Jan 07 02:04:16 PM PST 24
Peak memory 266064 kb
Host smart-a2d74f58-9b61-416f-8729-303adcd8e175
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935287213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.935287213
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1908905135
Short name T543
Test name
Test status
Simulation time 828170473 ps
CPU time 62.65 seconds
Started Jan 07 01:41:27 PM PST 24
Finished Jan 07 01:42:35 PM PST 24
Peak memory 255924 kb
Host smart-e28e6d45-c9ef-456b-866f-3287541fec7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19089
05135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1908905135
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.975071335
Short name T610
Test name
Test status
Simulation time 577464236 ps
CPU time 20.47 seconds
Started Jan 07 01:41:23 PM PST 24
Finished Jan 07 01:41:49 PM PST 24
Peak memory 255036 kb
Host smart-d065025a-0894-4c11-bebc-31300cee6708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97507
1335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.975071335
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1287287558
Short name T339
Test name
Test status
Simulation time 247049460874 ps
CPU time 2685.66 seconds
Started Jan 07 01:41:21 PM PST 24
Finished Jan 07 02:26:13 PM PST 24
Peak memory 288236 kb
Host smart-f0e5410f-330f-4875-a282-9cf42fb102df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287287558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1287287558
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2356210587
Short name T267
Test name
Test status
Simulation time 87474972057 ps
CPU time 1256.07 seconds
Started Jan 07 01:40:55 PM PST 24
Finished Jan 07 02:02:12 PM PST 24
Peak memory 272780 kb
Host smart-f3cb9473-6a18-49ce-87e9-deae50158208
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356210587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2356210587
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3405912322
Short name T48
Test name
Test status
Simulation time 86267640252 ps
CPU time 390.27 seconds
Started Jan 07 01:41:24 PM PST 24
Finished Jan 07 01:47:59 PM PST 24
Peak memory 247508 kb
Host smart-ada790aa-6213-41c0-b491-16b52e92c42a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405912322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3405912322
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3786818439
Short name T99
Test name
Test status
Simulation time 305361643 ps
CPU time 17.57 seconds
Started Jan 07 01:41:23 PM PST 24
Finished Jan 07 01:41:45 PM PST 24
Peak memory 248672 kb
Host smart-1043984b-49ed-4ead-9fb4-db8dfb3afdf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37868
18439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3786818439
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1850006514
Short name T389
Test name
Test status
Simulation time 235333714 ps
CPU time 16.18 seconds
Started Jan 07 01:41:28 PM PST 24
Finished Jan 07 01:41:50 PM PST 24
Peak memory 253512 kb
Host smart-581cf42e-5bdb-4a33-a465-ab5e02327944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18500
06514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1850006514
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2767695778
Short name T502
Test name
Test status
Simulation time 316631417 ps
CPU time 17.59 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:41:59 PM PST 24
Peak memory 248572 kb
Host smart-ea782ebe-330c-49eb-a554-2ac4e512b417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27676
95778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2767695778
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2105035713
Short name T582
Test name
Test status
Simulation time 1222937344 ps
CPU time 32.21 seconds
Started Jan 07 01:40:59 PM PST 24
Finished Jan 07 01:41:49 PM PST 24
Peak memory 248524 kb
Host smart-d5ca9ed4-eab0-4d22-897a-9c88ab5b2bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21050
35713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2105035713
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.698333346
Short name T95
Test name
Test status
Simulation time 39418790924 ps
CPU time 3166.87 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 02:34:32 PM PST 24
Peak memory 289516 kb
Host smart-4a80b402-b685-415b-8483-eea0b06ec73b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698333346 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.698333346
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1131727783
Short name T732
Test name
Test status
Simulation time 19831136013 ps
CPU time 1280.66 seconds
Started Jan 07 01:41:21 PM PST 24
Finished Jan 07 02:02:47 PM PST 24
Peak memory 273196 kb
Host smart-5fe520ca-d0dd-4d51-a9d3-d43537128abc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131727783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1131727783
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.4218683556
Short name T453
Test name
Test status
Simulation time 17625734831 ps
CPU time 278 seconds
Started Jan 07 01:41:40 PM PST 24
Finished Jan 07 01:46:32 PM PST 24
Peak memory 256480 kb
Host smart-6b790983-1af3-459d-876a-b60ca54e00de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42186
83556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.4218683556
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2331634643
Short name T666
Test name
Test status
Simulation time 253821162 ps
CPU time 26.2 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:42:07 PM PST 24
Peak memory 254708 kb
Host smart-b242d37c-6b02-4716-944a-8300ee5e4985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23316
34643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2331634643
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2426805170
Short name T358
Test name
Test status
Simulation time 59575416226 ps
CPU time 1847.24 seconds
Started Jan 07 01:41:01 PM PST 24
Finished Jan 07 02:12:05 PM PST 24
Peak memory 282060 kb
Host smart-fb4b1dcd-d8dd-451b-8e10-9981aa0fef1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426805170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2426805170
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2932023363
Short name T5
Test name
Test status
Simulation time 5959644339 ps
CPU time 680.53 seconds
Started Jan 07 01:41:31 PM PST 24
Finished Jan 07 01:52:58 PM PST 24
Peak memory 272868 kb
Host smart-8fee0640-55fa-43b1-836c-34185cf17794
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932023363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2932023363
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.512309823
Short name T326
Test name
Test status
Simulation time 44065692225 ps
CPU time 478.85 seconds
Started Jan 07 01:41:26 PM PST 24
Finished Jan 07 01:49:30 PM PST 24
Peak memory 248660 kb
Host smart-706eff53-64ba-4252-97fd-fe45613b212b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512309823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.512309823
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1056622705
Short name T413
Test name
Test status
Simulation time 51527282 ps
CPU time 3.02 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:41:44 PM PST 24
Peak memory 240476 kb
Host smart-be672eed-eaef-457a-b074-8a4a0190a814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10566
22705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1056622705
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.518409684
Short name T280
Test name
Test status
Simulation time 514678459 ps
CPU time 12.25 seconds
Started Jan 07 01:41:31 PM PST 24
Finished Jan 07 01:41:50 PM PST 24
Peak memory 248580 kb
Host smart-5a983a74-edd9-46c0-beeb-6d9dbec06cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51840
9684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.518409684
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2818057678
Short name T412
Test name
Test status
Simulation time 1925465961 ps
CPU time 52.8 seconds
Started Jan 07 01:41:04 PM PST 24
Finished Jan 07 01:42:13 PM PST 24
Peak memory 255220 kb
Host smart-df31d059-b3ff-44f6-aea5-89c86215a37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28180
57678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2818057678
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2784100159
Short name T585
Test name
Test status
Simulation time 555556472 ps
CPU time 31.41 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 01:42:08 PM PST 24
Peak memory 248652 kb
Host smart-4403baed-8c31-4b52-8e70-4960899b8095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27841
00159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2784100159
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2889383179
Short name T278
Test name
Test status
Simulation time 58825113604 ps
CPU time 1287 seconds
Started Jan 07 01:41:23 PM PST 24
Finished Jan 07 02:02:56 PM PST 24
Peak memory 289620 kb
Host smart-9d0f5390-355b-47c5-a208-53d489379501
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889383179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2889383179
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2024325662
Short name T265
Test name
Test status
Simulation time 16527096723 ps
CPU time 1503.59 seconds
Started Jan 07 01:41:25 PM PST 24
Finished Jan 07 02:06:35 PM PST 24
Peak memory 297520 kb
Host smart-c447dec8-4db1-4ed6-ab21-717bb285bbc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024325662 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2024325662
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.847115467
Short name T476
Test name
Test status
Simulation time 257777667308 ps
CPU time 2665.14 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 02:26:07 PM PST 24
Peak memory 288884 kb
Host smart-2be47455-821a-4611-87de-54d1c4a13785
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847115467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.847115467
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2270976957
Short name T224
Test name
Test status
Simulation time 7996294064 ps
CPU time 117.81 seconds
Started Jan 07 01:41:35 PM PST 24
Finished Jan 07 01:43:42 PM PST 24
Peak memory 249824 kb
Host smart-96aeefbf-b603-42de-badc-9ca6c82a65bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22709
76957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2270976957
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.4149256774
Short name T524
Test name
Test status
Simulation time 323647980 ps
CPU time 19.16 seconds
Started Jan 07 01:41:32 PM PST 24
Finished Jan 07 01:41:57 PM PST 24
Peak memory 254316 kb
Host smart-a2a29c63-bd26-4626-814b-82bd74bc8fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41492
56774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.4149256774
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.4218869827
Short name T341
Test name
Test status
Simulation time 127413527833 ps
CPU time 1277.4 seconds
Started Jan 07 01:41:04 PM PST 24
Finished Jan 07 02:02:37 PM PST 24
Peak memory 284608 kb
Host smart-19fb92da-13db-4807-81ff-aa717a307de4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218869827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4218869827
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3692848239
Short name T576
Test name
Test status
Simulation time 159537025306 ps
CPU time 2151.26 seconds
Started Jan 07 01:40:58 PM PST 24
Finished Jan 07 02:17:08 PM PST 24
Peak memory 288608 kb
Host smart-52bf5a01-662c-424a-829f-9c71dc678a89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692848239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3692848239
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.17889355
Short name T719
Test name
Test status
Simulation time 2567432557 ps
CPU time 16.51 seconds
Started Jan 07 01:41:35 PM PST 24
Finished Jan 07 01:42:00 PM PST 24
Peak memory 248644 kb
Host smart-cc7bc7cf-0348-4cd5-bf65-4c31973aa973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17889
355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.17889355
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3708549961
Short name T223
Test name
Test status
Simulation time 2885465468 ps
CPU time 38.36 seconds
Started Jan 07 01:41:03 PM PST 24
Finished Jan 07 01:41:58 PM PST 24
Peak memory 247204 kb
Host smart-4ff69b7b-f09b-41a2-8984-4772faf5cb66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37085
49961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3708549961
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2703977131
Short name T414
Test name
Test status
Simulation time 916198590 ps
CPU time 25.76 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 01:42:01 PM PST 24
Peak memory 247052 kb
Host smart-ed07fbda-bfda-4e49-9609-170046f5989a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27039
77131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2703977131
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.247223029
Short name T489
Test name
Test status
Simulation time 245198580 ps
CPU time 20.48 seconds
Started Jan 07 01:41:03 PM PST 24
Finished Jan 07 01:41:40 PM PST 24
Peak memory 248780 kb
Host smart-000ca88e-3a60-46c2-945f-a0a14f36872b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24722
3029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.247223029
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2413372891
Short name T718
Test name
Test status
Simulation time 119254143554 ps
CPU time 1863.01 seconds
Started Jan 07 01:41:24 PM PST 24
Finished Jan 07 02:12:33 PM PST 24
Peak memory 283040 kb
Host smart-78523b10-6cd8-4e4d-943b-71b10a9bb470
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413372891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2413372891
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.926470409
Short name T244
Test name
Test status
Simulation time 298465640749 ps
CPU time 4454.83 seconds
Started Jan 07 01:41:26 PM PST 24
Finished Jan 07 02:55:47 PM PST 24
Peak memory 297756 kb
Host smart-85d54bcf-6a52-4878-bd9d-537a560219cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926470409 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.926470409
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2269712611
Short name T694
Test name
Test status
Simulation time 26459158829 ps
CPU time 1571.94 seconds
Started Jan 07 01:41:23 PM PST 24
Finished Jan 07 02:07:40 PM PST 24
Peak memory 273116 kb
Host smart-0ad90b92-ebb8-45a7-9a35-e57151c0a1b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269712611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2269712611
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3731168496
Short name T85
Test name
Test status
Simulation time 3458968222 ps
CPU time 38.44 seconds
Started Jan 07 01:41:22 PM PST 24
Finished Jan 07 01:42:05 PM PST 24
Peak memory 255432 kb
Host smart-1e323673-afbb-4434-8c6f-4be88c95177c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37311
68496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3731168496
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1934546413
Short name T563
Test name
Test status
Simulation time 58554419213 ps
CPU time 3271.33 seconds
Started Jan 07 01:41:33 PM PST 24
Finished Jan 07 02:36:11 PM PST 24
Peak memory 288704 kb
Host smart-42314764-de2e-45f9-ae2f-b33e2378b40c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934546413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1934546413
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.4028278688
Short name T285
Test name
Test status
Simulation time 158597965058 ps
CPU time 875.67 seconds
Started Jan 07 01:41:08 PM PST 24
Finished Jan 07 01:55:57 PM PST 24
Peak memory 272084 kb
Host smart-5e67e529-61ea-4044-bcc2-f4ca86c845d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028278688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.4028278688
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.922890022
Short name T269
Test name
Test status
Simulation time 48380962764 ps
CPU time 371.35 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:47:54 PM PST 24
Peak memory 246640 kb
Host smart-91676cc4-15dd-4067-b4b0-38355ecd7cf1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922890022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.922890022
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1151865578
Short name T24
Test name
Test status
Simulation time 246915139 ps
CPU time 25.83 seconds
Started Jan 07 01:41:27 PM PST 24
Finished Jan 07 01:41:58 PM PST 24
Peak memory 255448 kb
Host smart-80fdf96a-7567-4cf2-977a-c370c136147d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11518
65578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1151865578
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.143312950
Short name T678
Test name
Test status
Simulation time 424355652 ps
CPU time 24.57 seconds
Started Jan 07 01:41:32 PM PST 24
Finished Jan 07 01:42:03 PM PST 24
Peak memory 255492 kb
Host smart-fc75ecab-62e1-42f8-8a03-7ed564be0821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14331
2950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.143312950
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2872963663
Short name T300
Test name
Test status
Simulation time 2792406202 ps
CPU time 28.01 seconds
Started Jan 07 01:41:07 PM PST 24
Finished Jan 07 01:41:49 PM PST 24
Peak memory 255120 kb
Host smart-2d5dbf57-f895-44ce-9d7b-3a42e2246c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28729
63663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2872963663
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.59016681
Short name T451
Test name
Test status
Simulation time 175461576 ps
CPU time 12.15 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:41:54 PM PST 24
Peak memory 248568 kb
Host smart-7bc16142-df85-4693-be94-f1bf5d377144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59016
681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.59016681
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.4191009641
Short name T391
Test name
Test status
Simulation time 71925111179 ps
CPU time 734.7 seconds
Started Jan 07 01:41:21 PM PST 24
Finished Jan 07 01:53:42 PM PST 24
Peak memory 265252 kb
Host smart-51896907-846c-4485-973d-2defcfd12f66
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191009641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.4191009641
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.799123702
Short name T214
Test name
Test status
Simulation time 1087982316444 ps
CPU time 5670.7 seconds
Started Jan 07 01:41:26 PM PST 24
Finished Jan 07 03:16:03 PM PST 24
Peak memory 322456 kb
Host smart-d0fff7a5-cd08-4730-a391-1629aa73d6da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799123702 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.799123702
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.242961415
Short name T100
Test name
Test status
Simulation time 31910120340 ps
CPU time 1929.68 seconds
Started Jan 07 01:41:40 PM PST 24
Finished Jan 07 02:14:05 PM PST 24
Peak memory 287348 kb
Host smart-0ee7d172-6849-451e-8683-8ac7887b3abd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242961415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.242961415
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1920173051
Short name T619
Test name
Test status
Simulation time 569588155 ps
CPU time 46.89 seconds
Started Jan 07 01:41:33 PM PST 24
Finished Jan 07 01:42:26 PM PST 24
Peak memory 248576 kb
Host smart-888e284f-dd48-43f8-baa2-9ccde521ebaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19201
73051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1920173051
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1655920894
Short name T429
Test name
Test status
Simulation time 2700494587 ps
CPU time 39.2 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 01:42:24 PM PST 24
Peak memory 254916 kb
Host smart-086470cd-e889-4d48-befe-a00a6a5072c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16559
20894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1655920894
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1606679927
Short name T15
Test name
Test status
Simulation time 76519750395 ps
CPU time 1291.63 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 02:03:17 PM PST 24
Peak memory 287584 kb
Host smart-a8ce8bda-4deb-4307-b836-ac6b2d956812
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606679927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1606679927
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2344903311
Short name T651
Test name
Test status
Simulation time 369341089 ps
CPU time 30.1 seconds
Started Jan 07 01:41:40 PM PST 24
Finished Jan 07 01:42:24 PM PST 24
Peak memory 248676 kb
Host smart-f06262b5-3528-4a9f-97a6-e68966fe55e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23449
03311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2344903311
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.618025463
Short name T473
Test name
Test status
Simulation time 914452068 ps
CPU time 48.16 seconds
Started Jan 07 01:41:04 PM PST 24
Finished Jan 07 01:42:08 PM PST 24
Peak memory 255368 kb
Host smart-d32c93ca-876d-4bd4-b4ef-ba764e82b761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61802
5463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.618025463
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2759701716
Short name T529
Test name
Test status
Simulation time 181685284 ps
CPU time 12.58 seconds
Started Jan 07 01:41:24 PM PST 24
Finished Jan 07 01:41:42 PM PST 24
Peak memory 252444 kb
Host smart-c8482738-a72e-4e4c-8945-d1858ceb0222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27597
01716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2759701716
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3188897350
Short name T231
Test name
Test status
Simulation time 2441783837 ps
CPU time 39.27 seconds
Started Jan 07 01:41:25 PM PST 24
Finished Jan 07 01:42:10 PM PST 24
Peak memory 248796 kb
Host smart-92696198-b865-4044-88c8-195160685eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31888
97350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3188897350
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.4073926183
Short name T542
Test name
Test status
Simulation time 26417791438 ps
CPU time 415.13 seconds
Started Jan 07 01:41:55 PM PST 24
Finished Jan 07 01:49:00 PM PST 24
Peak memory 256804 kb
Host smart-a553d48c-a203-4751-aeb1-c1dfff432c29
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073926183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.4073926183
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3289428867
Short name T251
Test name
Test status
Simulation time 25435274040 ps
CPU time 1509.23 seconds
Started Jan 07 01:41:32 PM PST 24
Finished Jan 07 02:06:47 PM PST 24
Peak memory 289140 kb
Host smart-c81cba75-bcb7-4bec-b05b-292f28330cb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289428867 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3289428867
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2324075538
Short name T89
Test name
Test status
Simulation time 59299677007 ps
CPU time 1717.56 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 02:10:59 PM PST 24
Peak memory 281508 kb
Host smart-4f30c340-8c17-4cd9-91ec-34ff6723f4b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324075538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2324075538
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1811707237
Short name T532
Test name
Test status
Simulation time 1732154151 ps
CPU time 139.01 seconds
Started Jan 07 01:42:10 PM PST 24
Finished Jan 07 01:44:38 PM PST 24
Peak memory 256172 kb
Host smart-16cb99cd-e8ba-4c7a-8017-59402e0d5173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18117
07237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1811707237
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.69832149
Short name T86
Test name
Test status
Simulation time 803613758 ps
CPU time 23.34 seconds
Started Jan 07 01:42:05 PM PST 24
Finished Jan 07 01:42:37 PM PST 24
Peak memory 254344 kb
Host smart-1174b00c-9ec5-4c45-aa22-e7bd1cba421d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69832
149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.69832149
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.49467278
Short name T558
Test name
Test status
Simulation time 11003544679 ps
CPU time 1216.85 seconds
Started Jan 07 01:42:08 PM PST 24
Finished Jan 07 02:02:34 PM PST 24
Peak memory 289724 kb
Host smart-0c1c1e8e-77c9-4e43-a55d-efe383215dae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49467278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.49467278
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1515834506
Short name T591
Test name
Test status
Simulation time 3654321907 ps
CPU time 146.85 seconds
Started Jan 07 01:41:57 PM PST 24
Finished Jan 07 01:44:34 PM PST 24
Peak memory 247632 kb
Host smart-74220ab3-f8d5-4357-89c0-0c699271fec2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515834506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1515834506
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.615174826
Short name T539
Test name
Test status
Simulation time 49015727 ps
CPU time 2.55 seconds
Started Jan 07 01:41:39 PM PST 24
Finished Jan 07 01:41:55 PM PST 24
Peak memory 240404 kb
Host smart-958fa8a9-03b8-41ce-8862-7b106bd400dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61517
4826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.615174826
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1090676405
Short name T724
Test name
Test status
Simulation time 6366748874 ps
CPU time 35.13 seconds
Started Jan 07 01:42:07 PM PST 24
Finished Jan 07 01:42:51 PM PST 24
Peak memory 254768 kb
Host smart-290190b0-30eb-4b4e-bd8c-3f4041b98708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10906
76405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1090676405
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1920363779
Short name T710
Test name
Test status
Simulation time 1036745759 ps
CPU time 13.6 seconds
Started Jan 07 01:41:31 PM PST 24
Finished Jan 07 01:41:50 PM PST 24
Peak memory 247776 kb
Host smart-753d3858-fdbc-401a-a17e-5309c44cd5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19203
63779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1920363779
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3777467978
Short name T544
Test name
Test status
Simulation time 5248055245 ps
CPU time 25.9 seconds
Started Jan 07 01:41:27 PM PST 24
Finished Jan 07 01:41:59 PM PST 24
Peak memory 248740 kb
Host smart-9bd5d559-957e-41d9-91b6-cbcca87e3ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37774
67978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3777467978
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2285083442
Short name T620
Test name
Test status
Simulation time 48296945442 ps
CPU time 2670.79 seconds
Started Jan 07 01:42:16 PM PST 24
Finished Jan 07 02:27:02 PM PST 24
Peak memory 289136 kb
Host smart-ad3669d7-8529-4a19-883f-939ef3b17fee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285083442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2285083442
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3721311633
Short name T485
Test name
Test status
Simulation time 17746301863 ps
CPU time 1045.85 seconds
Started Jan 07 01:41:51 PM PST 24
Finished Jan 07 01:59:28 PM PST 24
Peak memory 273380 kb
Host smart-f34e25f4-648d-472e-aa52-fd21bffebaff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721311633 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3721311633
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3708567509
Short name T97
Test name
Test status
Simulation time 41948797924 ps
CPU time 1251.34 seconds
Started Jan 07 01:42:19 PM PST 24
Finished Jan 07 02:03:27 PM PST 24
Peak memory 288596 kb
Host smart-14ec220e-c209-4a7c-a0b4-7290bc9affbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708567509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3708567509
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3915300391
Short name T390
Test name
Test status
Simulation time 4682239847 ps
CPU time 164.98 seconds
Started Jan 07 01:42:19 PM PST 24
Finished Jan 07 01:45:20 PM PST 24
Peak memory 255848 kb
Host smart-08b4f8d0-b193-4f81-8554-2d790b95db72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39153
00391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3915300391
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3742140881
Short name T388
Test name
Test status
Simulation time 2154399353 ps
CPU time 37.08 seconds
Started Jan 07 01:42:42 PM PST 24
Finished Jan 07 01:43:38 PM PST 24
Peak memory 254452 kb
Host smart-f2840d02-c8a2-48a0-81f1-f12a7fc3325b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37421
40881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3742140881
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3422010745
Short name T401
Test name
Test status
Simulation time 223693448262 ps
CPU time 2958.82 seconds
Started Jan 07 01:42:12 PM PST 24
Finished Jan 07 02:31:40 PM PST 24
Peak memory 288720 kb
Host smart-8094796b-f684-41d6-b514-9832dc8f52a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422010745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3422010745
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3731723615
Short name T611
Test name
Test status
Simulation time 5259132930 ps
CPU time 197.59 seconds
Started Jan 07 01:42:20 PM PST 24
Finished Jan 07 01:45:53 PM PST 24
Peak memory 247456 kb
Host smart-7831cdc9-4b18-48cb-90ce-4251833f33fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731723615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3731723615
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2185505514
Short name T408
Test name
Test status
Simulation time 3243540087 ps
CPU time 24.31 seconds
Started Jan 07 01:42:20 PM PST 24
Finished Jan 07 01:43:00 PM PST 24
Peak memory 255264 kb
Host smart-ab41bf85-13f0-4124-8cbf-60cbe16d59eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21855
05514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2185505514
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.323642317
Short name T547
Test name
Test status
Simulation time 685805152 ps
CPU time 20.32 seconds
Started Jan 07 01:42:24 PM PST 24
Finished Jan 07 01:43:02 PM PST 24
Peak memory 255052 kb
Host smart-08f33b89-db08-4f39-af89-403c3cc8ab54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32364
2317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.323642317
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2851501656
Short name T114
Test name
Test status
Simulation time 2919328086 ps
CPU time 59.65 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 01:43:22 PM PST 24
Peak memory 254776 kb
Host smart-6dc7ab75-364f-4759-a6b0-c91bbeda0500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28515
01656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2851501656
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3604969448
Short name T372
Test name
Test status
Simulation time 1390283586 ps
CPU time 39.81 seconds
Started Jan 07 01:42:27 PM PST 24
Finished Jan 07 01:43:26 PM PST 24
Peak memory 248636 kb
Host smart-72ef26ac-f6f2-439b-b612-292129c3172d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36049
69448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3604969448
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1700397917
Short name T482
Test name
Test status
Simulation time 681493592 ps
CPU time 35.57 seconds
Started Jan 07 01:42:42 PM PST 24
Finished Jan 07 01:43:37 PM PST 24
Peak memory 248576 kb
Host smart-1a600b7d-fb12-49e7-94eb-801812e08670
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700397917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1700397917
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3708947130
Short name T627
Test name
Test status
Simulation time 46289608090 ps
CPU time 1196.02 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 02:02:18 PM PST 24
Peak memory 289740 kb
Host smart-4c1ab315-d295-48d5-99c5-2eafbe67fa47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708947130 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3708947130
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.72496346
Short name T273
Test name
Test status
Simulation time 30731009569 ps
CPU time 1781.2 seconds
Started Jan 07 01:43:29 PM PST 24
Finished Jan 07 02:13:30 PM PST 24
Peak memory 282260 kb
Host smart-0436609a-448c-48d8-84d7-edbeeb8b83c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72496346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.72496346
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2759699550
Short name T491
Test name
Test status
Simulation time 4834176043 ps
CPU time 72.35 seconds
Started Jan 07 01:42:37 PM PST 24
Finished Jan 07 01:44:09 PM PST 24
Peak memory 256404 kb
Host smart-1c0cbfcf-ed4b-4fbf-ac5c-7ec01835b1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27596
99550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2759699550
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.647423548
Short name T595
Test name
Test status
Simulation time 1143431408 ps
CPU time 22.79 seconds
Started Jan 07 01:43:12 PM PST 24
Finished Jan 07 01:43:48 PM PST 24
Peak memory 248604 kb
Host smart-b31ce9fd-2abf-4d13-bf79-90333def3618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64742
3548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.647423548
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1225174791
Short name T713
Test name
Test status
Simulation time 42797522041 ps
CPU time 960.53 seconds
Started Jan 07 01:41:25 PM PST 24
Finished Jan 07 01:57:33 PM PST 24
Peak memory 268120 kb
Host smart-65d5f6f4-c98f-402c-b0e3-b906506b7716
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225174791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1225174791
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.340937890
Short name T560
Test name
Test status
Simulation time 60320204291 ps
CPU time 1160.11 seconds
Started Jan 07 01:41:27 PM PST 24
Finished Jan 07 02:00:53 PM PST 24
Peak memory 288696 kb
Host smart-6ed69f50-96be-4075-af4e-855185cb1df1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340937890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.340937890
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.80841946
Short name T674
Test name
Test status
Simulation time 32422138801 ps
CPU time 326.96 seconds
Started Jan 07 01:43:10 PM PST 24
Finished Jan 07 01:48:50 PM PST 24
Peak memory 247208 kb
Host smart-abeadc04-7bed-4517-9758-f183c3a6ec62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80841946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.80841946
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.330545301
Short name T617
Test name
Test status
Simulation time 10015830203 ps
CPU time 27.12 seconds
Started Jan 07 01:43:02 PM PST 24
Finished Jan 07 01:43:43 PM PST 24
Peak memory 248792 kb
Host smart-0636c916-d4c1-41cd-8c88-59dd97bba622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33054
5301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.330545301
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1374011732
Short name T579
Test name
Test status
Simulation time 643884668 ps
CPU time 9.44 seconds
Started Jan 07 01:42:40 PM PST 24
Finished Jan 07 01:43:10 PM PST 24
Peak memory 249328 kb
Host smart-557ff48b-9dd9-4b85-91fc-49c0744cd375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13740
11732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1374011732
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1774508114
Short name T649
Test name
Test status
Simulation time 1392013548 ps
CPU time 40.14 seconds
Started Jan 07 01:42:45 PM PST 24
Finished Jan 07 01:43:45 PM PST 24
Peak memory 255260 kb
Host smart-1b08cee0-f7a4-4624-9332-eb0da752bd7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17745
08114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1774508114
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.742989967
Short name T420
Test name
Test status
Simulation time 3906599059 ps
CPU time 59.56 seconds
Started Jan 07 01:42:40 PM PST 24
Finished Jan 07 01:44:01 PM PST 24
Peak memory 248748 kb
Host smart-4df98568-b011-4a47-ac84-70e0aa0706cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74298
9967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.742989967
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2688019789
Short name T618
Test name
Test status
Simulation time 93920955225 ps
CPU time 1471.41 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 02:06:07 PM PST 24
Peak memory 288180 kb
Host smart-50554308-7b98-4054-a01f-6dcccb75f4d3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688019789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2688019789
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1796753285
Short name T64
Test name
Test status
Simulation time 31774115135 ps
CPU time 1945.98 seconds
Started Jan 07 01:42:04 PM PST 24
Finished Jan 07 02:14:39 PM PST 24
Peak memory 289372 kb
Host smart-e0adc266-cef3-461f-b4db-46250cf6c235
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796753285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1796753285
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2450405920
Short name T216
Test name
Test status
Simulation time 16881509773 ps
CPU time 215.43 seconds
Started Jan 07 01:41:24 PM PST 24
Finished Jan 07 01:45:04 PM PST 24
Peak memory 256804 kb
Host smart-43072e4a-e4fc-411c-9f0c-d80f3ac70785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24504
05920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2450405920
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.4131434850
Short name T511
Test name
Test status
Simulation time 1108283833 ps
CPU time 26.05 seconds
Started Jan 07 01:41:38 PM PST 24
Finished Jan 07 01:42:15 PM PST 24
Peak memory 254432 kb
Host smart-68202785-3880-4127-8697-ad449f5b3042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41314
34850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.4131434850
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.508669104
Short name T343
Test name
Test status
Simulation time 60485064505 ps
CPU time 1019.02 seconds
Started Jan 07 01:41:35 PM PST 24
Finished Jan 07 01:58:42 PM PST 24
Peak memory 273276 kb
Host smart-594bb76b-bf68-448a-b158-4853aff1b19f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508669104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.508669104
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.4146534502
Short name T98
Test name
Test status
Simulation time 15789335223 ps
CPU time 706.6 seconds
Started Jan 07 01:41:25 PM PST 24
Finished Jan 07 01:53:20 PM PST 24
Peak memory 265320 kb
Host smart-f191df28-e5ba-4fe2-9c33-cf99fb43ed28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146534502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.4146534502
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2835862589
Short name T10
Test name
Test status
Simulation time 14121709077 ps
CPU time 185.15 seconds
Started Jan 07 01:41:31 PM PST 24
Finished Jan 07 01:44:42 PM PST 24
Peak memory 247612 kb
Host smart-c619d59f-1da5-4994-ad3e-cccba7bac7ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835862589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2835862589
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1799350680
Short name T601
Test name
Test status
Simulation time 544595917 ps
CPU time 25.34 seconds
Started Jan 07 01:41:21 PM PST 24
Finished Jan 07 01:41:52 PM PST 24
Peak memory 248720 kb
Host smart-baa53718-8758-4b7c-a4b9-4e68aa3efc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17993
50680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1799350680
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2619297782
Short name T271
Test name
Test status
Simulation time 3889574624 ps
CPU time 60.59 seconds
Started Jan 07 01:41:38 PM PST 24
Finished Jan 07 01:42:50 PM PST 24
Peak memory 254840 kb
Host smart-6dd2ec26-5b8e-493f-81cc-7f23950b20b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26192
97782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2619297782
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.111212900
Short name T583
Test name
Test status
Simulation time 539431069 ps
CPU time 17.35 seconds
Started Jan 07 01:41:21 PM PST 24
Finished Jan 07 01:41:49 PM PST 24
Peak memory 248556 kb
Host smart-239b9ba8-09f9-4c00-87a6-89863bfaa3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11121
2900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.111212900
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3230709129
Short name T87
Test name
Test status
Simulation time 331376534 ps
CPU time 21.07 seconds
Started Jan 07 01:41:11 PM PST 24
Finished Jan 07 01:41:44 PM PST 24
Peak memory 248760 kb
Host smart-ceebf683-e0a9-4226-b5c5-6582f7fbedc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32307
09129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3230709129
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.90290632
Short name T125
Test name
Test status
Simulation time 46100196893 ps
CPU time 2447.47 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 02:22:23 PM PST 24
Peak memory 289276 kb
Host smart-99a04971-a832-4752-b6ee-aa317f13baaf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90290632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_hand
ler_stress_all.90290632
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3769258740
Short name T699
Test name
Test status
Simulation time 27937073990 ps
CPU time 666.21 seconds
Started Jan 07 01:41:55 PM PST 24
Finished Jan 07 01:53:11 PM PST 24
Peak memory 264996 kb
Host smart-59475d3a-c59b-4232-8a44-5052b0533b91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769258740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3769258740
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2308972695
Short name T536
Test name
Test status
Simulation time 129270700 ps
CPU time 7.97 seconds
Started Jan 07 01:41:39 PM PST 24
Finished Jan 07 01:42:00 PM PST 24
Peak memory 250032 kb
Host smart-8ffa14b1-17c8-49b6-ac59-7978727250f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23089
72695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2308972695
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.354488655
Short name T81
Test name
Test status
Simulation time 704228701 ps
CPU time 25.7 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 01:42:17 PM PST 24
Peak memory 254316 kb
Host smart-f7d61017-071c-4472-aee6-62002fd169c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35448
8655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.354488655
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2486164702
Short name T551
Test name
Test status
Simulation time 9816668516 ps
CPU time 966.64 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:57:49 PM PST 24
Peak memory 281752 kb
Host smart-98cb6195-6c34-4fb2-b39b-ba850a7f57cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486164702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2486164702
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1381652545
Short name T42
Test name
Test status
Simulation time 23513721766 ps
CPU time 581.71 seconds
Started Jan 07 01:42:09 PM PST 24
Finished Jan 07 01:52:00 PM PST 24
Peak memory 264696 kb
Host smart-4d3923ce-7263-4b33-a961-c6ffb3458769
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381652545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1381652545
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.570188725
Short name T319
Test name
Test status
Simulation time 21049454449 ps
CPU time 441.61 seconds
Started Jan 07 01:42:02 PM PST 24
Finished Jan 07 01:49:32 PM PST 24
Peak memory 248492 kb
Host smart-b087648f-8f89-4ffe-ad94-e2262dffea80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570188725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.570188725
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1920186155
Short name T671
Test name
Test status
Simulation time 358146171 ps
CPU time 17.12 seconds
Started Jan 07 01:41:44 PM PST 24
Finished Jan 07 01:42:15 PM PST 24
Peak memory 248732 kb
Host smart-3f7351f5-05eb-468a-a352-ae8bc5f0462b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19201
86155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1920186155
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3204765028
Short name T400
Test name
Test status
Simulation time 5437905091 ps
CPU time 25.73 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 01:42:11 PM PST 24
Peak memory 255020 kb
Host smart-904280e0-5187-4961-933f-f6f307fe99d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32047
65028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3204765028
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1513444875
Short name T35
Test name
Test status
Simulation time 87602401 ps
CPU time 6.21 seconds
Started Jan 07 01:41:37 PM PST 24
Finished Jan 07 01:41:54 PM PST 24
Peak memory 253488 kb
Host smart-b70b983d-3abd-4150-a566-30ed45725662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15134
44875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1513444875
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3432985089
Short name T691
Test name
Test status
Simulation time 86744488 ps
CPU time 6.23 seconds
Started Jan 07 01:41:40 PM PST 24
Finished Jan 07 01:42:01 PM PST 24
Peak memory 248772 kb
Host smart-83bf1b84-2cc1-40e6-b1fb-750bbe6627f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34329
85089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3432985089
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.88814903
Short name T303
Test name
Test status
Simulation time 76252614658 ps
CPU time 1663.91 seconds
Started Jan 07 01:42:11 PM PST 24
Finished Jan 07 02:10:04 PM PST 24
Peak memory 288888 kb
Host smart-a4a1f630-21ac-428a-aeef-c055cb2e185b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88814903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_hand
ler_stress_all.88814903
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2876052352
Short name T200
Test name
Test status
Simulation time 82511983 ps
CPU time 3.85 seconds
Started Jan 07 01:40:32 PM PST 24
Finished Jan 07 01:41:02 PM PST 24
Peak memory 248912 kb
Host smart-d1ed261c-a5b0-49b9-9216-f81f61fcee91
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2876052352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2876052352
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3446197925
Short name T733
Test name
Test status
Simulation time 45128218198 ps
CPU time 2494.38 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 02:22:41 PM PST 24
Peak memory 289124 kb
Host smart-29a930dc-3185-4936-a6a6-c361c5830af9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446197925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3446197925
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.4191444434
Short name T609
Test name
Test status
Simulation time 1310801632 ps
CPU time 15.39 seconds
Started Jan 07 01:40:24 PM PST 24
Finished Jan 07 01:41:03 PM PST 24
Peak memory 240500 kb
Host smart-766d1a6f-7d9e-4258-bba5-50134d42b505
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4191444434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4191444434
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1808747126
Short name T549
Test name
Test status
Simulation time 478835629 ps
CPU time 49.95 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 01:41:54 PM PST 24
Peak memory 248104 kb
Host smart-8e0baa43-5510-4397-bcfa-beb74d570ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18087
47126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1808747126
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1589518082
Short name T588
Test name
Test status
Simulation time 34781534 ps
CPU time 4.42 seconds
Started Jan 07 01:40:24 PM PST 24
Finished Jan 07 01:40:52 PM PST 24
Peak memory 240120 kb
Host smart-98f9aa09-5145-4ca8-9197-66bdbb0df568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15895
18082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1589518082
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2354497828
Short name T340
Test name
Test status
Simulation time 71691022983 ps
CPU time 1975.67 seconds
Started Jan 07 01:40:29 PM PST 24
Finished Jan 07 02:13:49 PM PST 24
Peak memory 286420 kb
Host smart-65a5c632-39f0-432a-a73b-dbe706ed77fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354497828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2354497828
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3132839750
Short name T605
Test name
Test status
Simulation time 193227025052 ps
CPU time 2585.56 seconds
Started Jan 07 01:40:20 PM PST 24
Finished Jan 07 02:23:51 PM PST 24
Peak memory 283480 kb
Host smart-33cd485a-54fe-4636-9a63-cf34e3325d7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132839750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3132839750
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2859355384
Short name T324
Test name
Test status
Simulation time 5044980259 ps
CPU time 192.6 seconds
Started Jan 07 01:40:33 PM PST 24
Finished Jan 07 01:44:11 PM PST 24
Peak memory 248696 kb
Host smart-3c5e7946-90da-45ba-b5ad-75efa12b447a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859355384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2859355384
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2345182923
Short name T410
Test name
Test status
Simulation time 1683573313 ps
CPU time 47.03 seconds
Started Jan 07 01:40:31 PM PST 24
Finished Jan 07 01:41:44 PM PST 24
Peak memory 255136 kb
Host smart-94489479-2be4-4549-97b9-b19cfc4a0d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23451
82923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2345182923
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1187994831
Short name T422
Test name
Test status
Simulation time 1060468890 ps
CPU time 21.09 seconds
Started Jan 07 01:40:24 PM PST 24
Finished Jan 07 01:41:09 PM PST 24
Peak memory 246968 kb
Host smart-c71f5c93-2e7b-42eb-a60d-37820074976b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11879
94831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1187994831
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.120354694
Short name T606
Test name
Test status
Simulation time 314864895 ps
CPU time 22.37 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:41:30 PM PST 24
Peak memory 248572 kb
Host smart-e15b31af-af77-49b8-bf8f-ebe0d8542a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12035
4694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.120354694
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.888050821
Short name T643
Test name
Test status
Simulation time 368372874 ps
CPU time 21.25 seconds
Started Jan 07 01:40:44 PM PST 24
Finished Jan 07 01:41:32 PM PST 24
Peak memory 248604 kb
Host smart-9d4a6ac2-e559-4f63-bea4-5a5c7bccfbfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88805
0821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.888050821
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.500857685
Short name T233
Test name
Test status
Simulation time 1645893694 ps
CPU time 132.63 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:43:20 PM PST 24
Peak memory 256812 kb
Host smart-67b6ce50-ea47-4adc-92ae-12db1b866624
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500857685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.500857685
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.4288476064
Short name T249
Test name
Test status
Simulation time 72218840867 ps
CPU time 5250.46 seconds
Started Jan 07 01:40:44 PM PST 24
Finished Jan 07 03:08:41 PM PST 24
Peak memory 313640 kb
Host smart-774f48cb-7f7b-44cd-a8e0-2b138473317c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288476064 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.4288476064
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3868041703
Short name T236
Test name
Test status
Simulation time 346404721415 ps
CPU time 2537.27 seconds
Started Jan 07 01:42:31 PM PST 24
Finished Jan 07 02:25:05 PM PST 24
Peak memory 284752 kb
Host smart-eb809d7c-129e-4d98-baba-c842b0889056
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868041703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3868041703
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1062403742
Short name T682
Test name
Test status
Simulation time 3521516908 ps
CPU time 135.94 seconds
Started Jan 07 01:41:53 PM PST 24
Finished Jan 07 01:44:20 PM PST 24
Peak memory 255996 kb
Host smart-2020252f-c743-4647-890d-42c4b78d7098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10624
03742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1062403742
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2062506742
Short name T427
Test name
Test status
Simulation time 1142923645 ps
CPU time 66.61 seconds
Started Jan 07 01:42:11 PM PST 24
Finished Jan 07 01:43:27 PM PST 24
Peak memory 248532 kb
Host smart-65a592c7-215a-4bce-8269-06855e317993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20625
06742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2062506742
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2221440468
Short name T356
Test name
Test status
Simulation time 52073758657 ps
CPU time 1141.58 seconds
Started Jan 07 01:42:17 PM PST 24
Finished Jan 07 02:01:34 PM PST 24
Peak memory 284140 kb
Host smart-dc8d80c5-ecc8-4d9a-8497-dbc47d650565
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221440468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2221440468
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.866952571
Short name T596
Test name
Test status
Simulation time 38419045460 ps
CPU time 1543.69 seconds
Started Jan 07 01:42:32 PM PST 24
Finished Jan 07 02:08:31 PM PST 24
Peak memory 289080 kb
Host smart-41ba73cd-4d7e-46f0-b7d8-616abed4e942
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866952571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.866952571
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1919639486
Short name T329
Test name
Test status
Simulation time 11863428309 ps
CPU time 475.83 seconds
Started Jan 07 01:42:20 PM PST 24
Finished Jan 07 01:50:32 PM PST 24
Peak memory 247536 kb
Host smart-4dd9a7a4-d55a-4777-b3f4-9c86b461e1ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919639486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1919639486
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1857549339
Short name T698
Test name
Test status
Simulation time 1014394761 ps
CPU time 28.3 seconds
Started Jan 07 01:42:21 PM PST 24
Finished Jan 07 01:43:05 PM PST 24
Peak memory 248656 kb
Host smart-b206fbad-ee26-4f30-b884-00584aed1bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18575
49339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1857549339
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.651747441
Short name T21
Test name
Test status
Simulation time 483421184 ps
CPU time 8.5 seconds
Started Jan 07 01:41:45 PM PST 24
Finished Jan 07 01:42:07 PM PST 24
Peak memory 250032 kb
Host smart-34a53d5e-1265-4ee6-b86e-49afb58e9aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65174
7441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.651747441
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3785160933
Short name T727
Test name
Test status
Simulation time 965579242 ps
CPU time 57.12 seconds
Started Jan 07 01:41:54 PM PST 24
Finished Jan 07 01:43:01 PM PST 24
Peak memory 247720 kb
Host smart-2342ecf4-f779-4f29-921a-b078b86c1b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37851
60933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3785160933
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1876047320
Short name T693
Test name
Test status
Simulation time 7275130073 ps
CPU time 62.26 seconds
Started Jan 07 01:42:01 PM PST 24
Finished Jan 07 01:43:12 PM PST 24
Peak memory 248720 kb
Host smart-10a07497-472d-48c0-87ad-65b22663ea20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18760
47320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1876047320
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2467676089
Short name T44
Test name
Test status
Simulation time 14101445130 ps
CPU time 741.71 seconds
Started Jan 07 01:41:44 PM PST 24
Finished Jan 07 01:54:20 PM PST 24
Peak memory 265108 kb
Host smart-45f3c698-44c7-4559-867d-aa688e365276
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467676089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2467676089
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1578339811
Short name T463
Test name
Test status
Simulation time 56214303728 ps
CPU time 3036.24 seconds
Started Jan 07 01:42:34 PM PST 24
Finished Jan 07 02:33:29 PM PST 24
Peak memory 289480 kb
Host smart-d3743e82-b187-47cc-9675-395c2676c5a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578339811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1578339811
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3034582738
Short name T636
Test name
Test status
Simulation time 2227289862 ps
CPU time 116.54 seconds
Started Jan 07 01:42:30 PM PST 24
Finished Jan 07 01:44:44 PM PST 24
Peak memory 255944 kb
Host smart-551d5877-ffb7-4699-941d-352b7db5e649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30345
82738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3034582738
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1531867747
Short name T221
Test name
Test status
Simulation time 1064234940 ps
CPU time 57.01 seconds
Started Jan 07 01:42:42 PM PST 24
Finished Jan 07 01:44:06 PM PST 24
Peak memory 254396 kb
Host smart-ad7b4293-348b-4034-8995-32d54fd39b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15318
67747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1531867747
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1283698729
Short name T352
Test name
Test status
Simulation time 36811607689 ps
CPU time 2278.5 seconds
Started Jan 07 01:43:13 PM PST 24
Finished Jan 07 02:21:26 PM PST 24
Peak memory 288832 kb
Host smart-87e5c396-4b48-4ed0-b56d-1b0a8c78f88b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283698729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1283698729
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1104572087
Short name T382
Test name
Test status
Simulation time 81982802246 ps
CPU time 2089.38 seconds
Started Jan 07 01:42:33 PM PST 24
Finished Jan 07 02:17:39 PM PST 24
Peak memory 284212 kb
Host smart-2fd8b927-1fc7-4418-9c6b-1ae0dd715ca5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104572087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1104572087
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3640451942
Short name T320
Test name
Test status
Simulation time 15519488244 ps
CPU time 303.13 seconds
Started Jan 07 01:43:11 PM PST 24
Finished Jan 07 01:48:28 PM PST 24
Peak memory 247624 kb
Host smart-ba8f84e2-54eb-484f-b03f-b77bbf53b922
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640451942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3640451942
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1738716518
Short name T506
Test name
Test status
Simulation time 2788774836 ps
CPU time 49.67 seconds
Started Jan 07 01:42:35 PM PST 24
Finished Jan 07 01:43:44 PM PST 24
Peak memory 248640 kb
Host smart-2bba7361-1289-4f3d-b77a-25d3da3304c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17387
16518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1738716518
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3303012908
Short name T283
Test name
Test status
Simulation time 9473861408 ps
CPU time 26.08 seconds
Started Jan 07 01:42:45 PM PST 24
Finished Jan 07 01:43:31 PM PST 24
Peak memory 246792 kb
Host smart-fe7d7686-80ad-44c3-9f84-980682d571dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33030
12908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3303012908
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2310117863
Short name T673
Test name
Test status
Simulation time 3201682106 ps
CPU time 42.28 seconds
Started Jan 07 01:42:39 PM PST 24
Finished Jan 07 01:43:43 PM PST 24
Peak memory 255136 kb
Host smart-e36963c1-4874-4477-a500-1e25cb9a6a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23101
17863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2310117863
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3617623457
Short name T730
Test name
Test status
Simulation time 1114426872 ps
CPU time 22.71 seconds
Started Jan 07 01:42:21 PM PST 24
Finished Jan 07 01:43:00 PM PST 24
Peak memory 256812 kb
Host smart-53a74712-1b08-4b90-aa5f-42b1dfea8e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36176
23457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3617623457
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3263424169
Short name T663
Test name
Test status
Simulation time 170585590885 ps
CPU time 2293.49 seconds
Started Jan 07 01:41:22 PM PST 24
Finished Jan 07 02:19:41 PM PST 24
Peak memory 283392 kb
Host smart-118ca794-5573-4b2b-80e5-b2e14dba3760
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263424169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3263424169
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1313243476
Short name T245
Test name
Test status
Simulation time 439579602632 ps
CPU time 3927.94 seconds
Started Jan 07 01:41:35 PM PST 24
Finished Jan 07 02:47:11 PM PST 24
Peak memory 322136 kb
Host smart-1f6a9128-5576-4ae4-a291-c4b40739e3da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313243476 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1313243476
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1412332607
Short name T425
Test name
Test status
Simulation time 100933932185 ps
CPU time 1579.23 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 02:08:00 PM PST 24
Peak memory 273020 kb
Host smart-d27cdf1f-4a94-4246-b806-c0d0831df7e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412332607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1412332607
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2903488857
Short name T462
Test name
Test status
Simulation time 5951098940 ps
CPU time 72.34 seconds
Started Jan 07 01:41:22 PM PST 24
Finished Jan 07 01:42:40 PM PST 24
Peak memory 256732 kb
Host smart-cd32cdf0-1cbf-4ba6-b3f1-f72787cf7549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29034
88857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2903488857
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.4228721708
Short name T725
Test name
Test status
Simulation time 379405895 ps
CPU time 29.8 seconds
Started Jan 07 01:41:23 PM PST 24
Finished Jan 07 01:41:58 PM PST 24
Peak memory 248540 kb
Host smart-a0afd1bc-ce09-48a6-b080-df9c877a32e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42287
21708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.4228721708
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1901349198
Short name T348
Test name
Test status
Simulation time 204734972724 ps
CPU time 916.61 seconds
Started Jan 07 01:41:21 PM PST 24
Finished Jan 07 01:56:43 PM PST 24
Peak memory 273324 kb
Host smart-f62f8ca0-574a-4e4e-9028-7e7c6795cba5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901349198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1901349198
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.397756143
Short name T683
Test name
Test status
Simulation time 256618343576 ps
CPU time 1808.8 seconds
Started Jan 07 01:41:57 PM PST 24
Finished Jan 07 02:12:16 PM PST 24
Peak memory 288520 kb
Host smart-566d7a8f-06be-4714-add0-426c69a05c7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397756143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.397756143
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1409565801
Short name T336
Test name
Test status
Simulation time 29221383993 ps
CPU time 588.99 seconds
Started Jan 07 01:41:35 PM PST 24
Finished Jan 07 01:51:32 PM PST 24
Peak memory 248288 kb
Host smart-b475cb0f-a236-482b-a38b-6d755881c985
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409565801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1409565801
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3002813341
Short name T523
Test name
Test status
Simulation time 629713158 ps
CPU time 12.21 seconds
Started Jan 07 01:41:25 PM PST 24
Finished Jan 07 01:41:45 PM PST 24
Peak memory 253688 kb
Host smart-11d46648-c286-4589-b760-5b137c8864bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30028
13341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3002813341
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.4043448896
Short name T70
Test name
Test status
Simulation time 316875652 ps
CPU time 20.32 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 01:41:56 PM PST 24
Peak memory 247204 kb
Host smart-17a1582d-239f-4f68-a179-da17ee4a3852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40434
48896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.4043448896
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2047977908
Short name T77
Test name
Test status
Simulation time 588463697 ps
CPU time 34.07 seconds
Started Jan 07 01:41:38 PM PST 24
Finished Jan 07 01:42:24 PM PST 24
Peak memory 255272 kb
Host smart-9298b4d1-2196-46c1-8f72-815fc55072a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20479
77908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2047977908
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3786816040
Short name T712
Test name
Test status
Simulation time 124102471 ps
CPU time 9.11 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 01:41:54 PM PST 24
Peak memory 248776 kb
Host smart-85480a5a-3812-4c98-a5f6-2b4de53d8c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37868
16040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3786816040
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1521059882
Short name T684
Test name
Test status
Simulation time 10625100897 ps
CPU time 937.26 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 01:57:13 PM PST 24
Peak memory 283540 kb
Host smart-e4c35d70-8b3c-4fd6-afbe-3bd4197f3e97
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521059882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1521059882
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.384526642
Short name T106
Test name
Test status
Simulation time 36840489691 ps
CPU time 833.41 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 01:55:29 PM PST 24
Peak memory 285248 kb
Host smart-caf88a2f-d5d7-4906-a6a0-903dd4ab3846
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384526642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.384526642
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3433816048
Short name T411
Test name
Test status
Simulation time 4779812808 ps
CPU time 90.04 seconds
Started Jan 07 01:41:53 PM PST 24
Finished Jan 07 01:43:34 PM PST 24
Peak memory 256288 kb
Host smart-a3ef7eaa-e6ec-4e85-82fb-75e67352b130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34338
16048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3433816048
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3864327327
Short name T84
Test name
Test status
Simulation time 3495933586 ps
CPU time 51.16 seconds
Started Jan 07 01:41:29 PM PST 24
Finished Jan 07 01:42:31 PM PST 24
Peak memory 248820 kb
Host smart-4bc68cce-61c0-41d7-b669-6a96d4e41619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38643
27327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3864327327
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1536446785
Short name T322
Test name
Test status
Simulation time 68106751524 ps
CPU time 1819.33 seconds
Started Jan 07 01:41:30 PM PST 24
Finished Jan 07 02:11:55 PM PST 24
Peak memory 281568 kb
Host smart-e67e6c60-ac32-4936-ac27-0d0cfd6d91e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536446785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1536446785
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3212432916
Short name T102
Test name
Test status
Simulation time 23274000979 ps
CPU time 1170.28 seconds
Started Jan 07 01:42:08 PM PST 24
Finished Jan 07 02:01:48 PM PST 24
Peak memory 271996 kb
Host smart-c6d617d3-1b6c-4383-bdaa-1d2fdb1b251c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212432916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3212432916
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3673811085
Short name T703
Test name
Test status
Simulation time 2863131487 ps
CPU time 120.26 seconds
Started Jan 07 01:41:55 PM PST 24
Finished Jan 07 01:44:05 PM PST 24
Peak memory 247344 kb
Host smart-957172f1-ffc8-45a3-a146-99c7da4c7b75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673811085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3673811085
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3847536840
Short name T230
Test name
Test status
Simulation time 1074998879 ps
CPU time 23.16 seconds
Started Jan 07 01:41:28 PM PST 24
Finished Jan 07 01:41:56 PM PST 24
Peak memory 248616 kb
Host smart-1cf94942-38ea-4e74-adbb-71b384920033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38475
36840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3847536840
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3252585249
Short name T525
Test name
Test status
Simulation time 139742998 ps
CPU time 7.28 seconds
Started Jan 07 01:41:56 PM PST 24
Finished Jan 07 01:42:13 PM PST 24
Peak memory 250920 kb
Host smart-a5312fac-9b81-4357-9c68-e89195124194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32525
85249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3252585249
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2575151166
Short name T247
Test name
Test status
Simulation time 223992864 ps
CPU time 14.67 seconds
Started Jan 07 01:42:01 PM PST 24
Finished Jan 07 01:42:25 PM PST 24
Peak memory 255132 kb
Host smart-c6ea8576-37ce-4811-9e66-1ac776c08b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25751
51166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2575151166
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2239606765
Short name T402
Test name
Test status
Simulation time 63519038 ps
CPU time 6.75 seconds
Started Jan 07 01:41:37 PM PST 24
Finished Jan 07 01:41:54 PM PST 24
Peak memory 248744 kb
Host smart-0dc2f278-6013-4ef5-9d52-f5a90914df93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22396
06765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2239606765
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3516372712
Short name T632
Test name
Test status
Simulation time 215154353170 ps
CPU time 3212.75 seconds
Started Jan 07 01:41:33 PM PST 24
Finished Jan 07 02:35:12 PM PST 24
Peak memory 298000 kb
Host smart-3e7d9604-3e25-41eb-8612-208abb04999a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516372712 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3516372712
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2629496548
Short name T281
Test name
Test status
Simulation time 13994564949 ps
CPU time 1240.84 seconds
Started Jan 07 01:42:02 PM PST 24
Finished Jan 07 02:02:52 PM PST 24
Peak memory 284568 kb
Host smart-57095679-d139-4917-930c-b2c21781e66c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629496548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2629496548
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2432582735
Short name T440
Test name
Test status
Simulation time 5585665846 ps
CPU time 98.21 seconds
Started Jan 07 01:41:55 PM PST 24
Finished Jan 07 01:43:43 PM PST 24
Peak memory 249704 kb
Host smart-54e423fa-713b-4cf9-91f4-a07591506043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24325
82735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2432582735
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2653703768
Short name T607
Test name
Test status
Simulation time 354655634 ps
CPU time 28.23 seconds
Started Jan 07 01:42:01 PM PST 24
Finished Jan 07 01:42:38 PM PST 24
Peak memory 254296 kb
Host smart-994a8e5a-b16f-4894-8b45-c8b674ac4738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26537
03768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2653703768
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.936198161
Short name T19
Test name
Test status
Simulation time 46162143291 ps
CPU time 863.44 seconds
Started Jan 07 01:42:07 PM PST 24
Finished Jan 07 01:56:39 PM PST 24
Peak memory 272540 kb
Host smart-b26c408d-3454-448d-9e47-00728f604c3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936198161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.936198161
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.4089097516
Short name T439
Test name
Test status
Simulation time 120818256231 ps
CPU time 1314.09 seconds
Started Jan 07 01:42:07 PM PST 24
Finished Jan 07 02:04:11 PM PST 24
Peak memory 288904 kb
Host smart-ea328c53-b8b7-4c91-af95-9095ce0eabcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089097516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.4089097516
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1513232980
Short name T229
Test name
Test status
Simulation time 2694161602 ps
CPU time 116.58 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 01:44:06 PM PST 24
Peak memory 246672 kb
Host smart-f507bfb2-7cbb-475c-a76d-3f6edff85108
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513232980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1513232980
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.492475842
Short name T67
Test name
Test status
Simulation time 15449085735 ps
CPU time 57.52 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 01:42:42 PM PST 24
Peak memory 255708 kb
Host smart-9fb5191c-bb35-45ad-8303-e53c1a00dbba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49247
5842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.492475842
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1018851163
Short name T263
Test name
Test status
Simulation time 397737166 ps
CPU time 35.77 seconds
Started Jan 07 01:42:10 PM PST 24
Finished Jan 07 01:42:54 PM PST 24
Peak memory 246928 kb
Host smart-ac6b370e-c0ca-4769-9d0b-bcfd352463c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10188
51163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1018851163
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.190285986
Short name T294
Test name
Test status
Simulation time 1972696263 ps
CPU time 58.55 seconds
Started Jan 07 01:42:29 PM PST 24
Finished Jan 07 01:43:44 PM PST 24
Peak memory 255092 kb
Host smart-c56f7277-60cf-493e-99ee-7d259df644d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19028
5986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.190285986
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.756967739
Short name T374
Test name
Test status
Simulation time 735721629 ps
CPU time 41.71 seconds
Started Jan 07 01:41:52 PM PST 24
Finished Jan 07 01:42:45 PM PST 24
Peak memory 248608 kb
Host smart-94674f2c-83dd-4d86-9c6f-9c0eb02879f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75696
7739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.756967739
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1990662364
Short name T88
Test name
Test status
Simulation time 216667944846 ps
CPU time 3128.93 seconds
Started Jan 07 01:41:46 PM PST 24
Finished Jan 07 02:34:09 PM PST 24
Peak memory 306136 kb
Host smart-a8a512e7-3591-407e-aaad-6c6c4735a56e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990662364 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1990662364
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3429668626
Short name T456
Test name
Test status
Simulation time 116383089512 ps
CPU time 1655.74 seconds
Started Jan 07 01:42:43 PM PST 24
Finished Jan 07 02:10:39 PM PST 24
Peak memory 272912 kb
Host smart-43a0a989-4fb1-4538-84b4-8a9a906deed7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429668626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3429668626
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.4088347269
Short name T667
Test name
Test status
Simulation time 369855118 ps
CPU time 11.21 seconds
Started Jan 07 01:42:36 PM PST 24
Finished Jan 07 01:43:07 PM PST 24
Peak memory 255592 kb
Host smart-17a3c9e8-e3e7-4721-808e-86b481c9d3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40883
47269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.4088347269
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1193546718
Short name T377
Test name
Test status
Simulation time 9396020903 ps
CPU time 40.89 seconds
Started Jan 07 01:42:14 PM PST 24
Finished Jan 07 01:43:04 PM PST 24
Peak memory 248860 kb
Host smart-e1251769-67ab-497e-bf64-595d062ff8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11935
46718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1193546718
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3490977333
Short name T330
Test name
Test status
Simulation time 10797964560 ps
CPU time 922.96 seconds
Started Jan 07 01:42:16 PM PST 24
Finished Jan 07 01:57:53 PM PST 24
Peak memory 272832 kb
Host smart-71c80972-a770-4476-8339-2a806e07f8b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490977333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3490977333
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1947035301
Short name T252
Test name
Test status
Simulation time 29039543850 ps
CPU time 1758.5 seconds
Started Jan 07 01:42:10 PM PST 24
Finished Jan 07 02:11:38 PM PST 24
Peak memory 273180 kb
Host smart-b8c63710-23ba-4627-a5fd-64603b31b4c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947035301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1947035301
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3704890478
Short name T317
Test name
Test status
Simulation time 22339572563 ps
CPU time 168.01 seconds
Started Jan 07 01:42:33 PM PST 24
Finished Jan 07 01:45:37 PM PST 24
Peak memory 247636 kb
Host smart-5fa6e40f-a256-42cf-8dbe-6eb7cb6b819f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704890478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3704890478
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1395273995
Short name T457
Test name
Test status
Simulation time 1403247179 ps
CPU time 10.88 seconds
Started Jan 07 01:42:20 PM PST 24
Finished Jan 07 01:42:46 PM PST 24
Peak memory 248672 kb
Host smart-b852ad16-e71b-4e44-a5c1-f449a401de96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13952
73995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1395273995
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1548719962
Short name T424
Test name
Test status
Simulation time 483821628 ps
CPU time 9.67 seconds
Started Jan 07 01:42:11 PM PST 24
Finished Jan 07 01:42:29 PM PST 24
Peak memory 246876 kb
Host smart-dfc9ad5d-8089-4957-986e-29fadb25897e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15487
19962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1548719962
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1705813398
Short name T469
Test name
Test status
Simulation time 816005666 ps
CPU time 24.34 seconds
Started Jan 07 01:43:03 PM PST 24
Finished Jan 07 01:43:41 PM PST 24
Peak memory 248424 kb
Host smart-a7bd5af0-0564-47aa-ad47-23a227aee917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17058
13398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1705813398
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3922203424
Short name T445
Test name
Test status
Simulation time 1578814254 ps
CPU time 22.12 seconds
Started Jan 07 01:41:49 PM PST 24
Finished Jan 07 01:42:23 PM PST 24
Peak memory 248592 kb
Host smart-033a3ddd-987b-4aeb-9a91-f825d6e102fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39222
03424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3922203424
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.475704024
Short name T465
Test name
Test status
Simulation time 46263340927 ps
CPU time 2280.04 seconds
Started Jan 07 01:42:42 PM PST 24
Finished Jan 07 02:21:01 PM PST 24
Peak memory 289012 kb
Host smart-a1f14f94-5d3b-43b1-8e3e-89d747eef8fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475704024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.475704024
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.3166988242
Short name T637
Test name
Test status
Simulation time 40949191259 ps
CPU time 4254.41 seconds
Started Jan 07 01:42:31 PM PST 24
Finished Jan 07 02:53:42 PM PST 24
Peak memory 346676 kb
Host smart-bd24105f-bf51-4c2c-8e8b-2c10eeaad3a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166988242 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3166988242
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.4021340066
Short name T120
Test name
Test status
Simulation time 31060219871 ps
CPU time 713.27 seconds
Started Jan 07 01:41:21 PM PST 24
Finished Jan 07 01:53:20 PM PST 24
Peak memory 266052 kb
Host smart-b834f776-743f-4558-ba1e-60e2ad0ee614
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021340066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.4021340066
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2613037262
Short name T616
Test name
Test status
Simulation time 10185215003 ps
CPU time 177.09 seconds
Started Jan 07 01:41:24 PM PST 24
Finished Jan 07 01:44:27 PM PST 24
Peak memory 256300 kb
Host smart-bc02da59-d3a9-4d20-b886-3a47ef961c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26130
37262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2613037262
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3428534493
Short name T115
Test name
Test status
Simulation time 287254645 ps
CPU time 22.33 seconds
Started Jan 07 01:41:23 PM PST 24
Finished Jan 07 01:41:51 PM PST 24
Peak memory 254392 kb
Host smart-b76494b9-b60c-4dd1-9187-6f99165ff0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34285
34493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3428534493
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1483285079
Short name T353
Test name
Test status
Simulation time 61261124212 ps
CPU time 1384.09 seconds
Started Jan 07 01:41:26 PM PST 24
Finished Jan 07 02:04:36 PM PST 24
Peak memory 289120 kb
Host smart-ebf1ab86-ee39-475a-b45e-e2c7e5e66220
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483285079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1483285079
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2475015225
Short name T645
Test name
Test status
Simulation time 8832068392 ps
CPU time 807.38 seconds
Started Jan 07 01:41:27 PM PST 24
Finished Jan 07 01:55:03 PM PST 24
Peak memory 266060 kb
Host smart-bdb0df82-d84c-44a1-b489-ee2eef89a46f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475015225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2475015225
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2494284019
Short name T541
Test name
Test status
Simulation time 4492076278 ps
CPU time 165.61 seconds
Started Jan 07 01:41:35 PM PST 24
Finished Jan 07 01:44:29 PM PST 24
Peak memory 247644 kb
Host smart-01196742-7822-488e-b0d8-a4056d7e23d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494284019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2494284019
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3198921079
Short name T490
Test name
Test status
Simulation time 91003697 ps
CPU time 9.96 seconds
Started Jan 07 01:41:20 PM PST 24
Finished Jan 07 01:41:36 PM PST 24
Peak memory 248584 kb
Host smart-f315ce0b-1298-4c26-b1cf-a435c526b84e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31989
21079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3198921079
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4187871541
Short name T417
Test name
Test status
Simulation time 2302624182 ps
CPU time 40.24 seconds
Started Jan 07 01:41:33 PM PST 24
Finished Jan 07 01:42:19 PM PST 24
Peak memory 254864 kb
Host smart-62ca90d8-0369-4d75-be21-b9c48c6e3ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41878
71541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4187871541
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1898053818
Short name T232
Test name
Test status
Simulation time 1090631906 ps
CPU time 35.98 seconds
Started Jan 07 01:41:21 PM PST 24
Finished Jan 07 01:42:02 PM PST 24
Peak memory 246964 kb
Host smart-ba4eba0b-5dfb-4362-93c5-068708fe9032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18980
53818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1898053818
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2700448599
Short name T545
Test name
Test status
Simulation time 1688000530 ps
CPU time 52.25 seconds
Started Jan 07 01:41:35 PM PST 24
Finished Jan 07 01:42:35 PM PST 24
Peak memory 248656 kb
Host smart-3b894766-405e-41a3-ab25-6b55964694a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27004
48599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2700448599
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.4230736411
Short name T654
Test name
Test status
Simulation time 51589008778 ps
CPU time 1037.21 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 01:59:01 PM PST 24
Peak memory 287444 kb
Host smart-3bf1aab6-540e-48c7-bda2-8ed49d90069d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230736411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.4230736411
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.594225788
Short name T311
Test name
Test status
Simulation time 36033757573 ps
CPU time 2216.54 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 02:18:42 PM PST 24
Peak memory 289004 kb
Host smart-5df21a08-de74-4f86-a540-280ed13bc685
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594225788 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.594225788
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3690794185
Short name T123
Test name
Test status
Simulation time 7227968879 ps
CPU time 660.52 seconds
Started Jan 07 01:41:37 PM PST 24
Finished Jan 07 01:52:48 PM PST 24
Peak memory 266140 kb
Host smart-3b621b31-62f0-431c-a134-b73711882f76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690794185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3690794185
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.4216778396
Short name T478
Test name
Test status
Simulation time 10709592954 ps
CPU time 94.27 seconds
Started Jan 07 01:41:37 PM PST 24
Finished Jan 07 01:43:20 PM PST 24
Peak memory 256936 kb
Host smart-e331898f-3e96-470b-aec1-652779266d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42167
78396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.4216778396
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1690312628
Short name T569
Test name
Test status
Simulation time 129106166 ps
CPU time 13.84 seconds
Started Jan 07 01:41:34 PM PST 24
Finished Jan 07 01:41:56 PM PST 24
Peak memory 246992 kb
Host smart-cbbdc673-93de-4a6d-9c38-c8e606804396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16903
12628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1690312628
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1492351982
Short name T584
Test name
Test status
Simulation time 149844095662 ps
CPU time 2826 seconds
Started Jan 07 01:41:37 PM PST 24
Finished Jan 07 02:28:53 PM PST 24
Peak memory 286372 kb
Host smart-75bf6238-8916-4203-b205-51c1e48447e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492351982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1492351982
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3482672338
Short name T108
Test name
Test status
Simulation time 390746950375 ps
CPU time 2804.4 seconds
Started Jan 07 01:41:31 PM PST 24
Finished Jan 07 02:28:21 PM PST 24
Peak memory 289056 kb
Host smart-98e28f9c-c4db-4df7-a45f-1a59e33e477b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482672338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3482672338
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1546354621
Short name T308
Test name
Test status
Simulation time 9592140018 ps
CPU time 398.77 seconds
Started Jan 07 01:41:38 PM PST 24
Finished Jan 07 01:48:28 PM PST 24
Peak memory 246492 kb
Host smart-b1b52b19-a9cf-4654-8f54-5915488536c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546354621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1546354621
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3520529389
Short name T504
Test name
Test status
Simulation time 282956192 ps
CPU time 14.83 seconds
Started Jan 07 01:41:39 PM PST 24
Finished Jan 07 01:42:08 PM PST 24
Peak memory 254600 kb
Host smart-add2127f-e0b6-443e-97e9-3cccc1452ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35205
29389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3520529389
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.203476996
Short name T708
Test name
Test status
Simulation time 485175639 ps
CPU time 36.18 seconds
Started Jan 07 01:41:37 PM PST 24
Finished Jan 07 01:42:24 PM PST 24
Peak memory 248540 kb
Host smart-0b1ffd9e-514f-4154-8203-3bf6d331aa58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20347
6996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.203476996
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.396680165
Short name T531
Test name
Test status
Simulation time 488449301 ps
CPU time 18.04 seconds
Started Jan 07 01:41:38 PM PST 24
Finished Jan 07 01:42:07 PM PST 24
Peak memory 246800 kb
Host smart-ed26bb0b-70be-48d0-b3e6-549455806105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39668
0165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.396680165
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3587988922
Short name T690
Test name
Test status
Simulation time 749109460 ps
CPU time 46.57 seconds
Started Jan 07 01:41:38 PM PST 24
Finished Jan 07 01:42:35 PM PST 24
Peak memory 255240 kb
Host smart-b429e3da-e8f7-4caa-a699-ab46a6485f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35879
88922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3587988922
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3319672420
Short name T17
Test name
Test status
Simulation time 116498378614 ps
CPU time 1748.91 seconds
Started Jan 07 01:41:37 PM PST 24
Finished Jan 07 02:10:57 PM PST 24
Peak memory 281572 kb
Host smart-999041a4-f9ed-44e7-ab94-e8b034321597
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319672420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3319672420
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2674802919
Short name T301
Test name
Test status
Simulation time 1086695189734 ps
CPU time 3420.62 seconds
Started Jan 07 01:41:36 PM PST 24
Finished Jan 07 02:38:46 PM PST 24
Peak memory 305436 kb
Host smart-c637439c-fba8-4919-9721-e770fe6e2b76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674802919 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2674802919
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.181006710
Short name T270
Test name
Test status
Simulation time 91824982201 ps
CPU time 1405.27 seconds
Started Jan 07 01:41:27 PM PST 24
Finished Jan 07 02:04:57 PM PST 24
Peak memory 272964 kb
Host smart-81a55c1c-9597-45ce-b258-61a5ec4ece6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181006710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.181006710
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3980623953
Short name T508
Test name
Test status
Simulation time 118671568 ps
CPU time 10.89 seconds
Started Jan 07 01:41:53 PM PST 24
Finished Jan 07 01:42:15 PM PST 24
Peak memory 255520 kb
Host smart-6563305e-f7d4-49a4-90db-b2ce91216fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39806
23953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3980623953
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.329840638
Short name T378
Test name
Test status
Simulation time 306965479 ps
CPU time 26.04 seconds
Started Jan 07 01:41:37 PM PST 24
Finished Jan 07 01:42:12 PM PST 24
Peak memory 247960 kb
Host smart-33fefcf5-a77f-4313-aea8-5ab77809476e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32984
0638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.329840638
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1786300415
Short name T121
Test name
Test status
Simulation time 181523932233 ps
CPU time 2520.25 seconds
Started Jan 07 01:42:08 PM PST 24
Finished Jan 07 02:24:18 PM PST 24
Peak memory 288896 kb
Host smart-6e375653-50c8-4a17-935d-3b6e63ce3743
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786300415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1786300415
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.4073417681
Short name T659
Test name
Test status
Simulation time 10057768860 ps
CPU time 415.72 seconds
Started Jan 07 01:41:55 PM PST 24
Finished Jan 07 01:49:01 PM PST 24
Peak memory 247636 kb
Host smart-00396014-2174-4239-a86d-200c943c2c92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073417681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.4073417681
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2358884201
Short name T266
Test name
Test status
Simulation time 500351875 ps
CPU time 6.73 seconds
Started Jan 07 01:41:31 PM PST 24
Finished Jan 07 01:41:43 PM PST 24
Peak memory 248600 kb
Host smart-759bf307-c9ce-48bf-84e1-db959ef32ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23588
84201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2358884201
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2551574610
Short name T83
Test name
Test status
Simulation time 501737688 ps
CPU time 21.98 seconds
Started Jan 07 01:42:01 PM PST 24
Finished Jan 07 01:42:32 PM PST 24
Peak memory 246928 kb
Host smart-c650cfa7-80d9-4801-ae05-1bd9ff0e2dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25515
74610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2551574610
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2880078251
Short name T304
Test name
Test status
Simulation time 167576605 ps
CPU time 6.51 seconds
Started Jan 07 01:41:55 PM PST 24
Finished Jan 07 01:42:11 PM PST 24
Peak memory 240588 kb
Host smart-b4b1af86-0807-4fad-9e78-8813bb72ee82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28800
78251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2880078251
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1766933143
Short name T695
Test name
Test status
Simulation time 104385753 ps
CPU time 11.02 seconds
Started Jan 07 01:41:48 PM PST 24
Finished Jan 07 01:42:12 PM PST 24
Peak memory 248744 kb
Host smart-405839f8-d526-4826-844a-cfc165fd206c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17669
33143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1766933143
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3071067533
Short name T277
Test name
Test status
Simulation time 113383453220 ps
CPU time 1868.43 seconds
Started Jan 07 01:42:12 PM PST 24
Finished Jan 07 02:13:29 PM PST 24
Peak memory 281552 kb
Host smart-04cdac5a-eac5-4fa6-bae3-4dd6700e4f78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071067533 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3071067533
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.120748798
Short name T677
Test name
Test status
Simulation time 49494948324 ps
CPU time 1355.18 seconds
Started Jan 07 01:42:33 PM PST 24
Finished Jan 07 02:05:23 PM PST 24
Peak memory 289148 kb
Host smart-9241b64e-626a-480d-bd26-b0a6fc9eadeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120748798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.120748798
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3218239952
Short name T685
Test name
Test status
Simulation time 2750438281 ps
CPU time 142.78 seconds
Started Jan 07 01:41:51 PM PST 24
Finished Jan 07 01:44:25 PM PST 24
Peak memory 256192 kb
Host smart-39335797-b612-49ff-acbe-dc7dfc8fc75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32182
39952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3218239952
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2085341302
Short name T53
Test name
Test status
Simulation time 3435755178 ps
CPU time 44.61 seconds
Started Jan 07 01:42:33 PM PST 24
Finished Jan 07 01:43:34 PM PST 24
Peak memory 255196 kb
Host smart-5bbb9a7c-1d15-44ec-a5ad-a298cf3ca150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20853
41302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2085341302
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1593263553
Short name T687
Test name
Test status
Simulation time 43907743220 ps
CPU time 813.83 seconds
Started Jan 07 01:42:14 PM PST 24
Finished Jan 07 01:55:57 PM PST 24
Peak memory 265096 kb
Host smart-b9f5f9ea-764b-48f8-bd23-bede2296b9de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593263553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1593263553
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2133879144
Short name T487
Test name
Test status
Simulation time 41803661629 ps
CPU time 2329.77 seconds
Started Jan 07 01:42:33 PM PST 24
Finished Jan 07 02:21:39 PM PST 24
Peak memory 281932 kb
Host smart-26c06ffe-deb3-426f-956c-e2c5d6ac6db0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133879144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2133879144
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1371933398
Short name T729
Test name
Test status
Simulation time 38125070138 ps
CPU time 410.09 seconds
Started Jan 07 01:41:55 PM PST 24
Finished Jan 07 01:48:55 PM PST 24
Peak memory 247472 kb
Host smart-f0a3eb71-a667-46d4-8cae-f0067fc08287
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371933398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1371933398
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2475713080
Short name T622
Test name
Test status
Simulation time 799956111 ps
CPU time 27.74 seconds
Started Jan 07 01:42:08 PM PST 24
Finished Jan 07 01:42:45 PM PST 24
Peak memory 255528 kb
Host smart-20f8343f-4d08-4f5c-a6fe-2063ab1d6dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24757
13080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2475713080
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.515084777
Short name T628
Test name
Test status
Simulation time 1287073406 ps
CPU time 27.76 seconds
Started Jan 07 01:42:00 PM PST 24
Finished Jan 07 01:42:37 PM PST 24
Peak memory 247092 kb
Host smart-c700b362-4ac7-42f7-a6b8-8e884e4b4de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51508
4777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.515084777
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.4138951875
Short name T715
Test name
Test status
Simulation time 331332267 ps
CPU time 6.5 seconds
Started Jan 07 01:42:30 PM PST 24
Finished Jan 07 01:42:54 PM PST 24
Peak memory 248636 kb
Host smart-142fd888-08f3-447e-859a-def35aea8f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41389
51875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.4138951875
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.475546322
Short name T623
Test name
Test status
Simulation time 4107046091 ps
CPU time 36.6 seconds
Started Jan 07 01:42:18 PM PST 24
Finished Jan 07 01:43:10 PM PST 24
Peak memory 248720 kb
Host smart-c31e3426-52f5-4bb7-aee1-63a67df8627f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47554
6322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.475546322
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2805148609
Short name T686
Test name
Test status
Simulation time 11227819886 ps
CPU time 425.53 seconds
Started Jan 07 01:42:32 PM PST 24
Finished Jan 07 01:49:53 PM PST 24
Peak memory 255896 kb
Host smart-ee30f139-710d-4bc0-9337-9cb89e86012d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805148609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2805148609
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1979724497
Short name T68
Test name
Test status
Simulation time 11306853008 ps
CPU time 583.71 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 01:52:05 PM PST 24
Peak memory 271460 kb
Host smart-4cbbd4eb-e1a5-45ca-abb9-62aba71abfd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979724497 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1979724497
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.793220662
Short name T196
Test name
Test status
Simulation time 40437159 ps
CPU time 2.32 seconds
Started Jan 07 01:40:25 PM PST 24
Finished Jan 07 01:40:51 PM PST 24
Peak memory 248776 kb
Host smart-d887ae97-6ec2-4a52-98d1-ba246296bbcc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=793220662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.793220662
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1319110818
Short name T428
Test name
Test status
Simulation time 18697877137 ps
CPU time 1510.9 seconds
Started Jan 07 01:40:41 PM PST 24
Finished Jan 07 02:06:19 PM PST 24
Peak memory 288916 kb
Host smart-ba925949-6933-418d-b7f3-355ce9b463b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319110818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1319110818
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3653991775
Short name T393
Test name
Test status
Simulation time 285600078 ps
CPU time 14.03 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:41:21 PM PST 24
Peak memory 240376 kb
Host smart-53c8fe48-ad3c-4b55-aba4-c3841b0887e1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3653991775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3653991775
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.145123795
Short name T421
Test name
Test status
Simulation time 3714951923 ps
CPU time 205.11 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 01:44:25 PM PST 24
Peak memory 255956 kb
Host smart-dc4be8a3-eb72-4e41-bcd0-b8c54ca786d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14512
3795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.145123795
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3857572898
Short name T494
Test name
Test status
Simulation time 1053773899 ps
CPU time 14.51 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 01:41:21 PM PST 24
Peak memory 248320 kb
Host smart-ebe737b0-1c4d-4460-9a1b-744a013dd135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38575
72898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3857572898
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3492487701
Short name T360
Test name
Test status
Simulation time 36058102590 ps
CPU time 1940.75 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 02:13:28 PM PST 24
Peak memory 285244 kb
Host smart-77f59d33-a016-40f0-9391-454e7e5667b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492487701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3492487701
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.4175111360
Short name T472
Test name
Test status
Simulation time 9960814435 ps
CPU time 769.92 seconds
Started Jan 07 01:40:27 PM PST 24
Finished Jan 07 01:53:39 PM PST 24
Peak memory 273116 kb
Host smart-08024787-7a64-4e57-b5d0-8e920ca6c48c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175111360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.4175111360
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.4294088690
Short name T325
Test name
Test status
Simulation time 40235363313 ps
CPU time 392.68 seconds
Started Jan 07 01:40:21 PM PST 24
Finished Jan 07 01:47:18 PM PST 24
Peak memory 255476 kb
Host smart-975278a1-af52-426d-b6c5-30398b51931d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294088690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.4294088690
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3447313528
Short name T480
Test name
Test status
Simulation time 6242426826 ps
CPU time 29.66 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 01:41:30 PM PST 24
Peak memory 248636 kb
Host smart-dd77ac71-2a69-43b9-a37e-53a066a3f607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34473
13528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3447313528
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2491312732
Short name T669
Test name
Test status
Simulation time 3018953058 ps
CPU time 43.28 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:41:51 PM PST 24
Peak memory 254404 kb
Host smart-97ba774a-0735-46b2-809c-5f9008ee8492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24913
12732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2491312732
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2278894877
Short name T572
Test name
Test status
Simulation time 586593283 ps
CPU time 30.38 seconds
Started Jan 07 01:40:19 PM PST 24
Finished Jan 07 01:41:14 PM PST 24
Peak memory 247036 kb
Host smart-033b3f6e-b7e7-4709-a0ef-4cbf63c1ad8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22788
94877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2278894877
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3266778755
Short name T550
Test name
Test status
Simulation time 288487002 ps
CPU time 16.43 seconds
Started Jan 07 01:40:24 PM PST 24
Finished Jan 07 01:41:04 PM PST 24
Peak memory 248760 kb
Host smart-96de3281-7dfe-4a59-80a9-e7975286b2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32667
78755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3266778755
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3103682730
Short name T635
Test name
Test status
Simulation time 11486592706 ps
CPU time 152.2 seconds
Started Jan 07 01:40:28 PM PST 24
Finished Jan 07 01:43:26 PM PST 24
Peak memory 256780 kb
Host smart-693c0b5c-3b6b-454e-9724-62499a792c50
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103682730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3103682730
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2744882212
Short name T111
Test name
Test status
Simulation time 30217983138 ps
CPU time 1392.11 seconds
Started Jan 07 01:40:31 PM PST 24
Finished Jan 07 02:04:09 PM PST 24
Peak memory 281628 kb
Host smart-c777022c-e2a8-45de-8112-9f916f05fe31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744882212 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2744882212
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2710671631
Short name T205
Test name
Test status
Simulation time 139344641 ps
CPU time 3.07 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 01:41:10 PM PST 24
Peak memory 248932 kb
Host smart-793b7503-dc2e-42d0-9c1a-88de5c28b00b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2710671631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2710671631
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3917891213
Short name T538
Test name
Test status
Simulation time 181149567498 ps
CPU time 1230.18 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 02:01:37 PM PST 24
Peak memory 289520 kb
Host smart-a7e71f36-6d84-4c96-a0ab-8ebb448d7a57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917891213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3917891213
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3073348056
Short name T653
Test name
Test status
Simulation time 1085973737 ps
CPU time 13.76 seconds
Started Jan 07 01:40:42 PM PST 24
Finished Jan 07 01:41:22 PM PST 24
Peak memory 240488 kb
Host smart-e584be3e-0548-434b-8f29-f47c034ba489
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3073348056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3073348056
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2525553095
Short name T55
Test name
Test status
Simulation time 2789682596 ps
CPU time 172.51 seconds
Started Jan 07 01:40:22 PM PST 24
Finished Jan 07 01:43:39 PM PST 24
Peak memory 249716 kb
Host smart-ceb5a26d-9182-48f6-b70c-f8fcbf91b23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25255
53095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2525553095
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3592194740
Short name T647
Test name
Test status
Simulation time 54336668 ps
CPU time 2.98 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 01:41:06 PM PST 24
Peak memory 238724 kb
Host smart-ba145b71-855a-4757-813c-0f80250126f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35921
94740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3592194740
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.4217621544
Short name T630
Test name
Test status
Simulation time 371784130760 ps
CPU time 2902.03 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 02:29:26 PM PST 24
Peak memory 285856 kb
Host smart-980d134b-cd97-4970-9a15-93c84d71c328
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217621544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.4217621544
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2224159038
Short name T260
Test name
Test status
Simulation time 28594030359 ps
CPU time 1232.04 seconds
Started Jan 07 01:40:41 PM PST 24
Finished Jan 07 02:01:40 PM PST 24
Peak memory 286840 kb
Host smart-3639867a-e2da-49b0-9505-7f54e82ee712
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224159038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2224159038
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1250352129
Short name T316
Test name
Test status
Simulation time 34007326024 ps
CPU time 347.1 seconds
Started Jan 07 01:40:45 PM PST 24
Finished Jan 07 01:46:59 PM PST 24
Peak memory 247528 kb
Host smart-e3a98424-b177-4dab-8737-cca47268f59b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250352129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1250352129
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1615206079
Short name T554
Test name
Test status
Simulation time 572575980 ps
CPU time 13.46 seconds
Started Jan 07 01:40:27 PM PST 24
Finished Jan 07 01:41:03 PM PST 24
Peak memory 248696 kb
Host smart-12d39f50-57d7-4da3-96cd-10ba1b9de382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16152
06079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1615206079
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2168411661
Short name T537
Test name
Test status
Simulation time 3763498981 ps
CPU time 56.97 seconds
Started Jan 07 01:40:44 PM PST 24
Finished Jan 07 01:42:08 PM PST 24
Peak memory 255168 kb
Host smart-f239341b-773f-4390-9513-3c2021055614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21684
11661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2168411661
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2884367057
Short name T396
Test name
Test status
Simulation time 706779810 ps
CPU time 45.92 seconds
Started Jan 07 01:40:22 PM PST 24
Finished Jan 07 01:41:32 PM PST 24
Peak memory 255184 kb
Host smart-7c89f8ab-2b9c-427d-88da-50cac184072f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28843
67057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2884367057
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4249210375
Short name T373
Test name
Test status
Simulation time 912740974 ps
CPU time 18.75 seconds
Started Jan 07 01:40:49 PM PST 24
Finished Jan 07 01:41:32 PM PST 24
Peak memory 248648 kb
Host smart-835362ad-23c8-4574-b61e-44404abb6e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42492
10375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4249210375
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.69207299
Short name T581
Test name
Test status
Simulation time 133553282151 ps
CPU time 2439.77 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 02:21:49 PM PST 24
Peak memory 289308 kb
Host smart-9988996e-ef83-4966-9781-cb759d01d8b0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69207299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handl
er_stress_all.69207299
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.205260987
Short name T298
Test name
Test status
Simulation time 357509289477 ps
CPU time 2689.68 seconds
Started Jan 07 01:40:29 PM PST 24
Finished Jan 07 02:25:44 PM PST 24
Peak memory 281604 kb
Host smart-1d20b483-b376-4373-ab88-fafadb7267c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205260987 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.205260987
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1358627200
Short name T201
Test name
Test status
Simulation time 26289795 ps
CPU time 2.66 seconds
Started Jan 07 01:40:44 PM PST 24
Finished Jan 07 01:41:13 PM PST 24
Peak memory 248776 kb
Host smart-4369f1f4-b874-4c60-9c31-540ba6a49383
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1358627200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1358627200
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3363154825
Short name T122
Test name
Test status
Simulation time 876780951787 ps
CPU time 2915.32 seconds
Started Jan 07 01:40:41 PM PST 24
Finished Jan 07 02:29:44 PM PST 24
Peak memory 280860 kb
Host smart-54243b85-ac80-40bb-a37e-9ab1d5d72025
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363154825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3363154825
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.4264787298
Short name T218
Test name
Test status
Simulation time 443907650 ps
CPU time 8.28 seconds
Started Jan 07 01:40:46 PM PST 24
Finished Jan 07 01:41:20 PM PST 24
Peak memory 240300 kb
Host smart-2541815b-f1c2-49df-8fd4-1f13bfe79300
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4264787298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.4264787298
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2559643443
Short name T633
Test name
Test status
Simulation time 1215135912 ps
CPU time 52.23 seconds
Started Jan 07 01:40:35 PM PST 24
Finished Jan 07 01:41:53 PM PST 24
Peak memory 248568 kb
Host smart-4fd69d11-6409-44dc-87e2-41cd0411384b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25596
43443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2559643443
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.807720941
Short name T646
Test name
Test status
Simulation time 706218198 ps
CPU time 39.81 seconds
Started Jan 07 01:40:42 PM PST 24
Finished Jan 07 01:41:49 PM PST 24
Peak memory 254404 kb
Host smart-b1d11162-c076-452c-acc4-0ccf277628d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80772
0941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.807720941
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1447741369
Short name T47
Test name
Test status
Simulation time 59589236433 ps
CPU time 1224.66 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 02:01:30 PM PST 24
Peak memory 287172 kb
Host smart-fbe25c85-a2a2-447b-8d03-7432250facaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447741369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1447741369
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.295651669
Short name T564
Test name
Test status
Simulation time 280321528415 ps
CPU time 2041.76 seconds
Started Jan 07 01:40:44 PM PST 24
Finished Jan 07 02:15:12 PM PST 24
Peak memory 272216 kb
Host smart-26eca916-294b-4815-80db-7dca1bdb659b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295651669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.295651669
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2804850035
Short name T50
Test name
Test status
Simulation time 6659604083 ps
CPU time 259.66 seconds
Started Jan 07 01:40:47 PM PST 24
Finished Jan 07 01:45:32 PM PST 24
Peak memory 248716 kb
Host smart-fce56903-89dd-4911-b7c4-169b013fa942
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804850035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2804850035
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3099096795
Short name T471
Test name
Test status
Simulation time 849467399 ps
CPU time 53.99 seconds
Started Jan 07 01:40:32 PM PST 24
Finished Jan 07 01:41:52 PM PST 24
Peak memory 256816 kb
Host smart-3faa0d11-d681-473a-8500-c022a795371e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30990
96795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3099096795
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3901179427
Short name T505
Test name
Test status
Simulation time 6439324217 ps
CPU time 42.62 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 01:41:49 PM PST 24
Peak memory 254692 kb
Host smart-7c3e542b-9a42-4385-b2d3-d0985c3b44a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39011
79427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3901179427
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3594363322
Short name T299
Test name
Test status
Simulation time 1033071066 ps
CPU time 56.6 seconds
Started Jan 07 01:40:35 PM PST 24
Finished Jan 07 01:41:58 PM PST 24
Peak memory 248580 kb
Host smart-d624e472-5264-4c85-b9d3-41aebe66477e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35943
63322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3594363322
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2138669002
Short name T594
Test name
Test status
Simulation time 2508131702 ps
CPU time 35.95 seconds
Started Jan 07 01:40:33 PM PST 24
Finished Jan 07 01:41:35 PM PST 24
Peak memory 248752 kb
Host smart-913a7a63-1341-4bf1-bd25-fb142275525c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21386
69002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2138669002
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2911275196
Short name T443
Test name
Test status
Simulation time 36780236379 ps
CPU time 164.95 seconds
Started Jan 07 01:40:36 PM PST 24
Finished Jan 07 01:43:47 PM PST 24
Peak memory 256936 kb
Host smart-9a5cf947-e426-4d0c-84d7-3f69ec24358f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911275196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2911275196
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1412176758
Short name T639
Test name
Test status
Simulation time 196325073749 ps
CPU time 2646.76 seconds
Started Jan 07 01:40:32 PM PST 24
Finished Jan 07 02:25:05 PM PST 24
Peak memory 283064 kb
Host smart-47172749-468e-4f81-bd56-9d8bc98b4a89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412176758 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1412176758
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.671769611
Short name T204
Test name
Test status
Simulation time 13253633 ps
CPU time 2.24 seconds
Started Jan 07 01:40:23 PM PST 24
Finished Jan 07 01:40:49 PM PST 24
Peak memory 248892 kb
Host smart-988f00fe-8def-4342-b2cf-e660da385a99
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=671769611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.671769611
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3773992254
Short name T709
Test name
Test status
Simulation time 483640576305 ps
CPU time 2287.59 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 02:19:18 PM PST 24
Peak memory 289712 kb
Host smart-146f96bd-dcfb-44d3-a5ba-388a02a553a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773992254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3773992254
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2319040652
Short name T450
Test name
Test status
Simulation time 546949184 ps
CPU time 14.24 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 01:41:19 PM PST 24
Peak memory 240404 kb
Host smart-ab1557ae-74ff-4eb7-b8c4-659a9ed81e9e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2319040652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2319040652
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2399452306
Short name T624
Test name
Test status
Simulation time 13969905583 ps
CPU time 228.09 seconds
Started Jan 07 01:40:46 PM PST 24
Finished Jan 07 01:45:00 PM PST 24
Peak memory 256752 kb
Host smart-78f522f0-8c65-4c22-b73b-4f3a4ac75dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23994
52306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2399452306
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.415367817
Short name T452
Test name
Test status
Simulation time 3260072519 ps
CPU time 47.34 seconds
Started Jan 07 01:40:31 PM PST 24
Finished Jan 07 01:41:44 PM PST 24
Peak memory 255828 kb
Host smart-d05dd34c-f9f8-4a80-9ab2-aa2e5055a7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41536
7817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.415367817
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1586354918
Short name T349
Test name
Test status
Simulation time 44523809418 ps
CPU time 2376.22 seconds
Started Jan 07 01:40:30 PM PST 24
Finished Jan 07 02:20:32 PM PST 24
Peak memory 284460 kb
Host smart-d01de2e8-be4a-4db9-83b8-207b99685e47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586354918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1586354918
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.335904990
Short name T399
Test name
Test status
Simulation time 47518047545 ps
CPU time 979.62 seconds
Started Jan 07 01:40:42 PM PST 24
Finished Jan 07 01:57:29 PM PST 24
Peak memory 273164 kb
Host smart-fb419f1f-f8ad-40c3-9869-6973d6acdd68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335904990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.335904990
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1809891031
Short name T477
Test name
Test status
Simulation time 24126763682 ps
CPU time 244.86 seconds
Started Jan 07 01:40:47 PM PST 24
Finished Jan 07 01:45:17 PM PST 24
Peak memory 247508 kb
Host smart-1eef36f8-5f0a-4ae0-962b-b43f65f0ef15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809891031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1809891031
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3666933204
Short name T662
Test name
Test status
Simulation time 1015268864 ps
CPU time 17.48 seconds
Started Jan 07 01:40:35 PM PST 24
Finished Jan 07 01:41:19 PM PST 24
Peak memory 248580 kb
Host smart-50aad037-c7f8-4d29-808a-a3b58f12426c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36669
33204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3666933204
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3407612999
Short name T103
Test name
Test status
Simulation time 126578458 ps
CPU time 16.45 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 01:41:16 PM PST 24
Peak memory 255532 kb
Host smart-c32ef6b0-3d9b-43e8-a090-f0928fb52e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34076
12999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3407612999
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.409368510
Short name T242
Test name
Test status
Simulation time 1548860766 ps
CPU time 25.1 seconds
Started Jan 07 01:40:46 PM PST 24
Finished Jan 07 01:41:37 PM PST 24
Peak memory 253272 kb
Host smart-ef232707-5d4c-40df-bc53-7e8c3d628868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40936
8510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.409368510
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3621265443
Short name T446
Test name
Test status
Simulation time 176738655 ps
CPU time 4.27 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 01:41:08 PM PST 24
Peak memory 240408 kb
Host smart-bbda6e7b-2b3c-4951-b651-0f3e6bf532dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36212
65443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3621265443
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2925317076
Short name T282
Test name
Test status
Simulation time 178618008220 ps
CPU time 2602.25 seconds
Started Jan 07 01:40:35 PM PST 24
Finished Jan 07 02:24:24 PM PST 24
Peak memory 289408 kb
Host smart-49704f12-f095-42f9-89c2-af8e80ade5c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925317076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2925317076
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.551556274
Short name T238
Test name
Test status
Simulation time 827099769214 ps
CPU time 4491.44 seconds
Started Jan 07 01:40:37 PM PST 24
Finished Jan 07 02:55:56 PM PST 24
Peak memory 315320 kb
Host smart-c43043c0-41dd-47a5-94c1-4ec4d0fb7008
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551556274 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.551556274
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.829306199
Short name T194
Test name
Test status
Simulation time 134273244 ps
CPU time 1.94 seconds
Started Jan 07 01:40:24 PM PST 24
Finished Jan 07 01:40:50 PM PST 24
Peak memory 248840 kb
Host smart-3f0f3aa6-d6a5-4b4a-b592-649673b5275a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=829306199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.829306199
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2809133947
Short name T567
Test name
Test status
Simulation time 32241957351 ps
CPU time 1519.26 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 02:06:24 PM PST 24
Peak memory 289168 kb
Host smart-9178f6e6-93f9-45a2-ad7c-7e48422fb955
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809133947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2809133947
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.335331973
Short name T376
Test name
Test status
Simulation time 1154767599 ps
CPU time 48.68 seconds
Started Jan 07 01:40:25 PM PST 24
Finished Jan 07 01:41:37 PM PST 24
Peak memory 240440 kb
Host smart-0f076929-9bbd-49ad-8f6f-7af162c5e5c4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=335331973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.335331973
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4129102000
Short name T398
Test name
Test status
Simulation time 4887519961 ps
CPU time 268.87 seconds
Started Jan 07 01:40:23 PM PST 24
Finished Jan 07 01:45:16 PM PST 24
Peak memory 256272 kb
Host smart-4ece44ad-92a0-4c68-bfc8-05cb6deff7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41291
02000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4129102000
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3523482675
Short name T432
Test name
Test status
Simulation time 1049790237 ps
CPU time 22.98 seconds
Started Jan 07 01:40:27 PM PST 24
Finished Jan 07 01:41:12 PM PST 24
Peak memory 254332 kb
Host smart-3820f55f-f0f6-4845-a5a9-62e56e272d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35234
82675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3523482675
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2189841048
Short name T345
Test name
Test status
Simulation time 64209041606 ps
CPU time 1289.94 seconds
Started Jan 07 01:40:43 PM PST 24
Finished Jan 07 02:02:40 PM PST 24
Peak memory 289352 kb
Host smart-e77f1ddd-15c0-47e7-a8bf-03e1a73d998d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189841048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2189841048
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.584862046
Short name T386
Test name
Test status
Simulation time 34642001647 ps
CPU time 2266.87 seconds
Started Jan 07 01:40:47 PM PST 24
Finished Jan 07 02:19:00 PM PST 24
Peak memory 289436 kb
Host smart-0062714f-5728-4d2e-b25c-f02a7d66196b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584862046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.584862046
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2384400769
Short name T117
Test name
Test status
Simulation time 2065707240 ps
CPU time 83.79 seconds
Started Jan 07 01:40:38 PM PST 24
Finished Jan 07 01:42:29 PM PST 24
Peak memory 246500 kb
Host smart-72ba7317-a597-434c-bf51-7564be9bfe88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384400769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2384400769
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2937985942
Short name T470
Test name
Test status
Simulation time 276529093 ps
CPU time 16.4 seconds
Started Jan 07 01:40:34 PM PST 24
Finished Jan 07 01:41:16 PM PST 24
Peak memory 248656 kb
Host smart-469e1569-9dbd-4a76-9d31-e6363370cf73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29379
85942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2937985942
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2507447809
Short name T592
Test name
Test status
Simulation time 132549806 ps
CPU time 17.62 seconds
Started Jan 07 01:40:19 PM PST 24
Finished Jan 07 01:41:03 PM PST 24
Peak memory 246880 kb
Host smart-433d84ad-f6b8-42c7-a2c9-d95a9b5c752b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25074
47809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2507447809
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2511212637
Short name T261
Test name
Test status
Simulation time 6575113699 ps
CPU time 54.35 seconds
Started Jan 07 01:40:33 PM PST 24
Finished Jan 07 01:41:54 PM PST 24
Peak memory 255672 kb
Host smart-41668c78-6d09-468f-852d-f2aca16abc3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25112
12637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2511212637
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1555573711
Short name T575
Test name
Test status
Simulation time 506569965 ps
CPU time 34.5 seconds
Started Jan 07 01:40:40 PM PST 24
Finished Jan 07 01:41:41 PM PST 24
Peak memory 248540 kb
Host smart-6e1175a3-1c26-4edb-8083-cf0dc547830a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15555
73711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1555573711
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2236879523
Short name T430
Test name
Test status
Simulation time 4104900323 ps
CPU time 231.75 seconds
Started Jan 07 01:40:39 PM PST 24
Finished Jan 07 01:44:58 PM PST 24
Peak memory 250816 kb
Host smart-c1fa4ee8-9cf1-48fd-9551-967a5122c573
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236879523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2236879523
Directory /workspace/9.alert_handler_stress_all/latest
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