Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	60743	1			T4	5		T54	10		T19	297
class_i[0x1]	86596	1			T1	3041		T3	8		T53	3202
class_i[0x2]	74691	1			T5	2949		T26	1		T19	1
class_i[0x3]	76790	1			T22	1586		T54	9		T19	21

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	78176	1			T1	820		T4	1		T22	16
alert[0x1]	72595	1			T1	719		T4	4		T22	17
alert[0x2]	74846	1			T1	736		T22	19		T5	700
alert[0x3]	73203	1			T1	766		T3	8		T22	1534

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

298571

1

T1

3041

T3

8

T4

5

esc_ping_fail

249

1

T11

3

T12

8

T13

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	78115	1			T1	820		T4	1		T22	16
esc_integrity_fail	alert[0x1]	72525	1			T1	719		T4	4		T22	17
esc_integrity_fail	alert[0x2]	74783	1			T1	736		T22	19		T5	700
esc_integrity_fail	alert[0x3]	73148	1			T1	766		T3	8		T22	1534
esc_ping_fail	alert[0x0]	61	1			T11	2		T12	1		T13	2
esc_ping_fail	alert[0x1]	70	1			T11	1		T12	2		T13	1
esc_ping_fail	alert[0x2]	63	1			T12	3		T13	1		T304	1
esc_ping_fail	alert[0x3]	55	1			T12	2		T13	2		T304	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	60672	1			T4	5		T54	10		T19	297
esc_integrity_fail	class_i[0x1]	86538	1			T1	3041		T3	8		T53	3202
esc_integrity_fail	class_i[0x2]	74634	1			T5	2949		T26	1		T19	1
esc_integrity_fail	class_i[0x3]	76727	1			T22	1586		T54	9		T19	21
esc_ping_fail	class_i[0x0]	71	1			T102	7		T104	4		T314	2
esc_ping_fail	class_i[0x1]	58	1			T13	5		T306	2		T218	3
esc_ping_fail	class_i[0x2]	57	1			T11	3		T12	8		T13	1
esc_ping_fail	class_i[0x3]	63	1			T306	2		T314	3		T315	1