Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	708017839	0	0	642
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	708017839	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	708017839	707856020	0	0
tb.dut.CheckAccuCntDw	0	0	642	642	0	0
tb.dut.CheckEscCntDw	0	0	642	642	0	0
tb.dut.CheckNAlerts	0	0	642	642	0	0
tb.dut.CheckNClasses	0	0	642	642	0	0
tb.dut.CheckNEscSev	0	0	642	642	0	0
tb.dut.CrashdumpKnownO_A	0	0	708017839	707856020	0	0
tb.dut.EdnKnownO_A	0	0	708017839	707856020	0	0
tb.dut.EscPKnownO_A	0	0	708017839	707856020	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	708017839	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	708017839	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	708017839	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	708017839	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	708017839	70	0	0
tb.dut.IrqAKnownO_A	0	0	708017839	707856020	0	0
tb.dut.IrqBKnownO_A	0	0	708017839	707856020	0	0
tb.dut.IrqCKnownO_A	0	0	708017839	707856020	0	0
tb.dut.IrqDKnownO_A	0	0	708017839	707856020	0	0
tb.dut.TlAReadyKnownO_A	0	0	708017839	707856020	0	0
tb.dut.TlDValidKnownO_A	0	0	708017839	707856020	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	731506101	4301797	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	731506101	17531	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	731506101	17546	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	731506101	16822	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	731506101	18054	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	731506101	17159	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	731506101	18929	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	731506101	17781	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	731506101	18114	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	731506101	16303	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	731506101	19319	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	731506101	17891	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	731506101	16873	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	731506101	18441	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	731506101	17713	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	731506101	17330	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	731506101	17651	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	731506101	18387	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	731506101	17473	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	731506101	20019	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	731506101	16589	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	731506101	18066	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	731506101	19056	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	731506101	18712	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	731506101	17843	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	731506101	19524	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	731506101	17831	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	731506101	17155	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	731506101	18530	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	731506101	18212	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	731506101	18354	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	731506101	18225	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	731506101	18440	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	731506101	17654	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	731506101	16878	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	731506101	18265	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	731506101	18854	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	731506101	19348	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	731506101	18047	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	731506101	20497	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	731506101	17794	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	731506101	19037	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	731506101	17297	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	731506101	18135	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	731506101	18186	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	731506101	18212	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	731506101	19956	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	731506101	18207	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	731506101	19282	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	731506101	16532	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	731506101	16963	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	731506101	18141	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	731506101	19448	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	731506101	16439	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	731506101	17770	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	731506101	17890	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	731506101	19005	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	731506101	18481	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	731506101	18081	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	731506101	18611	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	731506101	19219	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	731506101	17458	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	731506101	19238	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	731506101	17178	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	731506101	17756	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	731506101	17832	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	731506101	17149	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	731506101	18091	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	731506101	17334	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	731506101	16665	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	731506101	32148	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	731506101	19247	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	731506101	18664	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	731506101	16829	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	731506101	17659	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	731506101	17275	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	731506101	17809	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	731506101	17584	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	731506101	19223	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	708017839	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	708017839	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	708017839	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	708017839	1874	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	708017839	224424	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	708017839	339881331	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	708017839	209	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	708017839	846	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	708017839	48	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	708017839	388	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	707851430	233166761	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	708017839	953	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	708017839	940	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	708017839	924	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	708017839	908	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	708017839	1342	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	708017839	145849	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	708017839	1225	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	708017839	69	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	708017839	1241	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	708017839	1031	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	642	642	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	708017839	707856020	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	708017839	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	708017839	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	708017839	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	708017839	4368	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	708017839	206465	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	708017839	395887621	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	708017839	250	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	708017839	504	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	708017839	31	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	708017839	219	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	707851430	322716761	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	708017839	586	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	708017839	575	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	708017839	560	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	708017839	553	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	708017839	1730	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	708017839	170070	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	708017839	1641	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	708017839	58	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	708017839	1313	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	708017839	1103	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	642	642	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	708017839	707856020	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	708017839	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	708017839	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	708017839	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	708017839	1546	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	708017839	205628	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	708017839	388220274	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	708017839	213	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	708017839	504	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	708017839	13	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	708017839	219	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	707851430	293702857	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	708017839	579	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	708017839	574	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	708017839	565	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	708017839	554	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	708017839	1634	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	708017839	168926	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	708017839	1548	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	708017839	73	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	708017839	1222	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	708017839	1012	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	642	642	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	708017839	707856020	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	708017839	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	708017839	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	708017839	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	708017839	5294	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	708017839	202915	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	708017839	389355261	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	708017839	231	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	708017839	479	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	708017839	17	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	708017839	212	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	707851430	329863001	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	708017839	563	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	708017839	553	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	708017839	549	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	708017839	540	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	708017839	1856	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	708017839	179379	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	708017839	1771	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	708017839	68	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	708017839	1235	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	708017839	1025	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	642	642	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	708017839	707856020	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	731506101	157303931	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	731506101	730868811	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	731506101	730868811	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	731506101	197244856	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	731506101	730868811	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	731506101	730868811	0	0
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