Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.04	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	7	33	82.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	7	33	82.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	69	1			T22	1		T25	1		T53	1
class_index[0x1]	58	1			T1	1		T22	1		T19	1
class_index[0x2]	73	1			T53	1		T58	5		T61	1
class_index[0x3]	68	1			T22	1		T19	1		T27	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	96	1			T22	1		T53	1		T19	1
intr_timeout_cnt[1]	59	1			T25	1		T53	1		T19	1
intr_timeout_cnt[2]	41	1			T81	1		T58	1		T82	2
intr_timeout_cnt[3]	16	1			T43	3		T82	1		T64	1
intr_timeout_cnt[4]	18	1			T1	1		T57	1		T87	3
intr_timeout_cnt[5]	8	1			T237	2		T238	1		T239	1
intr_timeout_cnt[6]	9	1			T240	1		T120	3		T241	1
intr_timeout_cnt[7]	7	1			T107	1		T242	1		T237	1
intr_timeout_cnt[8]	9	1			T22	2		T107	1		T243	1
intr_timeout_cnt[9]	5	1			T126	1		T68	1		T244	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	7	33	82.50	7

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[6] , intr_timeout_cnt[7]]	--	--	2
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[6]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T47	1		T80	1		T110	1
class_index[0x0]	intr_timeout_cnt[1]	14	1			T25	1		T53	1		T51	1
class_index[0x0]	intr_timeout_cnt[2]	15	1			T81	1		T82	1		T91	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T43	1		T64	1		T71	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T237	2		T239	1		T245	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T22	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	16	1			T22	1		T83	1		T84	1
class_index[0x1]	intr_timeout_cnt[1]	11	1			T19	1		T64	1		T87	2
class_index[0x1]	intr_timeout_cnt[2]	10	1			T121	1		T243	1		T246	2
class_index[0x1]	intr_timeout_cnt[3]	4	1			T43	2		T82	1		T247	1
class_index[0x1]	intr_timeout_cnt[4]	10	1			T1	1		T57	1		T87	3
class_index[0x1]	intr_timeout_cnt[5]	1	1			T248	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T237	1		T245	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	4	1			T107	1		T249	1		T250	1
class_index[0x2]	intr_timeout_cnt[0]	26	1			T53	1		T58	4		T61	1
class_index[0x2]	intr_timeout_cnt[1]	12	1			T42	2		T87	2		T121	1
class_index[0x2]	intr_timeout_cnt[2]	11	1			T58	1		T82	1		T107	1
class_index[0x2]	intr_timeout_cnt[3]	1	1			T212	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	6	1			T119	1		T251	3		T252	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T238	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	9	1			T240	1		T120	3		T241	1
class_index[0x2]	intr_timeout_cnt[7]	3	1			T242	1		T253	1		T254	1
class_index[0x2]	intr_timeout_cnt[8]	2	1			T243	1		T255	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T244	1		T256	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	24	1			T19	1		T27	1		T57	1
class_index[0x3]	intr_timeout_cnt[1]	22	1			T61	1		T100	1		T216	1
class_index[0x3]	intr_timeout_cnt[2]	5	1			T107	1		T257	2		T258	1
class_index[0x3]	intr_timeout_cnt[3]	6	1			T250	1		T239	1		T259	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T260	1		T261	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	2	1			T262	1		T263	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T107	1		T252	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T22	1		T264	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	3	1			T126	1		T68	1		T265	1