Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	378734	1			T17	4		T29	8		T30	4
all_values[1]	378734	1			T17	4		T29	8		T30	4
all_values[2]	378734	1			T17	4		T29	8		T30	4
all_values[3]	378734	1			T17	4		T29	8		T30	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

753773

1

T17

6

T29

17

T30

10

auto[1]

761163

1

T17

10

T29

15

T30

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

901191

1

T17

13

T29

23

T30

11

auto[1]

613745

1

T17

3

T29

9

T30

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	108435	1			T17	2		T29	4		T32	1
all_values[0]	auto[0]	auto[1]	79846	1			T29	1		T30	2		T228	2
all_values[0]	auto[1]	auto[0]	110101	1			T17	2		T29	1		T30	2
all_values[0]	auto[1]	auto[1]	80352	1			T29	2		T186	1		T226	1
all_values[1]	auto[0]	auto[0]	111563	1			T17	2		T29	3		T30	3
all_values[1]	auto[0]	auto[1]	77205	1			T29	3		T30	1		T186	3
all_values[1]	auto[1]	auto[0]	112686	1			T17	2		T29	2		T186	2
all_values[1]	auto[1]	auto[1]	77280	1			T227	2		T357	1		T358	4
all_values[2]	auto[0]	auto[0]	114508	1			T17	1		T29	1		T30	3
all_values[2]	auto[0]	auto[1]	73392	1			T29	1		T227	1		T359	2
all_values[2]	auto[1]	auto[0]	116605	1			T17	2		T29	4		T186	5
all_values[2]	auto[1]	auto[1]	74229	1			T17	1		T29	2		T30	1
all_values[3]	auto[0]	auto[0]	113011	1			T29	4		T30	1		T32	1
all_values[3]	auto[0]	auto[1]	75813	1			T17	1		T186	2		T227	3
all_values[3]	auto[1]	auto[0]	114282	1			T17	2		T29	4		T30	2
all_values[3]	auto[1]	auto[1]	75628	1			T17	1		T30	1		T226	3