Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	378734	1			T17	4		T29	8		T30	4
all_pins[1]	378734	1			T17	4		T29	8		T30	4
all_pins[2]	378734	1			T17	4		T29	8		T30	4
all_pins[3]	378734	1			T17	4		T29	8		T30	4

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1207447	1			T17	14		T29	28		T30	14
values[0x1]	307489	1			T17	2		T29	4		T30	2
transitions[0x0=>0x1]	203951	1			T17	2		T29	3		T30	1
transitions[0x1=>0x0]	204206	1			T17	2		T29	4		T30	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	298382	1			T17	4		T29	6		T30	4
all_pins[0]	values[0x1]	80352	1			T29	2		T186	1		T226	1
all_pins[0]	transitions[0x0=>0x1]	79655	1			T29	1		T226	1		T227	1
all_pins[0]	transitions[0x1=>0x0]	75186	1			T17	1		T30	1		T226	3
all_pins[1]	values[0x0]	301454	1			T17	4		T29	8		T30	4
all_pins[1]	values[0x1]	77280	1			T227	2		T357	1		T358	4
all_pins[1]	transitions[0x0=>0x1]	42381	1			T227	2		T357	1		T358	3
all_pins[1]	transitions[0x1=>0x0]	45453	1			T29	2		T186	1		T226	1
all_pins[2]	values[0x0]	304505	1			T17	3		T29	6		T30	3
all_pins[2]	values[0x1]	74229	1			T17	1		T29	2		T30	1
all_pins[2]	transitions[0x0=>0x1]	39884	1			T17	1		T29	2		T30	1
all_pins[2]	transitions[0x1=>0x0]	42935	1			T227	2		T357	1		T358	4
all_pins[3]	values[0x0]	303106	1			T17	3		T29	8		T30	3
all_pins[3]	values[0x1]	75628	1			T17	1		T30	1		T226	3
all_pins[3]	transitions[0x0=>0x1]	42031	1			T17	1		T226	2		T227	1
all_pins[3]	transitions[0x1=>0x0]	40632	1			T17	1		T29	2		T359	2