Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1			T17	4		T29	7		T30	4
all_values[1]	281	1			T17	4		T29	7		T30	4
all_values[2]	281	1			T17	4		T29	7		T30	4
all_values[3]	281	1			T17	4		T29	7		T30	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

616

1

T17

9

T29

15

T30

10

auto[1]

508

1

T17

7

T29

13

T30

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

498

1

T17

8

T29

13

T30

7

auto[1]

626

1

T17

8

T29

15

T30

9

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

709

1

T17

9

T29

16

T30

8

auto[1]

415

1

T17

7

T29

12

T30

8

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

77

1

T17

2

T29

2

T186

2

all_values[0]

auto[0]

auto[0]

auto[1]

25

1

T226

1

T358

1

T360

1

all_values[0]

auto[0]

auto[1]

auto[0]

53

1

T17

1

T30

1

T186

4

all_values[0]

auto[0]

auto[1]

auto[1]

24

1

T29

1

T227

1

T358

1

all_values[0]

auto[1]

auto[0]

auto[1]

56

1

T17

1

T29

3

T30

3

all_values[0]

auto[1]

auto[1]

auto[1]

46

1

T29

1

T226

1

T227

2

all_values[1]

auto[0]

auto[0]

auto[0]

75

1

T17

2

T30

2

T186

2

all_values[1]

auto[0]

auto[0]

auto[1]

28

1

T29

1

T186

2

T357

1

all_values[1]

auto[0]

auto[1]

auto[0]

50

1

T17

1

T29

3

T186

1

all_values[1]

auto[0]

auto[1]

auto[1]

27

1

T227

2

T358

1

T360

1

all_values[1]

auto[1]

auto[0]

auto[1]

60

1

T17

1

T29

3

T30

2

all_values[1]

auto[1]

auto[1]

auto[1]

41

1

T226

1

T358

2

T361

1

all_values[2]

auto[0]

auto[0]

auto[0]

65

1

T29

1

T30

2

T186

4

all_values[2]

auto[0]

auto[0]

auto[1]

27

1

T359

1

T358

2

T361

1

all_values[2]

auto[0]

auto[1]

auto[0]

52

1

T17

1

T29

2

T186

2

all_values[2]

auto[0]

auto[1]

auto[1]

31

1

T29

1

T359

1

T228

1

all_values[2]

auto[1]

auto[0]

auto[1]

59

1

T17

1

T29

2

T226

1

all_values[2]

auto[1]

auto[1]

auto[1]

47

1

T17

2

T29

1

T30

2

all_values[3]

auto[0]

auto[0]

auto[0]

60

1

T29

2

T30

1

T186

4

all_values[3]

auto[0]

auto[0]

auto[1]

25

1

T17

1

T227

2

T228

1

all_values[3]

auto[0]

auto[1]

auto[0]

66

1

T17

1

T29

3

T30

1

all_values[3]

auto[0]

auto[1]

auto[1]

24

1

T30

1

T226

1

T359

1

all_values[3]

auto[1]

auto[0]

auto[1]

59

1

T17

1

T29

1

T186

2

all_values[3]

auto[1]

auto[1]

auto[1]

47

1

T17

1

T29

1

T30

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal