Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	87623	1			T1	2269		T5	406		T18	329
accum_cnt_1000	259862	1			T1	4712		T3	1259		T4	1909
accum_cnt_100	30531	1			T1	372		T3	256		T4	139
accum_cnt_50	74139	1			T1	287		T3	622		T4	105
accum_cnt_10	184047	1			T1	5219		T3	1857		T4	32
accum_cnt_0	438272	1			T1	4939		T2	72		T3	5634

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	279154	1			T1	4807		T2	18		T3	2407
class_index[0x1]	279154	1			T1	4807		T2	18		T3	2407
class_index[0x2]	279153	1			T1	4807		T2	18		T3	2407
class_index[0x3]	279153	1			T1	4807		T2	18		T3	2407

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25052	1			T1	411		T5	37		T18	329
class_index[0x0]	accum_cnt_1000	72308	1			T1	1501		T3	184		T4	626
class_index[0x0]	accum_cnt_100	9464	1			T1	129		T3	38		T4	55
class_index[0x0]	accum_cnt_50	20720	1			T1	80		T3	32		T4	35
class_index[0x0]	accum_cnt_10	58897	1			T1	1429		T3	1743		T4	13
class_index[0x0]	accum_cnt_0	84268	1			T1	1257		T2	18		T3	410
class_index[0x1]	accum_cnt_2000	19335	1			T1	535		T5	95		T53	279
class_index[0x1]	accum_cnt_1000	59218	1			T1	510		T3	61		T4	644
class_index[0x1]	accum_cnt_100	6300	1			T1	69		T3	88		T4	40
class_index[0x1]	accum_cnt_50	14658	1			T1	75		T3	466		T4	33
class_index[0x1]	accum_cnt_10	48494	1			T1	2128		T3	30		T4	10
class_index[0x1]	accum_cnt_0	117967	1			T1	60		T2	18		T3	1762
class_index[0x2]	accum_cnt_2000	19034	1			T1	896		T6	499		T53	47
class_index[0x2]	accum_cnt_1000	61441	1			T1	1758		T3	492		T4	639
class_index[0x2]	accum_cnt_100	7696	1			T1	134		T3	72		T4	44
class_index[0x2]	accum_cnt_50	23013	1			T1	84		T3	81		T4	37
class_index[0x2]	accum_cnt_10	37202	1			T1	26		T3	30		T4	8
class_index[0x2]	accum_cnt_0	118913	1			T1	1909		T2	18		T3	1732
class_index[0x3]	accum_cnt_2000	24202	1			T1	427		T5	274		T53	138
class_index[0x3]	accum_cnt_1000	66895	1			T1	943		T3	522		T22	1
class_index[0x3]	accum_cnt_100	7071	1			T1	40		T3	58		T5	26
class_index[0x3]	accum_cnt_50	15748	1			T1	48		T3	43		T22	9
class_index[0x3]	accum_cnt_10	39454	1			T1	1636		T3	54		T4	1
class_index[0x3]	accum_cnt_0	117124	1			T1	1713		T2	18		T3	1730