Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4357	1			T1	131		T20	794		T27	50
alert[0x1]	8674	1			T4	479		T43	19		T125	1
alert[0x2]	7666	1			T3	3		T4	21		T76	26
alert[0x3]	4884	1			T1	1002		T27	96		T76	13
alert[0x4]	5880	1			T1	20		T20	194		T56	2
alert[0x5]	6719	1			T1	116		T22	25		T26	6
alert[0x6]	10809	1			T19	1		T61	85		T65	65
alert[0x7]	6260	1			T1	29		T12	1		T294	90
alert[0x8]	4094	1			T1	6		T125	1		T294	865
alert[0x9]	11661	1			T4	129		T126	128		T61	43
alert[0xa]	5391	1			T1	208		T20	345		T210	2
alert[0xb]	19882	1			T20	6424		T76	9		T56	20
alert[0xc]	7369	1			T1	142		T54	36		T20	230
alert[0xd]	7963	1			T1	213		T20	39		T76	15
alert[0xe]	2773	1			T20	423		T56	351		T79	2
alert[0xf]	9013	1			T4	101		T20	1109		T56	21
alert[0x10]	2350	1			T19	1		T11	2		T12	1
alert[0x11]	2165	1			T1	59		T4	53		T56	25
alert[0x12]	9345	1			T19	4		T76	4		T56	276
alert[0x13]	4307	1			T1	168		T20	36		T294	99
alert[0x14]	6627	1			T4	37		T22	5		T19	6
alert[0x15]	4738	1			T4	947		T20	5		T27	10
alert[0x16]	12114	1			T20	871		T43	4		T9	1
alert[0x17]	12272	1			T1	592		T27	2		T12	1
alert[0x18]	6591	1			T1	81		T3	7		T20	1
alert[0x19]	11300	1			T20	4778		T13	1		T294	622
alert[0x1a]	5353	1			T20	527		T56	7		T294	611
alert[0x1b]	7971	1			T26	1		T20	152		T56	2883
alert[0x1c]	7370	1			T3	6		T22	1		T76	12
alert[0x1d]	7835	1			T4	17		T294	3218		T126	108
alert[0x1e]	6700	1			T76	156		T294	200		T304	1
alert[0x1f]	6750	1			T27	20		T76	5		T56	208
alert[0x20]	9776	1			T4	9		T19	4		T27	2
alert[0x21]	7666	1			T1	37		T20	19		T125	1
alert[0x22]	4220	1			T1	10		T20	368		T27	550
alert[0x23]	5081	1			T19	1		T20	115		T76	1
alert[0x24]	6944	1			T1	45		T56	41		T125	2
alert[0x25]	3141	1			T11	1		T61	65		T271	176
alert[0x26]	6213	1			T22	1		T76	6		T56	385
alert[0x27]	11079	1			T20	345		T79	1		T125	7
alert[0x28]	5061	1			T19	1		T56	12		T57	2
alert[0x29]	13342	1			T1	113		T4	652		T76	29
alert[0x2a]	6422	1			T4	124		T20	39		T8	1
alert[0x2b]	3841	1			T1	4		T65	436		T91	26
alert[0x2c]	3273	1			T20	460		T27	1		T76	5
alert[0x2d]	2465	1			T20	11		T76	3		T56	23
alert[0x2e]	16688	1			T4	3		T20	42		T56	720
alert[0x2f]	3438	1			T76	4		T57	7		T13	1
alert[0x30]	7389	1			T1	1		T19	1		T11	1
alert[0x31]	9948	1			T1	389		T76	15		T56	342
alert[0x32]	5968	1			T20	32		T56	386		T125	33
alert[0x33]	5431	1			T1	23		T4	301		T20	1173
alert[0x34]	8406	1			T1	126		T20	63		T79	1
alert[0x35]	7849	1			T27	6		T57	57		T294	22
alert[0x36]	6994	1			T1	91		T76	4		T12	1
alert[0x37]	6461	1			T1	21		T11	1		T13	1
alert[0x38]	9045	1			T76	66		T12	1		T294	90
alert[0x39]	8697	1			T20	35		T12	1		T125	1
alert[0x3a]	9359	1			T26	2		T54	1		T20	275
alert[0x3b]	12661	1			T4	152		T294	57		T126	214
alert[0x3c]	8475	1			T20	462		T56	385		T271	142
alert[0x3d]	5931	1			T294	6		T61	51		T102	1
alert[0x3e]	6851	1			T1	14		T20	20		T27	28
alert[0x3f]	4576	1			T1	337		T76	24		T126	653
alert[0x40]	16718	1			T1	6370		T20	78		T76	3

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	136079	1			T27	683		T56	32		T79	22
class_i[0x1]	112597	1			T1	4729		T26	7		T54	37
class_i[0x2]	163924	1			T19	3		T20	19482		T27	1
class_i[0x3]	73992	1			T1	5619		T3	16		T4	3025

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

485939

1

T1

10348

T3

16

T4

3025

alert_ping_fail

653

1

T8

1

T9

1

T10

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4351	1			T1	131		T20	794		T27	50
alert_integrity_fail	alert[0x1]	8667	1			T4	479		T43	19		T125	1
alert_integrity_fail	alert[0x2]	7664	1			T3	3		T4	21		T76	26
alert_integrity_fail	alert[0x3]	4876	1			T1	1002		T27	96		T76	13
alert_integrity_fail	alert[0x4]	5871	1			T1	20		T20	194		T56	2
alert_integrity_fail	alert[0x5]	6709	1			T1	116		T22	25		T26	6
alert_integrity_fail	alert[0x6]	10800	1			T19	1		T61	85		T65	65
alert_integrity_fail	alert[0x7]	6244	1			T1	29		T294	90		T271	18
alert_integrity_fail	alert[0x8]	4086	1			T1	6		T125	1		T294	865
alert_integrity_fail	alert[0x9]	11648	1			T4	129		T126	128		T61	43
alert_integrity_fail	alert[0xa]	5377	1			T1	208		T20	345		T210	2
alert_integrity_fail	alert[0xb]	19864	1			T20	6424		T76	9		T56	20
alert_integrity_fail	alert[0xc]	7362	1			T1	142		T54	36		T20	230
alert_integrity_fail	alert[0xd]	7946	1			T1	213		T20	39		T76	15
alert_integrity_fail	alert[0xe]	2770	1			T20	423		T56	351		T79	2
alert_integrity_fail	alert[0xf]	8998	1			T4	101		T20	1109		T56	21
alert_integrity_fail	alert[0x10]	2338	1			T19	1		T126	45		T61	10
alert_integrity_fail	alert[0x11]	2159	1			T1	59		T4	53		T56	25
alert_integrity_fail	alert[0x12]	9337	1			T19	4		T76	4		T56	276
alert_integrity_fail	alert[0x13]	4285	1			T1	168		T20	36		T294	99
alert_integrity_fail	alert[0x14]	6612	1			T4	37		T22	5		T19	6
alert_integrity_fail	alert[0x15]	4719	1			T4	947		T20	5		T27	10
alert_integrity_fail	alert[0x16]	12101	1			T20	871		T43	4		T294	1654
alert_integrity_fail	alert[0x17]	12262	1			T1	592		T27	2		T126	48
alert_integrity_fail	alert[0x18]	6585	1			T1	81		T3	7		T20	1
alert_integrity_fail	alert[0x19]	11290	1			T20	4778		T294	622		T126	411
alert_integrity_fail	alert[0x1a]	5345	1			T20	527		T56	7		T294	611
alert_integrity_fail	alert[0x1b]	7963	1			T26	1		T20	152		T56	2883
alert_integrity_fail	alert[0x1c]	7362	1			T3	6		T22	1		T76	12
alert_integrity_fail	alert[0x1d]	7824	1			T4	17		T294	3218		T126	108
alert_integrity_fail	alert[0x1e]	6686	1			T76	156		T294	200		T126	8
alert_integrity_fail	alert[0x1f]	6740	1			T27	20		T76	5		T56	208
alert_integrity_fail	alert[0x20]	9764	1			T4	9		T19	4		T27	2
alert_integrity_fail	alert[0x21]	7652	1			T1	37		T20	19		T125	1
alert_integrity_fail	alert[0x22]	4207	1			T1	10		T20	368		T27	550
alert_integrity_fail	alert[0x23]	5068	1			T19	1		T20	115		T76	1
alert_integrity_fail	alert[0x24]	6938	1			T1	45		T56	41		T125	2
alert_integrity_fail	alert[0x25]	3132	1			T61	65		T271	176		T63	10
alert_integrity_fail	alert[0x26]	6202	1			T22	1		T76	6		T56	385
alert_integrity_fail	alert[0x27]	11069	1			T20	345		T79	1		T125	7
alert_integrity_fail	alert[0x28]	5055	1			T19	1		T56	12		T57	2
alert_integrity_fail	alert[0x29]	13337	1			T1	113		T4	652		T76	29
alert_integrity_fail	alert[0x2a]	6410	1			T4	124		T20	39		T76	7
alert_integrity_fail	alert[0x2b]	3832	1			T1	4		T65	436		T91	26
alert_integrity_fail	alert[0x2c]	3258	1			T20	460		T27	1		T76	5
alert_integrity_fail	alert[0x2d]	2456	1			T20	11		T76	3		T56	23
alert_integrity_fail	alert[0x2e]	16675	1			T4	3		T20	42		T56	720
alert_integrity_fail	alert[0x2f]	3425	1			T76	4		T57	7		T125	1
alert_integrity_fail	alert[0x30]	7378	1			T1	1		T19	1		T125	11
alert_integrity_fail	alert[0x31]	9941	1			T1	389		T76	15		T56	342
alert_integrity_fail	alert[0x32]	5957	1			T20	32		T56	386		T125	33
alert_integrity_fail	alert[0x33]	5423	1			T1	23		T4	301		T20	1173
alert_integrity_fail	alert[0x34]	8398	1			T1	126		T20	63		T79	1
alert_integrity_fail	alert[0x35]	7842	1			T27	6		T57	57		T294	22
alert_integrity_fail	alert[0x36]	6988	1			T1	91		T76	4		T271	52
alert_integrity_fail	alert[0x37]	6445	1			T1	21		T125	3		T271	33
alert_integrity_fail	alert[0x38]	9038	1			T76	66		T294	90		T42	31
alert_integrity_fail	alert[0x39]	8688	1			T20	35		T125	1		T63	146
alert_integrity_fail	alert[0x3a]	9350	1			T26	2		T54	1		T20	275
alert_integrity_fail	alert[0x3b]	12653	1			T4	152		T294	57		T126	214
alert_integrity_fail	alert[0x3c]	8467	1			T20	462		T56	385		T271	142
alert_integrity_fail	alert[0x3d]	5917	1			T294	6		T61	51		T305	3
alert_integrity_fail	alert[0x3e]	6844	1			T1	14		T20	20		T27	28
alert_integrity_fail	alert[0x3f]	4574	1			T1	337		T76	24		T126	653
alert_integrity_fail	alert[0x40]	16715	1			T1	6370		T20	78		T76	3
alert_ping_fail	alert[0x0]	6	1			T306	1		T307	1		T308	1
alert_ping_fail	alert[0x1]	7	1			T102	1		T306	2		T309	1
alert_ping_fail	alert[0x2]	2	1			T310	1		T311	1		-	-
alert_ping_fail	alert[0x3]	8	1			T312	1		T307	1		T313	2
alert_ping_fail	alert[0x4]	9	1			T314	1		T315	1		T316	1
alert_ping_fail	alert[0x5]	10	1			T104	1		T317	2		T115	1
alert_ping_fail	alert[0x6]	9	1			T318	1		T319	1		T320	1
alert_ping_fail	alert[0x7]	16	1			T12	1		T266	1		T314	1
alert_ping_fail	alert[0x8]	8	1			T102	1		T321	1		T322	1
alert_ping_fail	alert[0x9]	13	1			T102	2		T323	1		T324	1
alert_ping_fail	alert[0xa]	14	1			T10	1		T11	1		T12	1
alert_ping_fail	alert[0xb]	18	1			T306	1		T310	1		T315	1
alert_ping_fail	alert[0xc]	7	1			T13	1		T324	1		T325	1
alert_ping_fail	alert[0xd]	17	1			T12	1		T13	1		T306	1
alert_ping_fail	alert[0xe]	3	1			T102	1		T326	1		T327	1
alert_ping_fail	alert[0xf]	15	1			T304	1		T314	1		T310	1
alert_ping_fail	alert[0x10]	12	1			T11	2		T12	1		T315	1
alert_ping_fail	alert[0x11]	6	1			T309	1		T328	1		T329	1
alert_ping_fail	alert[0x12]	8	1			T307	1		T309	1		T330	1
alert_ping_fail	alert[0x13]	22	1			T104	1		T312	1		T218	1
alert_ping_fail	alert[0x14]	15	1			T300	1		T314	1		T322	1
alert_ping_fail	alert[0x15]	19	1			T11	1		T102	2		T317	2
alert_ping_fail	alert[0x16]	13	1			T9	1		T310	1		T218	1
alert_ping_fail	alert[0x17]	10	1			T12	1		T312	1		T316	1
alert_ping_fail	alert[0x18]	6	1			T306	1		T115	1		T309	1
alert_ping_fail	alert[0x19]	10	1			T13	1		T304	1		T102	1
alert_ping_fail	alert[0x1a]	8	1			T324	2		T315	1		T331	1
alert_ping_fail	alert[0x1b]	8	1			T312	1		T315	1		T332	1
alert_ping_fail	alert[0x1c]	8	1			T306	1		T317	1		T333	2
alert_ping_fail	alert[0x1d]	11	1			T307	1		T333	1		T331	1
alert_ping_fail	alert[0x1e]	14	1			T304	1		T102	1		T312	1
alert_ping_fail	alert[0x1f]	10	1			T300	1		T314	1		T312	1
alert_ping_fail	alert[0x20]	12	1			T102	1		T314	1		T115	1
alert_ping_fail	alert[0x21]	14	1			T102	1		T310	1		T325	1
alert_ping_fail	alert[0x22]	13	1			T102	1		T317	1		T307	2
alert_ping_fail	alert[0x23]	13	1			T102	2		T324	1		T315	1
alert_ping_fail	alert[0x24]	6	1			T307	1		T309	1		T334	1
alert_ping_fail	alert[0x25]	9	1			T11	1		T102	1		T218	1
alert_ping_fail	alert[0x26]	11	1			T13	1		T115	1		T333	1
alert_ping_fail	alert[0x27]	10	1			T104	1		T310	1		T312	1
alert_ping_fail	alert[0x28]	6	1			T95	1		T333	1		T335	1
alert_ping_fail	alert[0x29]	5	1			T102	1		T331	1		T334	1
alert_ping_fail	alert[0x2a]	12	1			T8	1		T11	1		T316	1
alert_ping_fail	alert[0x2b]	9	1			T325	1		T307	1		T331	1
alert_ping_fail	alert[0x2c]	15	1			T12	1		T301	1		T268	1
alert_ping_fail	alert[0x2d]	9	1			T102	2		T323	1		T336	1
alert_ping_fail	alert[0x2e]	13	1			T13	2		T324	1		T337	1
alert_ping_fail	alert[0x2f]	13	1			T13	1		T104	2		T310	1
alert_ping_fail	alert[0x30]	11	1			T11	1		T12	1		T310	1
alert_ping_fail	alert[0x31]	7	1			T13	1		T104	2		T318	1
alert_ping_fail	alert[0x32]	11	1			T310	1		T323	1		T316	1
alert_ping_fail	alert[0x33]	8	1			T12	1		T314	2		T332	1
alert_ping_fail	alert[0x34]	8	1			T332	1		T115	1		T333	1
alert_ping_fail	alert[0x35]	7	1			T304	1		T314	1		T323	1
alert_ping_fail	alert[0x36]	6	1			T12	1		T304	1		T312	1
alert_ping_fail	alert[0x37]	16	1			T11	1		T13	1		T312	1
alert_ping_fail	alert[0x38]	7	1			T12	1		T312	1		T308	1
alert_ping_fail	alert[0x39]	9	1			T12	1		T338	2		T313	1
alert_ping_fail	alert[0x3a]	9	1			T102	1		T310	1		T312	1
alert_ping_fail	alert[0x3b]	8	1			T310	1		T339	2		T313	1
alert_ping_fail	alert[0x3c]	8	1			T289	1		T325	1		T340	1
alert_ping_fail	alert[0x3d]	14	1			T102	1		T324	1		T332	1
alert_ping_fail	alert[0x3e]	7	1			T12	1		T331	1		T309	1
alert_ping_fail	alert[0x3f]	2	1			T315	1		T341	1		-	-
alert_ping_fail	alert[0x40]	3	1			T330	1		T334	1		T327	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	135940	1			T27	683		T56	32		T79	22
alert_integrity_fail	class_i[0x1]	112409	1			T1	4729		T26	7		T54	37
alert_integrity_fail	class_i[0x2]	163751	1			T19	3		T20	19482		T27	1
alert_integrity_fail	class_i[0x3]	73839	1			T1	5619		T3	16		T4	3025
alert_ping_fail	class_i[0x0]	139	1			T11	1		T12	1		T13	2
alert_ping_fail	class_i[0x1]	188	1			T9	1		T10	1		T11	1
alert_ping_fail	class_i[0x2]	173	1			T11	6		T13	7		T304	4
alert_ping_fail	class_i[0x3]	153	1			T8	1		T300	2		T104	1