Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.99 98.69 100.00 100.00 100.00 99.38 99.40


Total test records in report: 847
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T779 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3419860137 Jan 10 12:44:39 PM PST 24 Jan 10 12:45:57 PM PST 24 26841744 ps
T780 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.47158784 Jan 10 12:27:28 PM PST 24 Jan 10 12:27:41 PM PST 24 181685068 ps
T781 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1656678952 Jan 10 12:29:10 PM PST 24 Jan 10 12:29:38 PM PST 24 168595306 ps
T782 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2094021692 Jan 10 12:29:06 PM PST 24 Jan 10 12:29:29 PM PST 24 7230444 ps
T783 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1189406712 Jan 10 12:29:30 PM PST 24 Jan 10 12:29:58 PM PST 24 11924454 ps
T784 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.107866120 Jan 10 12:34:55 PM PST 24 Jan 10 12:35:42 PM PST 24 216695916 ps
T785 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1268989148 Jan 10 12:26:35 PM PST 24 Jan 10 12:26:48 PM PST 24 253770704 ps
T786 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3358294477 Jan 10 12:29:00 PM PST 24 Jan 10 12:29:52 PM PST 24 1967009447 ps
T787 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2856520120 Jan 10 12:29:17 PM PST 24 Jan 10 12:29:49 PM PST 24 336474531 ps
T788 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2802927000 Jan 10 12:29:13 PM PST 24 Jan 10 12:30:33 PM PST 24 1214117560 ps
T174 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3132881907 Jan 10 12:29:13 PM PST 24 Jan 10 12:30:07 PM PST 24 595190340 ps
T789 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3876411753 Jan 10 12:34:26 PM PST 24 Jan 10 12:35:03 PM PST 24 6670555 ps
T790 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2768111123 Jan 10 12:51:37 PM PST 24 Jan 10 12:53:04 PM PST 24 7175457 ps
T183 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3363036651 Jan 10 12:31:58 PM PST 24 Jan 10 12:33:17 PM PST 24 1609163668 ps
T176 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1633580218 Jan 10 12:26:48 PM PST 24 Jan 10 12:27:14 PM PST 24 295654827 ps
T791 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4028867164 Jan 10 12:35:51 PM PST 24 Jan 10 12:36:16 PM PST 24 11994145 ps
T141 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3752385445 Jan 10 12:31:17 PM PST 24 Jan 10 12:35:06 PM PST 24 3604658440 ps
T135 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.4049322060 Jan 10 12:32:21 PM PST 24 Jan 10 12:38:26 PM PST 24 5665522542 ps
T792 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2601463312 Jan 10 12:29:02 PM PST 24 Jan 10 12:29:37 PM PST 24 2251723800 ps
T155 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2473088799 Jan 10 12:29:11 PM PST 24 Jan 10 12:34:04 PM PST 24 4332311948 ps
T793 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.557983336 Jan 10 12:27:00 PM PST 24 Jan 10 12:27:41 PM PST 24 297662361 ps
T794 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.673085932 Jan 10 12:49:34 PM PST 24 Jan 10 12:51:23 PM PST 24 586068815 ps
T795 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2423531764 Jan 10 12:29:11 PM PST 24 Jan 10 12:29:43 PM PST 24 58861595 ps
T796 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.340852650 Jan 10 12:44:11 PM PST 24 Jan 10 12:45:28 PM PST 24 7788809 ps
T797 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3584432562 Jan 10 12:45:17 PM PST 24 Jan 10 12:46:40 PM PST 24 14466113 ps
T154 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2123532100 Jan 10 12:27:29 PM PST 24 Jan 10 12:30:32 PM PST 24 2910317101 ps
T180 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2601942696 Jan 10 12:46:03 PM PST 24 Jan 10 12:47:26 PM PST 24 54982864 ps
T168 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1331388438 Jan 10 12:28:16 PM PST 24 Jan 10 12:36:32 PM PST 24 11822999035 ps
T151 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1078500623 Jan 10 12:34:39 PM PST 24 Jan 10 12:37:00 PM PST 24 3081172000 ps
T156 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.622307799 Jan 10 12:28:55 PM PST 24 Jan 10 12:31:30 PM PST 24 4122345956 ps
T798 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3453643462 Jan 10 12:30:42 PM PST 24 Jan 10 12:31:33 PM PST 24 1016648978 ps
T799 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2379671133 Jan 10 12:26:19 PM PST 24 Jan 10 12:26:25 PM PST 24 39365050 ps
T800 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3691440749 Jan 10 12:44:15 PM PST 24 Jan 10 12:45:33 PM PST 24 17474076 ps
T801 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2706683531 Jan 10 12:27:49 PM PST 24 Jan 10 12:28:09 PM PST 24 64944932 ps
T148 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3809849607 Jan 10 12:28:45 PM PST 24 Jan 10 12:30:54 PM PST 24 1518547155 ps
T802 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2412410959 Jan 10 12:54:13 PM PST 24 Jan 10 12:55:21 PM PST 24 12866282 ps
T803 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.838742116 Jan 10 12:26:34 PM PST 24 Jan 10 12:27:02 PM PST 24 351085855 ps
T804 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.323180094 Jan 10 12:28:10 PM PST 24 Jan 10 12:28:44 PM PST 24 194130063 ps
T165 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2841219717 Jan 10 12:27:32 PM PST 24 Jan 10 12:36:58 PM PST 24 8075872044 ps
T805 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3132696544 Jan 10 12:49:58 PM PST 24 Jan 10 12:51:37 PM PST 24 12460136 ps
T806 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2830944317 Jan 10 01:01:32 PM PST 24 Jan 10 01:03:08 PM PST 24 137164809 ps
T807 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.949501683 Jan 10 12:29:48 PM PST 24 Jan 10 12:30:23 PM PST 24 14806940 ps
T808 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3324393277 Jan 10 12:27:51 PM PST 24 Jan 10 12:28:13 PM PST 24 732928555 ps
T809 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2572248640 Jan 10 12:29:21 PM PST 24 Jan 10 12:30:21 PM PST 24 529859083 ps
T810 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3981993196 Jan 10 12:29:48 PM PST 24 Jan 10 12:30:26 PM PST 24 37917591 ps
T811 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4018346262 Jan 10 12:29:12 PM PST 24 Jan 10 12:29:40 PM PST 24 233716574 ps
T812 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.577541823 Jan 10 12:29:05 PM PST 24 Jan 10 12:29:35 PM PST 24 438111477 ps
T813 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3398625717 Jan 10 01:00:01 PM PST 24 Jan 10 01:01:38 PM PST 24 71946548 ps
T814 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2180700948 Jan 10 12:29:33 PM PST 24 Jan 10 12:30:08 PM PST 24 321916834 ps
T815 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3392250609 Jan 10 12:28:05 PM PST 24 Jan 10 12:28:29 PM PST 24 168942189 ps
T816 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2034000277 Jan 10 12:27:15 PM PST 24 Jan 10 12:27:22 PM PST 24 13268729 ps
T817 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1554587304 Jan 10 12:26:49 PM PST 24 Jan 10 12:27:00 PM PST 24 112770677 ps
T818 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3171798041 Jan 10 12:49:01 PM PST 24 Jan 10 12:50:38 PM PST 24 19324402 ps
T149 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3087410001 Jan 10 12:30:03 PM PST 24 Jan 10 12:33:29 PM PST 24 8887335399 ps
T819 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.213662411 Jan 10 12:29:12 PM PST 24 Jan 10 12:29:57 PM PST 24 721960835 ps
T820 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2761348473 Jan 10 12:40:33 PM PST 24 Jan 10 12:41:17 PM PST 24 34310782 ps
T821 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3418724068 Jan 10 12:29:11 PM PST 24 Jan 10 12:29:35 PM PST 24 9493061 ps
T822 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3481218611 Jan 10 12:26:48 PM PST 24 Jan 10 12:26:54 PM PST 24 37012583 ps
T150 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2472081368 Jan 10 12:31:05 PM PST 24 Jan 10 12:41:06 PM PST 24 4565028591 ps
T823 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3391670818 Jan 10 12:27:41 PM PST 24 Jan 10 12:31:01 PM PST 24 6802241036 ps
T824 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3295769779 Jan 10 12:27:18 PM PST 24 Jan 10 12:27:27 PM PST 24 16309412 ps
T825 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1799373574 Jan 10 12:26:37 PM PST 24 Jan 10 12:26:47 PM PST 24 27075633 ps
T826 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.592846676 Jan 10 12:29:32 PM PST 24 Jan 10 12:29:59 PM PST 24 10089410 ps
T827 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2831172729 Jan 10 12:25:14 PM PST 24 Jan 10 12:25:17 PM PST 24 7774359 ps
T157 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3366763156 Jan 10 12:29:07 PM PST 24 Jan 10 12:33:00 PM PST 24 2172427829 ps
T828 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.126015096 Jan 10 12:30:32 PM PST 24 Jan 10 12:31:20 PM PST 24 64342052 ps
T152 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3970396655 Jan 10 12:30:37 PM PST 24 Jan 10 12:32:38 PM PST 24 1434617170 ps
T829 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3321353529 Jan 10 12:29:49 PM PST 24 Jan 10 12:30:25 PM PST 24 8695698 ps
T161 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2861300037 Jan 10 12:29:47 PM PST 24 Jan 10 12:39:35 PM PST 24 4577957825 ps
T830 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2450214798 Jan 10 12:25:35 PM PST 24 Jan 10 12:25:58 PM PST 24 332361347 ps
T831 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.429883515 Jan 10 12:51:55 PM PST 24 Jan 10 12:53:15 PM PST 24 94696666 ps
T832 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3905414090 Jan 10 01:06:43 PM PST 24 Jan 10 01:08:30 PM PST 24 1681627117 ps
T833 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.4205657254 Jan 10 12:43:57 PM PST 24 Jan 10 12:45:13 PM PST 24 12257693 ps
T834 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2141816051 Jan 10 12:31:33 PM PST 24 Jan 10 12:35:24 PM PST 24 3708224587 ps
T162 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3206437901 Jan 10 12:27:53 PM PST 24 Jan 10 12:30:29 PM PST 24 2032044439 ps
T362 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.455871839 Jan 10 12:29:57 PM PST 24 Jan 10 12:35:21 PM PST 24 9334843524 ps
T175 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1146565238 Jan 10 12:25:10 PM PST 24 Jan 10 12:25:32 PM PST 24 312961849 ps
T363 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.333908938 Jan 10 12:29:50 PM PST 24 Jan 10 12:34:38 PM PST 24 24625848243 ps
T158 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2179485969 Jan 10 12:29:11 PM PST 24 Jan 10 12:46:34 PM PST 24 16416831722 ps
T835 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2930434217 Jan 10 12:27:16 PM PST 24 Jan 10 12:29:41 PM PST 24 1950264228 ps
T836 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2983470810 Jan 10 12:31:39 PM PST 24 Jan 10 12:32:36 PM PST 24 110483113 ps
T837 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2745287041 Jan 10 12:53:53 PM PST 24 Jan 10 12:55:04 PM PST 24 7829220 ps
T364 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.4112453148 Jan 10 12:24:33 PM PST 24 Jan 10 12:34:20 PM PST 24 15414640969 ps
T838 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.215345358 Jan 10 12:30:55 PM PST 24 Jan 10 12:31:48 PM PST 24 55392348 ps
T839 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2576961738 Jan 10 12:31:28 PM PST 24 Jan 10 12:32:22 PM PST 24 244346208 ps
T167 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1688051011 Jan 10 12:48:30 PM PST 24 Jan 10 01:03:35 PM PST 24 13252309377 ps
T840 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2214483222 Jan 10 12:28:23 PM PST 24 Jan 10 12:28:47 PM PST 24 576589703 ps
T841 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2409583015 Jan 10 12:26:45 PM PST 24 Jan 10 12:33:47 PM PST 24 8936004359 ps
T842 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.303393602 Jan 10 12:27:02 PM PST 24 Jan 10 12:27:27 PM PST 24 581301156 ps
T843 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.470124646 Jan 10 12:26:48 PM PST 24 Jan 10 12:26:57 PM PST 24 98020252 ps
T844 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4064223228 Jan 10 12:26:33 PM PST 24 Jan 10 12:26:41 PM PST 24 84935853 ps
T163 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3904636719 Jan 10 12:31:03 PM PST 24 Jan 10 12:36:00 PM PST 24 13972489827 ps
T845 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3156417231 Jan 10 12:31:16 PM PST 24 Jan 10 12:32:04 PM PST 24 95650331 ps
T846 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3283008773 Jan 10 12:26:35 PM PST 24 Jan 10 12:26:44 PM PST 24 34707730 ps
T166 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3545134414 Jan 10 12:30:37 PM PST 24 Jan 10 12:38:10 PM PST 24 12406751756 ps
T179 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1440461509 Jan 10 12:27:42 PM PST 24 Jan 10 12:27:52 PM PST 24 84760466 ps
T847 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2412485625 Jan 10 12:40:18 PM PST 24 Jan 10 12:41:07 PM PST 24 19217799 ps

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.589916135
Short name T33
Test name
Test status
Simulation time 1372549979 ps
CPU time 78.14 seconds
Started Jan 10 12:29:08 PM PST 24
Finished Jan 10 12:30:47 PM PST 24
Peak memory 236604 kb
Host smart-18105994-1de4-4c97-8ec7-20bc69bc1ade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=589916135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.589916135
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.3325135961
Short name T1
Test name
Test status
Simulation time 72625911654 ps
CPU time 6490.85 seconds
Started Jan 10 12:32:40 PM PST 24
Finished Jan 10 02:21:19 PM PST 24
Peak memory 394804 kb
Host smart-bf07932d-4e2b-4cca-a711-537a4358c680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325135961 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.3325135961
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.471421418
Short name T17
Test name
Test status
Simulation time 10096148 ps
CPU time 1.4 seconds
Started Jan 10 12:24:33 PM PST 24
Finished Jan 10 12:24:35 PM PST 24
Peak memory 236300 kb
Host smart-d70157cf-d80c-4cb4-a9c2-a92d2476aa8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=471421418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.471421418
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1289010115
Short name T229
Test name
Test status
Simulation time 468572120 ps
CPU time 13.53 seconds
Started Jan 10 12:28:53 PM PST 24
Finished Jan 10 12:29:25 PM PST 24
Peak memory 248536 kb
Host smart-e6d0a2f4-f9bc-4806-af55-25c354f72880
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1289010115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1289010115
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1230250560
Short name T16
Test name
Test status
Simulation time 713835261 ps
CPU time 29.74 seconds
Started Jan 10 12:28:24 PM PST 24
Finished Jan 10 12:29:05 PM PST 24
Peak memory 270192 kb
Host smart-751a5324-8bc9-4f1f-9d67-43b7de537b1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1230250560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1230250560
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3802605271
Short name T36
Test name
Test status
Simulation time 31160744027 ps
CPU time 342 seconds
Started Jan 10 12:28:06 PM PST 24
Finished Jan 10 12:34:04 PM PST 24
Peak memory 270992 kb
Host smart-9ca6b67b-ef3a-4ee4-89fb-6360d8669d30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3802605271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3802605271
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3975395275
Short name T20
Test name
Test status
Simulation time 45239666742 ps
CPU time 1277.74 seconds
Started Jan 10 12:28:53 PM PST 24
Finished Jan 10 12:50:30 PM PST 24
Peak memory 289432 kb
Host smart-81415a6e-a803-400f-bc4f-8b13c3889389
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975395275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3975395275
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.496894495
Short name T300
Test name
Test status
Simulation time 120288503512 ps
CPU time 1671.57 seconds
Started Jan 10 12:30:55 PM PST 24
Finished Jan 10 12:59:33 PM PST 24
Peak memory 271628 kb
Host smart-8bd66f8f-1ed2-49c0-935f-858e51c4801e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496894495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.496894495
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.18555992
Short name T28
Test name
Test status
Simulation time 17455760581 ps
CPU time 1019.99 seconds
Started Jan 10 12:29:15 PM PST 24
Finished Jan 10 12:46:39 PM PST 24
Peak memory 264992 kb
Host smart-084f5d4e-41f3-410e-921d-9c53d0c5876f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18555992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.18555992
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3959260356
Short name T42
Test name
Test status
Simulation time 63103703082 ps
CPU time 2548.5 seconds
Started Jan 10 12:29:56 PM PST 24
Finished Jan 10 01:13:04 PM PST 24
Peak memory 281328 kb
Host smart-c81b9905-57b8-4899-8bb9-7974fc1d6496
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959260356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3959260356
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3566770736
Short name T140
Test name
Test status
Simulation time 4428779448 ps
CPU time 619.09 seconds
Started Jan 10 12:28:25 PM PST 24
Finished Jan 10 12:38:56 PM PST 24
Peak memory 271512 kb
Host smart-79bebb5f-6951-4222-9aa3-6c82662ae634
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566770736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3566770736
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1228701166
Short name T19
Test name
Test status
Simulation time 241056321404 ps
CPU time 4529.05 seconds
Started Jan 10 12:28:31 PM PST 24
Finished Jan 10 01:44:11 PM PST 24
Peak memory 314336 kb
Host smart-34d0481c-9a79-413a-be89-84c1dc51cad0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228701166 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1228701166
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2103810206
Short name T134
Test name
Test status
Simulation time 19758695626 ps
CPU time 290.07 seconds
Started Jan 10 12:44:32 PM PST 24
Finished Jan 10 12:50:40 PM PST 24
Peak memory 271840 kb
Host smart-706e7908-cbf2-4364-8964-6f566b96729e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2103810206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2103810206
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.849219107
Short name T102
Test name
Test status
Simulation time 210270316279 ps
CPU time 550.15 seconds
Started Jan 10 12:30:13 PM PST 24
Finished Jan 10 12:40:03 PM PST 24
Peak memory 247476 kb
Host smart-ef0c02cf-921c-4430-b179-7ab6dd68b137
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849219107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.849219107
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3623578321
Short name T298
Test name
Test status
Simulation time 59297569900 ps
CPU time 3142.04 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 01:22:51 PM PST 24
Peak memory 288752 kb
Host smart-1f752bba-e193-491f-b367-b9a81ac65b68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623578321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3623578321
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1688051011
Short name T167
Test name
Test status
Simulation time 13252309377 ps
CPU time 822.42 seconds
Started Jan 10 12:48:30 PM PST 24
Finished Jan 10 01:03:35 PM PST 24
Peak memory 265556 kb
Host smart-ee220c92-c74b-40d6-a928-4be2c7661892
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688051011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1688051011
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2641136434
Short name T61
Test name
Test status
Simulation time 52763514749 ps
CPU time 3286.79 seconds
Started Jan 10 12:29:16 PM PST 24
Finished Jan 10 01:24:26 PM PST 24
Peak memory 305248 kb
Host smart-4aca9ae0-cd8a-42bd-a3e3-cf4ffebad880
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641136434 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2641136434
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3603348798
Short name T345
Test name
Test status
Simulation time 166672384235 ps
CPU time 1672.09 seconds
Started Jan 10 12:30:22 PM PST 24
Finished Jan 10 12:58:55 PM PST 24
Peak memory 282084 kb
Host smart-d230b0e5-6e22-4b51-8b3e-2ab48012f191
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603348798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3603348798
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1082497666
Short name T138
Test name
Test status
Simulation time 3328590347 ps
CPU time 190.45 seconds
Started Jan 10 12:35:01 PM PST 24
Finished Jan 10 12:38:50 PM PST 24
Peak memory 265324 kb
Host smart-25bf7ba3-ede5-419b-93cf-7c79e6e02a3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1082497666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1082497666
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3222770585
Short name T64
Test name
Test status
Simulation time 281901769231 ps
CPU time 3504.07 seconds
Started Jan 10 12:31:55 PM PST 24
Finished Jan 10 01:31:06 PM PST 24
Peak memory 305008 kb
Host smart-6cb8e467-19ac-4152-90fb-5e55c1d13859
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222770585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3222770585
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2353738957
Short name T12
Test name
Test status
Simulation time 41297787458 ps
CPU time 419.34 seconds
Started Jan 10 12:30:12 PM PST 24
Finished Jan 10 12:37:52 PM PST 24
Peak memory 247208 kb
Host smart-4ffb8a6f-072d-4f30-aa7c-cdbc92643d65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353738957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2353738957
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1366104978
Short name T8
Test name
Test status
Simulation time 20577391026 ps
CPU time 1672.61 seconds
Started Jan 10 12:28:40 PM PST 24
Finished Jan 10 12:56:46 PM PST 24
Peak memory 288824 kb
Host smart-aa98f0dc-1e06-40fe-8930-5dac9d8a5980
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366104978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1366104978
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.763593760
Short name T132
Test name
Test status
Simulation time 50411792787 ps
CPU time 948.83 seconds
Started Jan 10 12:28:49 PM PST 24
Finished Jan 10 12:44:54 PM PST 24
Peak memory 265220 kb
Host smart-b7690eda-e257-4182-b2b9-f5a1b3d60b09
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763593760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.763593760
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.477172374
Short name T309
Test name
Test status
Simulation time 26423570835 ps
CPU time 545.88 seconds
Started Jan 10 12:28:22 PM PST 24
Finished Jan 10 12:37:40 PM PST 24
Peak memory 247560 kb
Host smart-0520b462-cd75-42e6-a9e4-efb6f4c582dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477172374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.477172374
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.974823000
Short name T171
Test name
Test status
Simulation time 366076588 ps
CPU time 3.29 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 12:30:31 PM PST 24
Peak memory 235552 kb
Host smart-1493d579-641a-43ee-9319-4af8b2f1e098
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=974823000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.974823000
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2097380287
Short name T95
Test name
Test status
Simulation time 88772386613 ps
CPU time 1990.27 seconds
Started Jan 10 12:29:25 PM PST 24
Finished Jan 10 01:03:02 PM PST 24
Peak memory 283912 kb
Host smart-ac120799-c732-46af-a81b-caf9802e3363
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097380287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2097380287
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1527464647
Short name T358
Test name
Test status
Simulation time 20578756 ps
CPU time 1.41 seconds
Started Jan 10 12:25:46 PM PST 24
Finished Jan 10 12:25:48 PM PST 24
Peak memory 235484 kb
Host smart-14376aac-a215-4993-bbd1-4d4a6617cfb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1527464647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1527464647
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.709929613
Short name T82
Test name
Test status
Simulation time 105837803087 ps
CPU time 2075.8 seconds
Started Jan 10 12:28:26 PM PST 24
Finished Jan 10 01:03:13 PM PST 24
Peak memory 289180 kb
Host smart-2b4ae265-0636-43fa-862e-50707dd28907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709929613 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.709929613
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2123532100
Short name T154
Test name
Test status
Simulation time 2910317101 ps
CPU time 178.99 seconds
Started Jan 10 12:27:29 PM PST 24
Finished Jan 10 12:30:32 PM PST 24
Peak memory 272508 kb
Host smart-6a01428b-9074-4228-88ab-48b0d22c4443
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2123532100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2123532100
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3688257019
Short name T5
Test name
Test status
Simulation time 11772000639 ps
CPU time 965.39 seconds
Started Jan 10 12:28:55 PM PST 24
Finished Jan 10 12:45:19 PM PST 24
Peak memory 273120 kb
Host smart-8a9d3e5a-95d5-4735-831e-ce57f8cbcc3c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688257019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3688257019
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1865248626
Short name T307
Test name
Test status
Simulation time 26924014177 ps
CPU time 537.62 seconds
Started Jan 10 12:28:25 PM PST 24
Finished Jan 10 12:37:34 PM PST 24
Peak memory 247448 kb
Host smart-11ab864c-67e2-4bb7-8544-9a99ac3b4e1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865248626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1865248626
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1278693065
Short name T68
Test name
Test status
Simulation time 129257565370 ps
CPU time 2092.97 seconds
Started Jan 10 12:29:51 PM PST 24
Finished Jan 10 01:05:20 PM PST 24
Peak memory 289876 kb
Host smart-a52c9124-af1f-442c-9785-c1f1d14f6f75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278693065 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1278693065
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1316159090
Short name T107
Test name
Test status
Simulation time 115827648471 ps
CPU time 1724.7 seconds
Started Jan 10 12:28:48 PM PST 24
Finished Jan 10 12:57:49 PM PST 24
Peak memory 289704 kb
Host smart-c8d7026f-c9e4-4ee7-bbf8-d97394a2c46c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316159090 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1316159090
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3087410001
Short name T149
Test name
Test status
Simulation time 8887335399 ps
CPU time 164.11 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:33:29 PM PST 24
Peak memory 269092 kb
Host smart-4acf52d0-98bd-4527-bba3-22d482b5da21
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3087410001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3087410001
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.540957250
Short name T241
Test name
Test status
Simulation time 604498627 ps
CPU time 17.27 seconds
Started Jan 10 12:30:10 PM PST 24
Finished Jan 10 12:31:08 PM PST 24
Peak memory 246744 kb
Host smart-7d414854-03bc-4b2d-a17b-3cebc20228c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54095
7250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.540957250
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.4039810314
Short name T248
Test name
Test status
Simulation time 101380502009 ps
CPU time 5734.61 seconds
Started Jan 10 12:29:01 PM PST 24
Finished Jan 10 02:04:56 PM PST 24
Peak memory 321800 kb
Host smart-17334b67-e8d1-4c0a-a1d6-b28171114804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039810314 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.4039810314
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2220180371
Short name T91
Test name
Test status
Simulation time 131556922474 ps
CPU time 3123.94 seconds
Started Jan 10 12:32:02 PM PST 24
Finished Jan 10 01:24:53 PM PST 24
Peak memory 321172 kb
Host smart-fb90bcd5-6f09-4c10-a2f7-3d5fc056a6b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220180371 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2220180371
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3487183218
Short name T630
Test name
Test status
Simulation time 110779414455 ps
CPU time 608.53 seconds
Started Jan 10 12:31:53 PM PST 24
Finished Jan 10 12:42:49 PM PST 24
Peak memory 247392 kb
Host smart-9119e34c-db62-4897-b610-77a42a758320
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487183218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3487183218
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3090120092
Short name T269
Test name
Test status
Simulation time 89196848191 ps
CPU time 4246.34 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 01:41:30 PM PST 24
Peak memory 390700 kb
Host smart-9f1d8f78-64bf-4513-96b2-11fc7733a607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090120092 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3090120092
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.637418579
Short name T147
Test name
Test status
Simulation time 24349751639 ps
CPU time 457.45 seconds
Started Jan 10 12:26:48 PM PST 24
Finished Jan 10 12:34:30 PM PST 24
Peak memory 263816 kb
Host smart-4d55b823-359f-4c2b-8dc7-7c68fb9c207b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637418579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.637418579
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.67327177
Short name T9
Test name
Test status
Simulation time 42013113819 ps
CPU time 2320.02 seconds
Started Jan 10 12:29:10 PM PST 24
Finished Jan 10 01:08:12 PM PST 24
Peak memory 289340 kb
Host smart-5eac5217-d76c-4c4c-8a20-7d913744c373
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67327177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.67327177
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3904636719
Short name T163
Test name
Test status
Simulation time 13972489827 ps
CPU time 250.06 seconds
Started Jan 10 12:31:03 PM PST 24
Finished Jan 10 12:36:00 PM PST 24
Peak memory 271060 kb
Host smart-5532cb95-c764-4ae5-aa5f-320504c0a023
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3904636719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3904636719
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2598685246
Short name T136
Test name
Test status
Simulation time 6504197442 ps
CPU time 336.89 seconds
Started Jan 10 12:36:11 PM PST 24
Finished Jan 10 12:42:19 PM PST 24
Peak memory 269144 kb
Host smart-44825a3d-32c5-4911-84c6-3e83b7ba9917
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598685246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2598685246
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3924917804
Short name T30
Test name
Test status
Simulation time 10970138 ps
CPU time 1.36 seconds
Started Jan 10 12:28:25 PM PST 24
Finished Jan 10 12:28:37 PM PST 24
Peak memory 235448 kb
Host smart-86501a7d-eac3-49f3-9d5a-c33e0dba05a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3924917804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3924917804
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3115660593
Short name T250
Test name
Test status
Simulation time 361088821312 ps
CPU time 6005.94 seconds
Started Jan 10 12:28:35 PM PST 24
Finished Jan 10 02:08:54 PM PST 24
Peak memory 322212 kb
Host smart-22170b0a-24f5-4a2d-99bf-75f7a3e188da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115660593 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3115660593
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3476132468
Short name T65
Test name
Test status
Simulation time 75793674410 ps
CPU time 2311.08 seconds
Started Jan 10 12:28:43 PM PST 24
Finished Jan 10 01:07:28 PM PST 24
Peak memory 288968 kb
Host smart-59bc204d-d76b-4e7c-92f7-2546ad752a9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476132468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3476132468
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.109410286
Short name T315
Test name
Test status
Simulation time 83452036899 ps
CPU time 211.93 seconds
Started Jan 10 12:29:24 PM PST 24
Finished Jan 10 12:33:23 PM PST 24
Peak memory 247664 kb
Host smart-67760f5d-0fce-4879-ac2a-99a032fe0835
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109410286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.109410286
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1024344325
Short name T169
Test name
Test status
Simulation time 5234028372 ps
CPU time 56.27 seconds
Started Jan 10 12:28:57 PM PST 24
Finished Jan 10 12:30:12 PM PST 24
Peak memory 245860 kb
Host smart-1bcb4079-c921-40dd-a23e-6c7d68b084ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1024344325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1024344325
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2473088799
Short name T155
Test name
Test status
Simulation time 4332311948 ps
CPU time 271.05 seconds
Started Jan 10 12:29:11 PM PST 24
Finished Jan 10 12:34:04 PM PST 24
Peak memory 267404 kb
Host smart-45b5240f-fabe-4622-84d3-d99f5ff3b1f1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473088799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2473088799
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1456645625
Short name T192
Test name
Test status
Simulation time 83685005 ps
CPU time 4.13 seconds
Started Jan 10 12:28:05 PM PST 24
Finished Jan 10 12:28:24 PM PST 24
Peak memory 248888 kb
Host smart-2f3c5fc1-02df-44c1-a92b-ec5efa0c9ec9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1456645625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1456645625
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.721344162
Short name T105
Test name
Test status
Simulation time 53974620 ps
CPU time 2.36 seconds
Started Jan 10 12:31:46 PM PST 24
Finished Jan 10 12:32:36 PM PST 24
Peak memory 246112 kb
Host smart-f3c5d3cd-deaa-4ad1-8bae-52fbd5e95448
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=721344162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.721344162
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.323086880
Short name T202
Test name
Test status
Simulation time 74386106 ps
CPU time 2.74 seconds
Started Jan 10 12:28:38 PM PST 24
Finished Jan 10 12:28:53 PM PST 24
Peak memory 248796 kb
Host smart-847ae6a7-02f6-4df8-ae18-645216333c12
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=323086880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.323086880
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3526167685
Short name T203
Test name
Test status
Simulation time 144663263 ps
CPU time 2.79 seconds
Started Jan 10 12:28:35 PM PST 24
Finished Jan 10 12:28:50 PM PST 24
Peak memory 248636 kb
Host smart-f696d917-f906-4bd0-95b7-0855cc014714
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3526167685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3526167685
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.622307799
Short name T156
Test name
Test status
Simulation time 4122345956 ps
CPU time 136.42 seconds
Started Jan 10 12:28:55 PM PST 24
Finished Jan 10 12:31:30 PM PST 24
Peak memory 257140 kb
Host smart-eb285585-3ca4-463f-8625-22c139580182
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=622307799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.622307799
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1489977867
Short name T293
Test name
Test status
Simulation time 49495549345 ps
CPU time 716.71 seconds
Started Jan 10 12:32:02 PM PST 24
Finished Jan 10 12:44:45 PM PST 24
Peak memory 272784 kb
Host smart-09b574ef-70a0-4b8e-b173-52203aa639d3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489977867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1489977867
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1934449127
Short name T237
Test name
Test status
Simulation time 2480567045 ps
CPU time 36.27 seconds
Started Jan 10 12:31:04 PM PST 24
Finished Jan 10 12:32:27 PM PST 24
Peak memory 253616 kb
Host smart-31cd4960-7656-4b64-8594-fe680d7d48c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19344
49127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1934449127
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3745483374
Short name T322
Test name
Test status
Simulation time 45193918487 ps
CPU time 1340.75 seconds
Started Jan 10 12:29:09 PM PST 24
Finished Jan 10 12:51:53 PM PST 24
Peak memory 273148 kb
Host smart-b3066cbc-15f1-47c4-8bb5-4c9452ad99c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745483374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3745483374
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.662000986
Short name T243
Test name
Test status
Simulation time 207096150642 ps
CPU time 1653.47 seconds
Started Jan 10 12:29:28 PM PST 24
Finished Jan 10 12:57:27 PM PST 24
Peak memory 289672 kb
Host smart-5ac6c53b-d235-4e28-8725-30c6c4cafff6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662000986 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.662000986
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.4287527591
Short name T333
Test name
Test status
Simulation time 27573580780 ps
CPU time 542.51 seconds
Started Jan 10 12:29:48 PM PST 24
Finished Jan 10 12:39:24 PM PST 24
Peak memory 247148 kb
Host smart-a45eb0be-9b62-4eb8-a12a-f44fd8fdb67b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287527591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.4287527591
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3169183663
Short name T22
Test name
Test status
Simulation time 702064070 ps
CPU time 38.09 seconds
Started Jan 10 12:30:56 PM PST 24
Finished Jan 10 12:32:21 PM PST 24
Peak memory 254708 kb
Host smart-7f03a1f3-4fb6-4c25-a484-1473e625cb3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31691
83663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3169183663
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3152528340
Short name T310
Test name
Test status
Simulation time 7997579906 ps
CPU time 303.63 seconds
Started Jan 10 12:30:00 PM PST 24
Finished Jan 10 12:35:45 PM PST 24
Peak memory 247532 kb
Host smart-420b4779-facc-411a-a646-93a17aec5bb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152528340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3152528340
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2993958380
Short name T53
Test name
Test status
Simulation time 386069664775 ps
CPU time 1365.7 seconds
Started Jan 10 12:29:20 PM PST 24
Finished Jan 10 12:52:31 PM PST 24
Peak memory 288496 kb
Host smart-58f2587c-0792-4a6d-af4e-fb9d88f276b8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993958380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2993958380
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1798651279
Short name T337
Test name
Test status
Simulation time 40634665122 ps
CPU time 2031.58 seconds
Started Jan 10 12:29:49 PM PST 24
Finished Jan 10 01:04:15 PM PST 24
Peak memory 273184 kb
Host smart-b1a416ff-0976-4fef-af0d-6e4d829a45f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798651279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1798651279
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.728428658
Short name T252
Test name
Test status
Simulation time 322847803906 ps
CPU time 5476.31 seconds
Started Jan 10 12:29:32 PM PST 24
Finished Jan 10 02:01:15 PM PST 24
Peak memory 354136 kb
Host smart-61371f2c-aabc-4e74-89cd-85918558a22c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728428658 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.728428658
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1078500623
Short name T151
Test name
Test status
Simulation time 3081172000 ps
CPU time 100.06 seconds
Started Jan 10 12:34:39 PM PST 24
Finished Jan 10 12:37:00 PM PST 24
Peak memory 257052 kb
Host smart-8b2c54bb-7362-4c4b-b5db-fd02fc222781
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1078500623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1078500623
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3809849607
Short name T148
Test name
Test status
Simulation time 1518547155 ps
CPU time 114.68 seconds
Started Jan 10 12:28:45 PM PST 24
Finished Jan 10 12:30:54 PM PST 24
Peak memory 256904 kb
Host smart-a359a43a-c78e-47dd-ac78-4d177f7baa0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3809849607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3809849607
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3274675494
Short name T172
Test name
Test status
Simulation time 96640726 ps
CPU time 2.34 seconds
Started Jan 10 12:34:22 PM PST 24
Finished Jan 10 12:34:57 PM PST 24
Peak memory 236496 kb
Host smart-9d5a68c6-a650-49ef-bf98-78a26214abbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3274675494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3274675494
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2753942136
Short name T261
Test name
Test status
Simulation time 13278403281 ps
CPU time 878.66 seconds
Started Jan 10 12:28:25 PM PST 24
Finished Jan 10 12:43:15 PM PST 24
Peak memory 272852 kb
Host smart-52f0f1ac-ca8e-47f0-b388-7753c921dda5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753942136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2753942136
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1900625416
Short name T327
Test name
Test status
Simulation time 46835690995 ps
CPU time 460.1 seconds
Started Jan 10 12:32:01 PM PST 24
Finished Jan 10 12:40:28 PM PST 24
Peak memory 246760 kb
Host smart-15e932ff-7e5d-4406-bedb-32b7704c504c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900625416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1900625416
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.247061295
Short name T253
Test name
Test status
Simulation time 2544874800 ps
CPU time 40.45 seconds
Started Jan 10 12:28:39 PM PST 24
Finished Jan 10 12:29:32 PM PST 24
Peak memory 255108 kb
Host smart-fd9525f6-8fd1-4c27-97f9-baf4ef4387af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24706
1295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.247061295
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3331767089
Short name T284
Test name
Test status
Simulation time 17988494717 ps
CPU time 1030.43 seconds
Started Jan 10 12:29:08 PM PST 24
Finished Jan 10 12:46:40 PM PST 24
Peak memory 282524 kb
Host smart-ee4d7a58-ae2d-4169-a8c3-d445126a679e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331767089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3331767089
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2802713301
Short name T244
Test name
Test status
Simulation time 204934401850 ps
CPU time 3073.78 seconds
Started Jan 10 12:29:03 PM PST 24
Finished Jan 10 01:20:36 PM PST 24
Peak memory 298268 kb
Host smart-4f1bc81a-ad1b-42a7-a5e2-431892a20a86
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802713301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2802713301
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3305545484
Short name T75
Test name
Test status
Simulation time 212649118717 ps
CPU time 2287.92 seconds
Started Jan 10 12:29:05 PM PST 24
Finished Jan 10 01:07:34 PM PST 24
Peak memory 272952 kb
Host smart-5ff63e8b-c660-4fc6-9bcd-fd1b559ab542
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305545484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3305545484
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2217846826
Short name T262
Test name
Test status
Simulation time 57226913603 ps
CPU time 3028.9 seconds
Started Jan 10 12:29:07 PM PST 24
Finished Jan 10 01:19:57 PM PST 24
Peak memory 289452 kb
Host smart-527ba631-e20e-4c55-a8cf-9953ad1086b1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217846826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2217846826
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3891395843
Short name T302
Test name
Test status
Simulation time 11685457268 ps
CPU time 902.93 seconds
Started Jan 10 12:29:14 PM PST 24
Finished Jan 10 12:44:40 PM PST 24
Peak memory 272512 kb
Host smart-7ce22c5b-ccc0-4936-a697-6d192f13e736
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891395843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3891395843
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1667819699
Short name T297
Test name
Test status
Simulation time 56109366958 ps
CPU time 1333.78 seconds
Started Jan 10 12:29:19 PM PST 24
Finished Jan 10 12:51:57 PM PST 24
Peak memory 285516 kb
Host smart-52bcdd8b-e0b1-4941-91f6-3aa096451c59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667819699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1667819699
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1544899492
Short name T238
Test name
Test status
Simulation time 16568438881 ps
CPU time 1460.81 seconds
Started Jan 10 12:28:40 PM PST 24
Finished Jan 10 12:53:14 PM PST 24
Peak memory 288968 kb
Host smart-a5a3fa34-7906-4a48-9454-40681ade4d17
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544899492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1544899492
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2228505548
Short name T319
Test name
Test status
Simulation time 18243718143 ps
CPU time 1097.48 seconds
Started Jan 10 12:28:21 PM PST 24
Finished Jan 10 12:46:51 PM PST 24
Peak memory 271580 kb
Host smart-78f29db4-4688-4072-b190-3854adbda4f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228505548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2228505548
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.823243424
Short name T212
Test name
Test status
Simulation time 684348499 ps
CPU time 18.8 seconds
Started Jan 10 12:29:51 PM PST 24
Finished Jan 10 12:30:46 PM PST 24
Peak memory 246768 kb
Host smart-46af0666-05ba-4425-a810-b4f5eb5da3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82324
3424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.823243424
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3424357274
Short name T115
Test name
Test status
Simulation time 23180815404 ps
CPU time 355.73 seconds
Started Jan 10 12:32:13 PM PST 24
Finished Jan 10 12:38:50 PM PST 24
Peak memory 246764 kb
Host smart-0dd5cbf9-9e6f-4d28-8b96-7c749f98c594
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424357274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3424357274
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2377405744
Short name T173
Test name
Test status
Simulation time 34747633 ps
CPU time 2.09 seconds
Started Jan 10 12:28:16 PM PST 24
Finished Jan 10 12:28:32 PM PST 24
Peak memory 236344 kb
Host smart-6be8b51a-0933-44a2-9a97-534a662d186f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2377405744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2377405744
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2842696509
Short name T178
Test name
Test status
Simulation time 206301136 ps
CPU time 8.63 seconds
Started Jan 10 12:28:38 PM PST 24
Finished Jan 10 12:28:59 PM PST 24
Peak memory 235164 kb
Host smart-bfb994bc-278f-4657-ad90-0098ec42d6a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2842696509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2842696509
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.629355744
Short name T129
Test name
Test status
Simulation time 1282335617 ps
CPU time 74.24 seconds
Started Jan 10 12:29:16 PM PST 24
Finished Jan 10 12:30:54 PM PST 24
Peak memory 238892 kb
Host smart-7b554306-080f-43ff-859c-88eaa44a3fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=629355744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.629355744
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3132881907
Short name T174
Test name
Test status
Simulation time 595190340 ps
CPU time 32.33 seconds
Started Jan 10 12:29:13 PM PST 24
Finished Jan 10 12:30:07 PM PST 24
Peak memory 239232 kb
Host smart-e300d57e-8374-4ffd-b2d0-81b37b60c889
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3132881907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3132881907
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2601942696
Short name T180
Test name
Test status
Simulation time 54982864 ps
CPU time 2.06 seconds
Started Jan 10 12:46:03 PM PST 24
Finished Jan 10 12:47:26 PM PST 24
Peak memory 237520 kb
Host smart-8582c3dd-6033-4782-9ae6-f1aa7ee57d49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2601942696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2601942696
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2179485969
Short name T158
Test name
Test status
Simulation time 16416831722 ps
CPU time 1021.24 seconds
Started Jan 10 12:29:11 PM PST 24
Finished Jan 10 12:46:34 PM PST 24
Peak memory 264860 kb
Host smart-1bcbba11-aeca-4196-a2de-21fa3fdabc69
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179485969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2179485969
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1440461509
Short name T179
Test name
Test status
Simulation time 84760466 ps
CPU time 2.72 seconds
Started Jan 10 12:27:42 PM PST 24
Finished Jan 10 12:27:52 PM PST 24
Peak memory 235412 kb
Host smart-42997825-7ff0-4f40-ad9c-b578de80445b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1440461509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1440461509
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.4035705736
Short name T182
Test name
Test status
Simulation time 1261180554 ps
CPU time 17.47 seconds
Started Jan 10 12:28:55 PM PST 24
Finished Jan 10 12:29:32 PM PST 24
Peak memory 238364 kb
Host smart-d5720929-6898-4d50-8e35-80d73cd66de1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4035705736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.4035705736
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3363036651
Short name T183
Test name
Test status
Simulation time 1609163668 ps
CPU time 32.86 seconds
Started Jan 10 12:31:58 PM PST 24
Finished Jan 10 12:33:17 PM PST 24
Peak memory 236336 kb
Host smart-5924dc88-b1ca-4c5f-adfa-f7f7eaf2ef85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3363036651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3363036651
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3475074362
Short name T38
Test name
Test status
Simulation time 360098076 ps
CPU time 22.74 seconds
Started Jan 10 12:30:21 PM PST 24
Finished Jan 10 12:31:25 PM PST 24
Peak memory 254464 kb
Host smart-ca4e2a5c-69b2-4de6-b055-a40d84775420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34750
74362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3475074362
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.702360845
Short name T37
Test name
Test status
Simulation time 1050141907 ps
CPU time 12.85 seconds
Started Jan 10 12:29:49 PM PST 24
Finished Jan 10 12:30:35 PM PST 24
Peak memory 255396 kb
Host smart-9eac3210-ccc0-40c4-8814-0e81cac7dffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70236
0845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.702360845
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2992369361
Short name T137
Test name
Test status
Simulation time 2374502926 ps
CPU time 120.59 seconds
Started Jan 10 12:26:31 PM PST 24
Finished Jan 10 12:28:35 PM PST 24
Peak memory 238976 kb
Host smart-b588bace-db76-45a6-ad00-31ee66684229
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2992369361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2992369361
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3391670818
Short name T823
Test name
Test status
Simulation time 6802241036 ps
CPU time 191.7 seconds
Started Jan 10 12:27:41 PM PST 24
Finished Jan 10 12:31:01 PM PST 24
Peak memory 236344 kb
Host smart-21c716f9-ca0d-4de8-acc0-9196db202682
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3391670818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3391670818
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2850442931
Short name T35
Test name
Test status
Simulation time 111140666 ps
CPU time 8.53 seconds
Started Jan 10 12:26:16 PM PST 24
Finished Jan 10 12:26:27 PM PST 24
Peak memory 240316 kb
Host smart-96d29d96-fc4b-4483-920e-60780672a458
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2850442931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2850442931
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4064223228
Short name T844
Test name
Test status
Simulation time 84935853 ps
CPU time 4.95 seconds
Started Jan 10 12:26:33 PM PST 24
Finished Jan 10 12:26:41 PM PST 24
Peak memory 248220 kb
Host smart-eb330d14-9d57-4ce8-bd94-13b77f806d4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064223228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.4064223228
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1644435531
Short name T774
Test name
Test status
Simulation time 57898249 ps
CPU time 4.27 seconds
Started Jan 10 12:30:02 PM PST 24
Finished Jan 10 12:30:48 PM PST 24
Peak memory 235148 kb
Host smart-fc3bc942-03b6-4ad2-a9fd-b740631d7476
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1644435531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1644435531
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.942124217
Short name T760
Test name
Test status
Simulation time 6722672 ps
CPU time 1.39 seconds
Started Jan 10 12:28:08 PM PST 24
Finished Jan 10 12:28:25 PM PST 24
Peak memory 234648 kb
Host smart-29c376af-7a9d-416d-a4e9-9d3c5be13daf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=942124217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.942124217
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.240260251
Short name T775
Test name
Test status
Simulation time 502948650 ps
CPU time 32.34 seconds
Started Jan 10 12:27:28 PM PST 24
Finished Jan 10 12:28:06 PM PST 24
Peak memory 244500 kb
Host smart-1f47e2b7-5d5f-4173-84c7-86c4c48fbc47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=240260251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.240260251
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.4089909092
Short name T130
Test name
Test status
Simulation time 2615000772 ps
CPU time 161.62 seconds
Started Jan 10 12:29:17 PM PST 24
Finished Jan 10 12:32:22 PM PST 24
Peak memory 255872 kb
Host smart-81b8fa32-343b-47f4-a99b-3854316e0766
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4089909092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.4089909092
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2856520120
Short name T787
Test name
Test status
Simulation time 336474531 ps
CPU time 8.44 seconds
Started Jan 10 12:29:17 PM PST 24
Finished Jan 10 12:29:49 PM PST 24
Peak memory 247264 kb
Host smart-ae67b1b2-c315-4ba4-b049-00a2297ecbd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2856520120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2856520120
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3249839445
Short name T761
Test name
Test status
Simulation time 4392946851 ps
CPU time 255.58 seconds
Started Jan 10 12:28:55 PM PST 24
Finished Jan 10 12:33:30 PM PST 24
Peak memory 239500 kb
Host smart-83a5d510-486d-4e87-88f4-312f8c04ecdf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3249839445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3249839445
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2141816051
Short name T834
Test name
Test status
Simulation time 3708224587 ps
CPU time 180.87 seconds
Started Jan 10 12:31:33 PM PST 24
Finished Jan 10 12:35:24 PM PST 24
Peak memory 235088 kb
Host smart-ec6c2aac-b198-4c7c-bfb8-210772f5d2f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2141816051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2141816051
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1921663336
Short name T757
Test name
Test status
Simulation time 233458359 ps
CPU time 5 seconds
Started Jan 10 12:29:07 PM PST 24
Finished Jan 10 12:29:33 PM PST 24
Peak memory 239224 kb
Host smart-b2388b0c-701f-45ba-b98b-859a1817d909
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1921663336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1921663336
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4018346262
Short name T811
Test name
Test status
Simulation time 233716574 ps
CPU time 6.2 seconds
Started Jan 10 12:29:12 PM PST 24
Finished Jan 10 12:29:40 PM PST 24
Peak memory 251412 kb
Host smart-dad0e18e-441c-4dca-98b8-9f66e4acaf99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018346262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.4018346262
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1628989509
Short name T368
Test name
Test status
Simulation time 720750218 ps
CPU time 4.24 seconds
Started Jan 10 12:26:32 PM PST 24
Finished Jan 10 12:26:39 PM PST 24
Peak memory 235000 kb
Host smart-72a765b9-ba94-4cf3-86ef-b65a7269d4ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1628989509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1628989509
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3785995386
Short name T160
Test name
Test status
Simulation time 175443925 ps
CPU time 21.3 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:31:05 PM PST 24
Peak memory 248092 kb
Host smart-12424a4b-e697-47d3-b202-714439761aa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3785995386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3785995386
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.455871839
Short name T362
Test name
Test status
Simulation time 9334843524 ps
CPU time 284.86 seconds
Started Jan 10 12:29:57 PM PST 24
Finished Jan 10 12:35:21 PM PST 24
Peak memory 264940 kb
Host smart-c795b589-d0b0-4be5-9c23-827088de46ed
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455871839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.455871839
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.215345358
Short name T838
Test name
Test status
Simulation time 55392348 ps
CPU time 6.51 seconds
Started Jan 10 12:30:55 PM PST 24
Finished Jan 10 12:31:48 PM PST 24
Peak memory 251912 kb
Host smart-3f831288-ad3d-4f87-b9ef-b8cd4bc4d898
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=215345358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.215345358
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1146565238
Short name T175
Test name
Test status
Simulation time 312961849 ps
CPU time 20.43 seconds
Started Jan 10 12:25:10 PM PST 24
Finished Jan 10 12:25:32 PM PST 24
Peak memory 248468 kb
Host smart-fb0b18bd-925f-447a-9a73-29823b6785ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1146565238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1146565238
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3452585530
Short name T753
Test name
Test status
Simulation time 225382114 ps
CPU time 6.17 seconds
Started Jan 10 12:28:06 PM PST 24
Finished Jan 10 12:28:28 PM PST 24
Peak memory 243356 kb
Host smart-145da91e-2627-4080-819e-21edf948a3f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452585530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3452585530
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2706683531
Short name T801
Test name
Test status
Simulation time 64944932 ps
CPU time 5.2 seconds
Started Jan 10 12:27:49 PM PST 24
Finished Jan 10 12:28:09 PM PST 24
Peak memory 236316 kb
Host smart-4a6d0127-21c5-4c0e-a465-8d696e56a868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2706683531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2706683531
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2034000277
Short name T816
Test name
Test status
Simulation time 13268729 ps
CPU time 1.26 seconds
Started Jan 10 12:27:15 PM PST 24
Finished Jan 10 12:27:22 PM PST 24
Peak memory 236320 kb
Host smart-52d87907-032e-47c4-8173-cf9d2faf1b55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2034000277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2034000277
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1085757902
Short name T34
Test name
Test status
Simulation time 1197664739 ps
CPU time 34.55 seconds
Started Jan 10 12:30:42 PM PST 24
Finished Jan 10 12:31:59 PM PST 24
Peak memory 247372 kb
Host smart-e7e96ec8-6862-4a21-a6ff-5b9e1b4ac0d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1085757902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1085757902
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2930434217
Short name T835
Test name
Test status
Simulation time 1950264228 ps
CPU time 139.37 seconds
Started Jan 10 12:27:16 PM PST 24
Finished Jan 10 12:29:41 PM PST 24
Peak memory 256940 kb
Host smart-5e612365-5809-40b3-8c92-19f1655186da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2930434217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2930434217
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3982185006
Short name T145
Test name
Test status
Simulation time 8290480966 ps
CPU time 564.69 seconds
Started Jan 10 12:27:16 PM PST 24
Finished Jan 10 12:36:46 PM PST 24
Peak memory 265312 kb
Host smart-b75b53c3-6732-4eb2-a166-d55173ccc37e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982185006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3982185006
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3830398723
Short name T131
Test name
Test status
Simulation time 34920230 ps
CPU time 4.07 seconds
Started Jan 10 12:26:46 PM PST 24
Finished Jan 10 12:26:56 PM PST 24
Peak memory 249664 kb
Host smart-34922c80-ccc1-46a3-8fd2-c0288971b883
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3830398723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3830398723
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1799373574
Short name T825
Test name
Test status
Simulation time 27075633 ps
CPU time 4.89 seconds
Started Jan 10 12:26:37 PM PST 24
Finished Jan 10 12:26:47 PM PST 24
Peak memory 240704 kb
Host smart-be691fbe-4bd2-4671-9e77-c06c0d35744e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799373574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1799373574
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1633280739
Short name T187
Test name
Test status
Simulation time 62901004 ps
CPU time 5.03 seconds
Started Jan 10 12:27:43 PM PST 24
Finished Jan 10 12:28:00 PM PST 24
Peak memory 235416 kb
Host smart-c8440bf3-0640-48c8-82d6-750207af5e1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1633280739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1633280739
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.391374942
Short name T747
Test name
Test status
Simulation time 55336825 ps
CPU time 2.78 seconds
Started Jan 10 12:29:57 PM PST 24
Finished Jan 10 12:30:40 PM PST 24
Peak memory 235204 kb
Host smart-0f545394-3fa5-4954-b7c6-9ff8000b346c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=391374942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.391374942
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1175304139
Short name T748
Test name
Test status
Simulation time 719273374 ps
CPU time 39.5 seconds
Started Jan 10 12:29:34 PM PST 24
Finished Jan 10 12:30:41 PM PST 24
Peak memory 243268 kb
Host smart-62e59894-4bf7-4643-bac0-25c167ef9977
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1175304139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1175304139
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2256391539
Short name T143
Test name
Test status
Simulation time 2168596020 ps
CPU time 159.53 seconds
Started Jan 10 12:25:15 PM PST 24
Finished Jan 10 12:27:55 PM PST 24
Peak memory 257040 kb
Host smart-cec64491-f872-4964-bbcc-9d0834964ba6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2256391539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2256391539
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1331388438
Short name T168
Test name
Test status
Simulation time 11822999035 ps
CPU time 481.24 seconds
Started Jan 10 12:28:16 PM PST 24
Finished Jan 10 12:36:32 PM PST 24
Peak memory 267604 kb
Host smart-748aa181-b9d8-4ef5-b5f7-8a9447bae4e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331388438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1331388438
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3453643462
Short name T798
Test name
Test status
Simulation time 1016648978 ps
CPU time 8.8 seconds
Started Jan 10 12:30:42 PM PST 24
Finished Jan 10 12:31:33 PM PST 24
Peak memory 252124 kb
Host smart-46af01d6-294c-4a07-a53f-92528043d9e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3453643462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3453643462
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.4140675185
Short name T234
Test name
Test status
Simulation time 315824639 ps
CPU time 6.62 seconds
Started Jan 10 12:28:19 PM PST 24
Finished Jan 10 12:28:39 PM PST 24
Peak memory 251104 kb
Host smart-089d5ccf-70d1-4f66-aee5-1d8a38fbdc2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140675185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.4140675185
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3392250609
Short name T815
Test name
Test status
Simulation time 168942189 ps
CPU time 8.33 seconds
Started Jan 10 12:28:05 PM PST 24
Finished Jan 10 12:28:29 PM PST 24
Peak memory 236268 kb
Host smart-ac16d25b-e757-4913-850a-b40f539f938a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3392250609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3392250609
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1189406712
Short name T783
Test name
Test status
Simulation time 11924454 ps
CPU time 1.3 seconds
Started Jan 10 12:29:30 PM PST 24
Finished Jan 10 12:29:58 PM PST 24
Peak memory 233048 kb
Host smart-834dc5fb-deab-47de-b0e2-322faab0812e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1189406712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1189406712
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.323180094
Short name T804
Test name
Test status
Simulation time 194130063 ps
CPU time 19.67 seconds
Started Jan 10 12:28:10 PM PST 24
Finished Jan 10 12:28:44 PM PST 24
Peak memory 248476 kb
Host smart-65ed1321-c0fe-46fd-9609-b6f0b6040168
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=323180094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.323180094
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3970396655
Short name T152
Test name
Test status
Simulation time 1434617170 ps
CPU time 78.03 seconds
Started Jan 10 12:30:37 PM PST 24
Finished Jan 10 12:32:38 PM PST 24
Peak memory 256740 kb
Host smart-71bfdf4b-3f4d-4e73-8088-8d421c900736
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3970396655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3970396655
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.14243311
Short name T144
Test name
Test status
Simulation time 9116817681 ps
CPU time 271.76 seconds
Started Jan 10 12:29:30 PM PST 24
Finished Jan 10 12:34:28 PM PST 24
Peak memory 263920 kb
Host smart-91511a26-8c80-4a3a-b9cb-c3c95190a91d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14243311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.14243311
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3427048088
Short name T185
Test name
Test status
Simulation time 87065611 ps
CPU time 2.88 seconds
Started Jan 10 12:30:40 PM PST 24
Finished Jan 10 12:31:26 PM PST 24
Peak memory 239792 kb
Host smart-039c2122-c116-4b44-b7fc-03f4d6c37c58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3427048088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3427048088
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1975746004
Short name T177
Test name
Test status
Simulation time 1226806198 ps
CPU time 76.14 seconds
Started Jan 10 12:45:59 PM PST 24
Finished Jan 10 12:48:36 PM PST 24
Peak memory 239656 kb
Host smart-8155e286-d505-45d2-b44b-a1e79687e629
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1975746004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1975746004
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.63729831
Short name T737
Test name
Test status
Simulation time 67530286 ps
CPU time 6.39 seconds
Started Jan 10 12:29:31 PM PST 24
Finished Jan 10 12:30:03 PM PST 24
Peak memory 255616 kb
Host smart-cbf5812d-6bfa-491a-98d8-8a52ed75bba7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63729831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.alert_handler_csr_mem_rw_with_rand_reset.63729831
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.126015096
Short name T828
Test name
Test status
Simulation time 64342052 ps
CPU time 4.8 seconds
Started Jan 10 12:30:32 PM PST 24
Finished Jan 10 12:31:20 PM PST 24
Peak memory 236024 kb
Host smart-ae4a21aa-0028-4d0b-833f-d7a82bf5227f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=126015096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.126015096
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.592846676
Short name T826
Test name
Test status
Simulation time 10089410 ps
CPU time 1.42 seconds
Started Jan 10 12:29:32 PM PST 24
Finished Jan 10 12:29:59 PM PST 24
Peak memory 235020 kb
Host smart-ccaa43ed-199a-4062-8415-9dc320874fe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=592846676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.592846676
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1906283798
Short name T759
Test name
Test status
Simulation time 85849904 ps
CPU time 8.79 seconds
Started Jan 10 12:29:33 PM PST 24
Finished Jan 10 12:30:08 PM PST 24
Peak memory 239860 kb
Host smart-53231aee-d347-4f5b-9d51-637aba8ac325
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1906283798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1906283798
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2754099202
Short name T133
Test name
Test status
Simulation time 20777707054 ps
CPU time 272.17 seconds
Started Jan 10 12:40:47 PM PST 24
Finished Jan 10 12:46:07 PM PST 24
Peak memory 271048 kb
Host smart-ad647155-724b-41db-9fe7-19a5d6eab787
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2754099202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2754099202
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2180700948
Short name T814
Test name
Test status
Simulation time 321916834 ps
CPU time 9.16 seconds
Started Jan 10 12:29:33 PM PST 24
Finished Jan 10 12:30:08 PM PST 24
Peak memory 248100 kb
Host smart-21929169-1065-4429-b7ec-e22a4b811e8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2180700948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2180700948
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2423531764
Short name T795
Test name
Test status
Simulation time 58861595 ps
CPU time 3.75 seconds
Started Jan 10 12:29:11 PM PST 24
Finished Jan 10 12:29:43 PM PST 24
Peak memory 240056 kb
Host smart-27f69ed0-c5f3-470f-a67b-55b08f4b18f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423531764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2423531764
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3355383663
Short name T365
Test name
Test status
Simulation time 94436539 ps
CPU time 7.56 seconds
Started Jan 10 12:29:19 PM PST 24
Finished Jan 10 12:29:52 PM PST 24
Peak memory 236320 kb
Host smart-ad70fa1a-7acb-426c-b80a-d148ff0be2b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3355383663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3355383663
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3584432562
Short name T797
Test name
Test status
Simulation time 14466113 ps
CPU time 1.29 seconds
Started Jan 10 12:45:17 PM PST 24
Finished Jan 10 12:46:40 PM PST 24
Peak memory 234532 kb
Host smart-98116978-5c53-4b29-9396-222512e77876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3584432562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3584432562
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.94734827
Short name T736
Test name
Test status
Simulation time 685078058 ps
CPU time 20.92 seconds
Started Jan 10 01:12:07 PM PST 24
Finished Jan 10 01:13:45 PM PST 24
Peak memory 244660 kb
Host smart-3727ce3f-2d7c-4c64-91ee-172cc59397ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=94734827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outs
tanding.94734827
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2983470810
Short name T836
Test name
Test status
Simulation time 110483113 ps
CPU time 6.36 seconds
Started Jan 10 12:31:39 PM PST 24
Finished Jan 10 12:32:36 PM PST 24
Peak memory 246568 kb
Host smart-4cad6308-fc81-4b8f-ac3d-3e518375aff1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2983470810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2983470810
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2830944317
Short name T806
Test name
Test status
Simulation time 137164809 ps
CPU time 6.82 seconds
Started Jan 10 01:01:32 PM PST 24
Finished Jan 10 01:03:08 PM PST 24
Peak memory 236836 kb
Host smart-47cf57c4-b75f-455f-815b-6b9bd6a29879
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2830944317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2830944317
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2175415834
Short name T127
Test name
Test status
Simulation time 57191388 ps
CPU time 5.73 seconds
Started Jan 10 12:31:18 PM PST 24
Finished Jan 10 12:32:09 PM PST 24
Peak memory 251096 kb
Host smart-db0d4ac4-111f-4384-a6e2-075faf2d8962
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175415834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2175415834
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2369397352
Short name T159
Test name
Test status
Simulation time 68857567 ps
CPU time 3.56 seconds
Started Jan 10 12:24:46 PM PST 24
Finished Jan 10 12:24:51 PM PST 24
Peak memory 238336 kb
Host smart-241239ec-a486-4c93-bd11-abfa682d0b4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2369397352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2369397352
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1318656205
Short name T186
Test name
Test status
Simulation time 18961367 ps
CPU time 1.56 seconds
Started Jan 10 12:37:35 PM PST 24
Finished Jan 10 12:38:11 PM PST 24
Peak memory 235572 kb
Host smart-d82bfcfe-16ba-4402-a6c4-784f358a9469
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1318656205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1318656205
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2572248640
Short name T809
Test name
Test status
Simulation time 529859083 ps
CPU time 32.48 seconds
Started Jan 10 12:29:21 PM PST 24
Finished Jan 10 12:30:21 PM PST 24
Peak memory 244216 kb
Host smart-4bf9bf00-3339-4503-ab43-79fb1336f6fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2572248640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2572248640
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2876502385
Short name T32
Test name
Test status
Simulation time 455042951 ps
CPU time 8.77 seconds
Started Jan 10 12:25:11 PM PST 24
Finished Jan 10 12:25:20 PM PST 24
Peak memory 248548 kb
Host smart-d59825ee-2636-4fba-a528-5770f5c9bb6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2876502385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2876502385
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1639426707
Short name T233
Test name
Test status
Simulation time 89876641 ps
CPU time 7.84 seconds
Started Jan 10 12:39:25 PM PST 24
Finished Jan 10 12:40:03 PM PST 24
Peak memory 243520 kb
Host smart-361c5099-4337-46f7-84ac-98e25a7ad27a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639426707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1639426707
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1630602491
Short name T764
Test name
Test status
Simulation time 65379429 ps
CPU time 4.92 seconds
Started Jan 10 12:34:28 PM PST 24
Finished Jan 10 12:35:11 PM PST 24
Peak memory 236456 kb
Host smart-c91fffaa-837b-4b23-ace9-fc37aaec1edc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1630602491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1630602491
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3171798041
Short name T818
Test name
Test status
Simulation time 19324402 ps
CPU time 1.29 seconds
Started Jan 10 12:49:01 PM PST 24
Finished Jan 10 12:50:38 PM PST 24
Peak memory 236488 kb
Host smart-3afc47a9-b49b-45d2-a70f-4d7157c6d47d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3171798041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3171798041
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.213662411
Short name T819
Test name
Test status
Simulation time 721960835 ps
CPU time 22.83 seconds
Started Jan 10 12:29:12 PM PST 24
Finished Jan 10 12:29:57 PM PST 24
Peak memory 239868 kb
Host smart-966f963e-2bd5-4cce-b0f4-dde669a2c089
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=213662411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.213662411
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3324393277
Short name T808
Test name
Test status
Simulation time 732928555 ps
CPU time 6.84 seconds
Started Jan 10 12:27:51 PM PST 24
Finished Jan 10 12:28:13 PM PST 24
Peak memory 249300 kb
Host smart-d5d5b5c9-99cc-4dea-9a92-17e80e0a4d18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3324393277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3324393277
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3398625717
Short name T813
Test name
Test status
Simulation time 71946548 ps
CPU time 3.68 seconds
Started Jan 10 01:00:01 PM PST 24
Finished Jan 10 01:01:38 PM PST 24
Peak memory 255928 kb
Host smart-8cc5d5e7-c970-4eaa-807d-dcab5e2669d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398625717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3398625717
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.76902376
Short name T758
Test name
Test status
Simulation time 52520959 ps
CPU time 4.59 seconds
Started Jan 10 12:50:51 PM PST 24
Finished Jan 10 12:52:11 PM PST 24
Peak memory 239300 kb
Host smart-5e67ae50-b5a3-43ba-8670-6d1513504fcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=76902376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.76902376
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3905414090
Short name T832
Test name
Test status
Simulation time 1681627117 ps
CPU time 23.42 seconds
Started Jan 10 01:06:43 PM PST 24
Finished Jan 10 01:08:30 PM PST 24
Peak memory 244392 kb
Host smart-9578f0fa-107a-426d-b5dc-684d7e18a29c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3905414090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3905414090
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.962222543
Short name T153
Test name
Test status
Simulation time 33105413145 ps
CPU time 559.03 seconds
Started Jan 10 12:46:43 PM PST 24
Finished Jan 10 12:57:18 PM PST 24
Peak memory 267952 kb
Host smart-b7f919b0-9c3d-4b2b-b732-d1debfd786ce
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962222543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.962222543
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3147353490
Short name T776
Test name
Test status
Simulation time 683641299 ps
CPU time 5.23 seconds
Started Jan 10 12:28:49 PM PST 24
Finished Jan 10 12:29:11 PM PST 24
Peak memory 252280 kb
Host smart-e05166b8-5513-4e41-8d10-6e4d1b872360
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3147353490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3147353490
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.673085932
Short name T794
Test name
Test status
Simulation time 586068815 ps
CPU time 21.58 seconds
Started Jan 10 12:49:34 PM PST 24
Finished Jan 10 12:51:23 PM PST 24
Peak memory 239236 kb
Host smart-540cdf75-1e72-468f-bfd4-46349f63f5bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=673085932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.673085932
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.107866120
Short name T784
Test name
Test status
Simulation time 216695916 ps
CPU time 5.98 seconds
Started Jan 10 12:34:55 PM PST 24
Finished Jan 10 12:35:42 PM PST 24
Peak memory 251732 kb
Host smart-3643286d-2641-41e4-8027-229f21d0f491
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107866120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.107866120
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.4051738112
Short name T367
Test name
Test status
Simulation time 100217655 ps
CPU time 4.31 seconds
Started Jan 10 12:28:39 PM PST 24
Finished Jan 10 12:28:56 PM PST 24
Peak memory 235440 kb
Host smart-3684a065-7652-4d3c-a975-732307416379
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4051738112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.4051738112
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3474753677
Short name T228
Test name
Test status
Simulation time 26190565 ps
CPU time 1.42 seconds
Started Jan 10 12:31:41 PM PST 24
Finished Jan 10 12:32:32 PM PST 24
Peak memory 235052 kb
Host smart-f8bb927e-6627-4d58-a487-30e23d318b3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3474753677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3474753677
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3358294477
Short name T786
Test name
Test status
Simulation time 1967009447 ps
CPU time 32.89 seconds
Started Jan 10 12:29:00 PM PST 24
Finished Jan 10 12:29:52 PM PST 24
Peak memory 244456 kb
Host smart-cf7cd22c-d355-4541-83ce-1db494d81aab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3358294477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3358294477
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.15303469
Short name T139
Test name
Test status
Simulation time 6322209328 ps
CPU time 184.98 seconds
Started Jan 10 12:30:14 PM PST 24
Finished Jan 10 12:33:59 PM PST 24
Peak memory 265240 kb
Host smart-3598771c-f4b5-4f7f-a350-ac76ac7e6c31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=15303469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_error
s.15303469
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2841219717
Short name T165
Test name
Test status
Simulation time 8075872044 ps
CPU time 560.37 seconds
Started Jan 10 12:27:32 PM PST 24
Finished Jan 10 12:36:58 PM PST 24
Peak memory 265340 kb
Host smart-195bb26d-72d7-4409-b26d-937059003007
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841219717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2841219717
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.429883515
Short name T831
Test name
Test status
Simulation time 94696666 ps
CPU time 6.42 seconds
Started Jan 10 12:51:55 PM PST 24
Finished Jan 10 12:53:15 PM PST 24
Peak memory 248008 kb
Host smart-591a8280-03e5-47be-bace-3640b969a2ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=429883515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.429883515
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.173075791
Short name T184
Test name
Test status
Simulation time 41316083 ps
CPU time 4.22 seconds
Started Jan 10 12:25:14 PM PST 24
Finished Jan 10 12:25:20 PM PST 24
Peak memory 240368 kb
Host smart-9deac4e9-823a-48f3-b6da-7b471cfaf796
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173075791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.173075791
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2468140945
Short name T754
Test name
Test status
Simulation time 35556967 ps
CPU time 4.53 seconds
Started Jan 10 12:43:00 PM PST 24
Finished Jan 10 12:44:18 PM PST 24
Peak memory 235624 kb
Host smart-76eba244-f4d5-43ad-a6c9-90a74ea8df8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2468140945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2468140945
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.4205657254
Short name T833
Test name
Test status
Simulation time 12257693 ps
CPU time 1.28 seconds
Started Jan 10 12:43:57 PM PST 24
Finished Jan 10 12:45:13 PM PST 24
Peak memory 234636 kb
Host smart-e1a35af5-3943-44b2-83a6-ac1e9a24da15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4205657254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.4205657254
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2214483222
Short name T840
Test name
Test status
Simulation time 576589703 ps
CPU time 12.31 seconds
Started Jan 10 12:28:23 PM PST 24
Finished Jan 10 12:28:47 PM PST 24
Peak memory 244520 kb
Host smart-e42091aa-dc7d-4720-b126-6056786ef304
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2214483222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2214483222
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2861300037
Short name T161
Test name
Test status
Simulation time 4577957825 ps
CPU time 553.78 seconds
Started Jan 10 12:29:47 PM PST 24
Finished Jan 10 12:39:35 PM PST 24
Peak memory 264912 kb
Host smart-24a8e428-4498-40cc-801f-fe40907bbba8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861300037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2861300037
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3450783271
Short name T769
Test name
Test status
Simulation time 156078540 ps
CPU time 9.01 seconds
Started Jan 10 12:36:06 PM PST 24
Finished Jan 10 12:36:41 PM PST 24
Peak memory 248656 kb
Host smart-39fa418a-365d-4013-9c0f-6e75b1950a75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3450783271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3450783271
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2002733505
Short name T768
Test name
Test status
Simulation time 1657147632 ps
CPU time 122.98 seconds
Started Jan 10 12:24:24 PM PST 24
Finished Jan 10 12:26:28 PM PST 24
Peak memory 240332 kb
Host smart-cfd6e28f-c0dd-42da-bdf1-9e18865c9c8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2002733505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2002733505
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1306205714
Short name T765
Test name
Test status
Simulation time 1671362190 ps
CPU time 76.01 seconds
Started Jan 10 12:29:06 PM PST 24
Finished Jan 10 12:30:43 PM PST 24
Peak memory 239836 kb
Host smart-6183d04b-07dc-42d4-bcb8-3fa661d5cb6e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1306205714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1306205714
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.577541823
Short name T812
Test name
Test status
Simulation time 438111477 ps
CPU time 8.46 seconds
Started Jan 10 12:29:05 PM PST 24
Finished Jan 10 12:29:35 PM PST 24
Peak memory 239336 kb
Host smart-35eedaa2-6534-4511-958b-70c9cef49ec6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=577541823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.577541823
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2235000268
Short name T746
Test name
Test status
Simulation time 26126997 ps
CPU time 4.91 seconds
Started Jan 10 12:28:47 PM PST 24
Finished Jan 10 12:29:07 PM PST 24
Peak memory 251920 kb
Host smart-9f5776c0-597f-46e8-8024-7836360a4db6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235000268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2235000268
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.593564006
Short name T762
Test name
Test status
Simulation time 221399983 ps
CPU time 4.55 seconds
Started Jan 10 12:28:20 PM PST 24
Finished Jan 10 12:28:38 PM PST 24
Peak memory 238072 kb
Host smart-1c762d9b-d0bc-4604-98ab-c8232106746a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=593564006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.593564006
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4279028504
Short name T29
Test name
Test status
Simulation time 8463848 ps
CPU time 1.33 seconds
Started Jan 10 12:27:49 PM PST 24
Finished Jan 10 12:28:05 PM PST 24
Peak memory 236348 kb
Host smart-0e0e6913-0b54-4c49-931b-2408bddb04b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4279028504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4279028504
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2450214798
Short name T830
Test name
Test status
Simulation time 332361347 ps
CPU time 22.27 seconds
Started Jan 10 12:25:35 PM PST 24
Finished Jan 10 12:25:58 PM PST 24
Peak memory 244844 kb
Host smart-11f701b3-70a7-43d6-96de-c1b2c846eb49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2450214798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2450214798
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.303393602
Short name T842
Test name
Test status
Simulation time 581301156 ps
CPU time 17.91 seconds
Started Jan 10 12:27:02 PM PST 24
Finished Jan 10 12:27:27 PM PST 24
Peak memory 254576 kb
Host smart-8d5b91ac-26b7-4dbd-8b71-38b3311eb454
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=303393602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.303393602
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.957079575
Short name T767
Test name
Test status
Simulation time 35238012 ps
CPU time 1.25 seconds
Started Jan 10 12:34:23 PM PST 24
Finished Jan 10 12:34:59 PM PST 24
Peak memory 235520 kb
Host smart-a4f7dc02-c402-46c5-bf76-48222334422e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=957079575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.957079575
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2412485625
Short name T847
Test name
Test status
Simulation time 19217799 ps
CPU time 1.31 seconds
Started Jan 10 12:40:18 PM PST 24
Finished Jan 10 12:41:07 PM PST 24
Peak memory 235496 kb
Host smart-3a7afe52-5fc3-4b24-be97-09b614f96bbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2412485625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2412485625
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2831172729
Short name T827
Test name
Test status
Simulation time 7774359 ps
CPU time 1.5 seconds
Started Jan 10 12:25:14 PM PST 24
Finished Jan 10 12:25:17 PM PST 24
Peak memory 235508 kb
Host smart-f255e0a1-5fe5-4c22-a1ef-4d5a9bfdcdd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2831172729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2831172729
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1658632342
Short name T742
Test name
Test status
Simulation time 6953468 ps
CPU time 1.24 seconds
Started Jan 10 12:48:33 PM PST 24
Finished Jan 10 12:49:56 PM PST 24
Peak memory 234608 kb
Host smart-72b62748-f477-4735-a52f-db46b5ea387b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1658632342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1658632342
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1651890247
Short name T360
Test name
Test status
Simulation time 26197922 ps
CPU time 1.35 seconds
Started Jan 10 12:34:33 PM PST 24
Finished Jan 10 12:35:15 PM PST 24
Peak memory 236372 kb
Host smart-9cef1171-fa6b-4460-8a51-58f7cebd5b12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1651890247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1651890247
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.526928948
Short name T777
Test name
Test status
Simulation time 16420561 ps
CPU time 1.23 seconds
Started Jan 10 12:43:44 PM PST 24
Finished Jan 10 12:45:01 PM PST 24
Peak memory 236392 kb
Host smart-e3267410-a467-4f10-84d8-fa1ee256d694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=526928948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.526928948
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3876411753
Short name T789
Test name
Test status
Simulation time 6670555 ps
CPU time 1.38 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:03 PM PST 24
Peak memory 236392 kb
Host smart-7e2da421-b286-4e20-add7-788092269680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3876411753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3876411753
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2916043713
Short name T766
Test name
Test status
Simulation time 11555532 ps
CPU time 1.34 seconds
Started Jan 10 12:59:43 PM PST 24
Finished Jan 10 01:01:21 PM PST 24
Peak memory 236100 kb
Host smart-19364839-99e2-46e2-8494-c4d2daef69dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2916043713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2916043713
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2761348473
Short name T820
Test name
Test status
Simulation time 34310782 ps
CPU time 1.31 seconds
Started Jan 10 12:40:33 PM PST 24
Finished Jan 10 12:41:17 PM PST 24
Peak memory 236488 kb
Host smart-dbe58ae2-b063-43aa-8d63-3f763f95df6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2761348473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2761348473
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3672483260
Short name T735
Test name
Test status
Simulation time 9271896619 ps
CPU time 141.2 seconds
Started Jan 10 12:28:56 PM PST 24
Finished Jan 10 12:31:36 PM PST 24
Peak memory 236328 kb
Host smart-0bf7377a-9546-4e74-8419-b4ed92d91f80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3672483260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3672483260
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.13072666
Short name T31
Test name
Test status
Simulation time 6532625961 ps
CPU time 184.5 seconds
Started Jan 10 12:29:47 PM PST 24
Finished Jan 10 12:33:25 PM PST 24
Peak memory 235488 kb
Host smart-e0bb0ab5-2d78-495d-810f-fb6107bc16da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=13072666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.13072666
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1031846638
Short name T770
Test name
Test status
Simulation time 22646544 ps
CPU time 3.59 seconds
Started Jan 10 12:29:48 PM PST 24
Finished Jan 10 12:30:25 PM PST 24
Peak memory 239820 kb
Host smart-6df734a4-a95c-4341-b824-d051678a67b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1031846638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1031846638
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3235795493
Short name T128
Test name
Test status
Simulation time 28994618 ps
CPU time 5.76 seconds
Started Jan 10 12:26:54 PM PST 24
Finished Jan 10 12:27:05 PM PST 24
Peak memory 252232 kb
Host smart-2eb1cb7f-f9b3-4ca2-8097-2754b2c01b00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235795493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3235795493
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3981993196
Short name T810
Test name
Test status
Simulation time 37917591 ps
CPU time 4.9 seconds
Started Jan 10 12:29:48 PM PST 24
Finished Jan 10 12:30:26 PM PST 24
Peak memory 235872 kb
Host smart-79e2301b-44f4-45a7-ad68-137ea0d13218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3981993196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3981993196
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.949501683
Short name T807
Test name
Test status
Simulation time 14806940 ps
CPU time 1.37 seconds
Started Jan 10 12:29:48 PM PST 24
Finished Jan 10 12:30:23 PM PST 24
Peak memory 235104 kb
Host smart-9d09988a-cee9-48d1-9094-be1ef8abb8b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=949501683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.949501683
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3968472884
Short name T190
Test name
Test status
Simulation time 2118195345 ps
CPU time 23.33 seconds
Started Jan 10 12:26:38 PM PST 24
Finished Jan 10 12:27:06 PM PST 24
Peak memory 244676 kb
Host smart-603618a4-c8bb-4578-97d1-7f67aad15103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3968472884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3968472884
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3487715486
Short name T142
Test name
Test status
Simulation time 55453425216 ps
CPU time 452.98 seconds
Started Jan 10 12:28:42 PM PST 24
Finished Jan 10 12:36:28 PM PST 24
Peak memory 265212 kb
Host smart-2d7a8eab-0cf3-453f-87e5-e4d08b389ac5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487715486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3487715486
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2154378686
Short name T170
Test name
Test status
Simulation time 522742330 ps
CPU time 15.75 seconds
Started Jan 10 12:29:05 PM PST 24
Finished Jan 10 12:29:42 PM PST 24
Peak memory 246828 kb
Host smart-9719cdf5-1404-475e-a058-d72f2020eb0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2154378686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2154378686
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.557983336
Short name T793
Test name
Test status
Simulation time 297662361 ps
CPU time 33.67 seconds
Started Jan 10 12:27:00 PM PST 24
Finished Jan 10 12:27:41 PM PST 24
Peak memory 240228 kb
Host smart-1cbafee1-880b-40af-ba74-4d6a939ad26f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=557983336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.557983336
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2197284077
Short name T739
Test name
Test status
Simulation time 7756945 ps
CPU time 1.52 seconds
Started Jan 10 01:00:03 PM PST 24
Finished Jan 10 01:01:31 PM PST 24
Peak memory 235636 kb
Host smart-08978e49-4f36-43e1-bab6-bdf2474a8240
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2197284077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2197284077
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.340852650
Short name T796
Test name
Test status
Simulation time 7788809 ps
CPU time 1.44 seconds
Started Jan 10 12:44:11 PM PST 24
Finished Jan 10 12:45:28 PM PST 24
Peak memory 234612 kb
Host smart-021ef335-859f-4e3c-b355-25d6063e9d9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=340852650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.340852650
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1573661233
Short name T227
Test name
Test status
Simulation time 11995353 ps
CPU time 1.32 seconds
Started Jan 10 12:34:44 PM PST 24
Finished Jan 10 12:35:27 PM PST 24
Peak memory 235408 kb
Host smart-14f74b36-51cd-42e8-9e8a-acef56baef0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1573661233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1573661233
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3660596834
Short name T226
Test name
Test status
Simulation time 7517544 ps
CPU time 1.38 seconds
Started Jan 10 12:40:06 PM PST 24
Finished Jan 10 12:40:53 PM PST 24
Peak memory 236320 kb
Host smart-928ddb91-f750-4d9e-9902-e4b6b3274d82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3660596834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3660596834
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3691440749
Short name T800
Test name
Test status
Simulation time 17474076 ps
CPU time 1.46 seconds
Started Jan 10 12:44:15 PM PST 24
Finished Jan 10 12:45:33 PM PST 24
Peak memory 236224 kb
Host smart-98774baf-756e-4c10-844f-70f20271cd88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3691440749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3691440749
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3419860137
Short name T779
Test name
Test status
Simulation time 26841744 ps
CPU time 1.28 seconds
Started Jan 10 12:44:39 PM PST 24
Finished Jan 10 12:45:57 PM PST 24
Peak memory 235640 kb
Host smart-e994c8ce-b517-4b14-97d9-402e21c9e63d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3419860137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3419860137
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2412410959
Short name T802
Test name
Test status
Simulation time 12866282 ps
CPU time 1.57 seconds
Started Jan 10 12:54:13 PM PST 24
Finished Jan 10 12:55:21 PM PST 24
Peak memory 235012 kb
Host smart-081aa63f-55db-411d-bf63-bb4207002c46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2412410959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2412410959
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2094021692
Short name T782
Test name
Test status
Simulation time 7230444 ps
CPU time 1.41 seconds
Started Jan 10 12:29:06 PM PST 24
Finished Jan 10 12:29:29 PM PST 24
Peak memory 234544 kb
Host smart-7b3fbf6a-1648-4872-9d94-8f2dc825fa34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2094021692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2094021692
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3132696544
Short name T805
Test name
Test status
Simulation time 12460136 ps
CPU time 1.28 seconds
Started Jan 10 12:49:58 PM PST 24
Finished Jan 10 12:51:37 PM PST 24
Peak memory 235500 kb
Host smart-1ece688f-f64f-4741-b7ad-0aee1378f996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3132696544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3132696544
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2768111123
Short name T790
Test name
Test status
Simulation time 7175457 ps
CPU time 1.24 seconds
Started Jan 10 12:51:37 PM PST 24
Finished Jan 10 12:53:04 PM PST 24
Peak memory 235484 kb
Host smart-f045fbb6-8243-42c3-b3e4-6538494789b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2768111123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2768111123
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2802927000
Short name T788
Test name
Test status
Simulation time 1214117560 ps
CPU time 57.68 seconds
Started Jan 10 12:29:13 PM PST 24
Finished Jan 10 12:30:33 PM PST 24
Peak memory 240044 kb
Host smart-82ea87e9-2805-4d0a-8dc0-f923e156d7e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2802927000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2802927000
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2409583015
Short name T841
Test name
Test status
Simulation time 8936004359 ps
CPU time 417.41 seconds
Started Jan 10 12:26:45 PM PST 24
Finished Jan 10 12:33:47 PM PST 24
Peak memory 240352 kb
Host smart-7a242ef9-91f0-4021-93f5-832ed9ed8fec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2409583015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2409583015
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2379671133
Short name T799
Test name
Test status
Simulation time 39365050 ps
CPU time 4.11 seconds
Started Jan 10 12:26:19 PM PST 24
Finished Jan 10 12:26:25 PM PST 24
Peak memory 240624 kb
Host smart-2dc081a9-07cd-4866-b281-6bf9c2632fcf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2379671133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2379671133
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2561222886
Short name T763
Test name
Test status
Simulation time 65941219 ps
CPU time 3.97 seconds
Started Jan 10 12:27:12 PM PST 24
Finished Jan 10 12:27:21 PM PST 24
Peak memory 255748 kb
Host smart-09577d4f-d409-4f9c-9ee0-7da3591bf22c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561222886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2561222886
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.230305199
Short name T164
Test name
Test status
Simulation time 142014350 ps
CPU time 5.07 seconds
Started Jan 10 12:29:53 PM PST 24
Finished Jan 10 12:30:35 PM PST 24
Peak memory 239976 kb
Host smart-025a7851-7d83-4bef-8902-4a4412c0d0e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=230305199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.230305199
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3418724068
Short name T821
Test name
Test status
Simulation time 9493061 ps
CPU time 1.5 seconds
Started Jan 10 12:29:11 PM PST 24
Finished Jan 10 12:29:35 PM PST 24
Peak memory 235232 kb
Host smart-c177f33e-e7a4-49a9-9ae4-192efd52ce77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3418724068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3418724068
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3684262946
Short name T188
Test name
Test status
Simulation time 2026953507 ps
CPU time 38.69 seconds
Started Jan 10 12:28:16 PM PST 24
Finished Jan 10 12:29:09 PM PST 24
Peak memory 244872 kb
Host smart-84f0cad8-1c7c-412d-b466-67f04bebcab1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3684262946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3684262946
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2444326413
Short name T146
Test name
Test status
Simulation time 2848229591 ps
CPU time 181.64 seconds
Started Jan 10 12:26:18 PM PST 24
Finished Jan 10 12:29:22 PM PST 24
Peak memory 266324 kb
Host smart-e339cd29-4a4a-49f8-90ad-9f1ff9645603
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2444326413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2444326413
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1268989148
Short name T785
Test name
Test status
Simulation time 253770704 ps
CPU time 10.01 seconds
Started Jan 10 12:26:35 PM PST 24
Finished Jan 10 12:26:48 PM PST 24
Peak memory 247268 kb
Host smart-798e1f1d-d4a2-4c61-833e-7ba49372a470
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1268989148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1268989148
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3536630564
Short name T749
Test name
Test status
Simulation time 7748533 ps
CPU time 1.32 seconds
Started Jan 10 12:41:09 PM PST 24
Finished Jan 10 12:42:11 PM PST 24
Peak memory 236484 kb
Host smart-2be78c1c-2a76-4c10-9847-b8bbfece8a26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3536630564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3536630564
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.490115409
Short name T772
Test name
Test status
Simulation time 17982598 ps
CPU time 1.34 seconds
Started Jan 10 12:50:43 PM PST 24
Finished Jan 10 12:52:06 PM PST 24
Peak memory 234692 kb
Host smart-81a7a3f5-cb6b-44c3-8b08-2827a36fee32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=490115409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.490115409
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2745287041
Short name T837
Test name
Test status
Simulation time 7829220 ps
CPU time 1.26 seconds
Started Jan 10 12:53:53 PM PST 24
Finished Jan 10 12:55:04 PM PST 24
Peak memory 236356 kb
Host smart-06d1acbc-de1f-4102-8bed-f110fb40d78c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2745287041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2745287041
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1283680690
Short name T741
Test name
Test status
Simulation time 7614311 ps
CPU time 1.32 seconds
Started Jan 10 12:34:48 PM PST 24
Finished Jan 10 12:35:31 PM PST 24
Peak memory 236480 kb
Host smart-8df4acbd-248a-49c3-ba14-7e4b0984a660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1283680690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1283680690
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4028867164
Short name T791
Test name
Test status
Simulation time 11994145 ps
CPU time 1.54 seconds
Started Jan 10 12:35:51 PM PST 24
Finished Jan 10 12:36:16 PM PST 24
Peak memory 236480 kb
Host smart-05847da6-0e0e-435f-9cc9-04f40f7a5e18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4028867164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.4028867164
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.792902182
Short name T755
Test name
Test status
Simulation time 15087214 ps
CPU time 1.31 seconds
Started Jan 10 12:50:38 PM PST 24
Finished Jan 10 12:51:57 PM PST 24
Peak memory 236408 kb
Host smart-c0d7d471-a7ed-413b-a929-d62e1c44348d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=792902182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.792902182
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3282956282
Short name T778
Test name
Test status
Simulation time 17884509 ps
CPU time 1.37 seconds
Started Jan 10 12:28:34 PM PST 24
Finished Jan 10 12:28:47 PM PST 24
Peak memory 236500 kb
Host smart-ec5ac57a-96e3-464b-a847-6a3fcc41d7f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3282956282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3282956282
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4224533505
Short name T359
Test name
Test status
Simulation time 6455932 ps
CPU time 1.38 seconds
Started Jan 10 12:39:37 PM PST 24
Finished Jan 10 12:40:08 PM PST 24
Peak memory 236404 kb
Host smart-eedfbcef-3452-4ac6-94db-593e898f3c4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4224533505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4224533505
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3743970000
Short name T771
Test name
Test status
Simulation time 6852313 ps
CPU time 1.37 seconds
Started Jan 10 12:59:12 PM PST 24
Finished Jan 10 01:00:49 PM PST 24
Peak memory 236496 kb
Host smart-69ecd88d-9218-4469-8e4e-ba8e647af0e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3743970000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3743970000
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2008945573
Short name T751
Test name
Test status
Simulation time 6649600 ps
CPU time 1.42 seconds
Started Jan 10 12:28:46 PM PST 24
Finished Jan 10 12:29:02 PM PST 24
Peak memory 236308 kb
Host smart-71442706-5ecf-4a0d-a6b9-846688761e84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2008945573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2008945573
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3295769779
Short name T824
Test name
Test status
Simulation time 16309412 ps
CPU time 3.39 seconds
Started Jan 10 12:27:18 PM PST 24
Finished Jan 10 12:27:27 PM PST 24
Peak memory 240348 kb
Host smart-f6e407a4-bb3f-4a68-9b4a-828e08ee6ce9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295769779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3295769779
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3283008773
Short name T846
Test name
Test status
Simulation time 34707730 ps
CPU time 4.87 seconds
Started Jan 10 12:26:35 PM PST 24
Finished Jan 10 12:26:44 PM PST 24
Peak memory 235028 kb
Host smart-9c7b4b36-b454-4ef5-b26d-0e490d3ad063
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3283008773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3283008773
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4065760659
Short name T773
Test name
Test status
Simulation time 11933322 ps
CPU time 1.41 seconds
Started Jan 10 12:28:38 PM PST 24
Finished Jan 10 12:28:52 PM PST 24
Peak memory 235176 kb
Host smart-bfb321a0-8721-4dd8-888e-bb523aa12acf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4065760659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.4065760659
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3965088879
Short name T750
Test name
Test status
Simulation time 523677121 ps
CPU time 31.54 seconds
Started Jan 10 12:30:10 PM PST 24
Finished Jan 10 12:31:22 PM PST 24
Peak memory 243288 kb
Host smart-e20a55ad-0fd4-44a0-a5f1-5ee2b0d2854c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3965088879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3965088879
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.4049322060
Short name T135
Test name
Test status
Simulation time 5665522542 ps
CPU time 327.02 seconds
Started Jan 10 12:32:21 PM PST 24
Finished Jan 10 12:38:26 PM PST 24
Peak memory 264920 kb
Host smart-3e8d1ea6-8422-4d35-9bd4-817355bcfc0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4049322060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.4049322060
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.4112453148
Short name T364
Test name
Test status
Simulation time 15414640969 ps
CPU time 586.24 seconds
Started Jan 10 12:24:33 PM PST 24
Finished Jan 10 12:34:20 PM PST 24
Peak memory 265224 kb
Host smart-4037c59a-f79a-47a5-a2f5-35cfa5645d33
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112453148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.4112453148
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2601463312
Short name T792
Test name
Test status
Simulation time 2251723800 ps
CPU time 15.69 seconds
Started Jan 10 12:29:02 PM PST 24
Finished Jan 10 12:29:37 PM PST 24
Peak memory 248560 kb
Host smart-afc76159-2682-4c47-93d0-9caf69493f72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2601463312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2601463312
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1554587304
Short name T817
Test name
Test status
Simulation time 112770677 ps
CPU time 6.61 seconds
Started Jan 10 12:26:49 PM PST 24
Finished Jan 10 12:27:00 PM PST 24
Peak memory 251800 kb
Host smart-12c47fd9-a805-40b4-b7c3-57d5f8a31610
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554587304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1554587304
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.47158784
Short name T780
Test name
Test status
Simulation time 181685068 ps
CPU time 7.7 seconds
Started Jan 10 12:27:28 PM PST 24
Finished Jan 10 12:27:41 PM PST 24
Peak memory 240148 kb
Host smart-ef920f2f-6de3-426e-bc82-9809ec34e2ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=47158784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.47158784
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3321353529
Short name T829
Test name
Test status
Simulation time 8695698 ps
CPU time 1.27 seconds
Started Jan 10 12:29:49 PM PST 24
Finished Jan 10 12:30:25 PM PST 24
Peak memory 235172 kb
Host smart-7f45812e-6f45-4584-a683-a05e04ce9a16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3321353529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3321353529
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.48078658
Short name T745
Test name
Test status
Simulation time 1109392541 ps
CPU time 41.41 seconds
Started Jan 10 12:26:58 PM PST 24
Finished Jan 10 12:27:46 PM PST 24
Peak memory 244672 kb
Host smart-703d6842-4e4d-41aa-b987-4338d185992a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=48078658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outst
anding.48078658
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3366763156
Short name T157
Test name
Test status
Simulation time 2172427829 ps
CPU time 212.21 seconds
Started Jan 10 12:29:07 PM PST 24
Finished Jan 10 12:33:00 PM PST 24
Peak memory 264728 kb
Host smart-d9d67bd0-3724-4a01-9890-001c26d40540
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3366763156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3366763156
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.333908938
Short name T363
Test name
Test status
Simulation time 24625848243 ps
CPU time 251.9 seconds
Started Jan 10 12:29:50 PM PST 24
Finished Jan 10 12:34:38 PM PST 24
Peak memory 264924 kb
Host smart-841360ed-f4e3-4201-bea6-c2e8379120cb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333908938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.333908938
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1656678952
Short name T781
Test name
Test status
Simulation time 168595306 ps
CPU time 5.94 seconds
Started Jan 10 12:29:10 PM PST 24
Finished Jan 10 12:29:38 PM PST 24
Peak memory 251860 kb
Host smart-c80ac868-def4-4d2a-a673-e0ed1186f23a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1656678952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1656678952
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2406579970
Short name T738
Test name
Test status
Simulation time 43448490 ps
CPU time 4.21 seconds
Started Jan 10 12:27:11 PM PST 24
Finished Jan 10 12:27:20 PM PST 24
Peak memory 237464 kb
Host smart-68bd986a-9b46-4539-9790-f03fb127b769
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406579970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2406579970
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2576961738
Short name T839
Test name
Test status
Simulation time 244346208 ps
CPU time 4.83 seconds
Started Jan 10 12:31:28 PM PST 24
Finished Jan 10 12:32:22 PM PST 24
Peak memory 236052 kb
Host smart-39f6171d-e872-47a7-812b-0a0b0f3473e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2576961738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2576961738
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3481218611
Short name T822
Test name
Test status
Simulation time 37012583 ps
CPU time 1.59 seconds
Started Jan 10 12:26:48 PM PST 24
Finished Jan 10 12:26:54 PM PST 24
Peak memory 234840 kb
Host smart-23a51ec4-7f03-41e0-8545-bd6ba5025986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3481218611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3481218611
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.838742116
Short name T803
Test name
Test status
Simulation time 351085855 ps
CPU time 24.54 seconds
Started Jan 10 12:26:34 PM PST 24
Finished Jan 10 12:27:02 PM PST 24
Peak memory 248628 kb
Host smart-ac697fe6-687a-4b63-8854-1fa8903c0228
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=838742116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.838742116
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1037283352
Short name T743
Test name
Test status
Simulation time 810457053 ps
CPU time 12.92 seconds
Started Jan 10 12:26:48 PM PST 24
Finished Jan 10 12:27:06 PM PST 24
Peak memory 245768 kb
Host smart-583184d9-9bdd-4516-bfb7-db9b6a1ce36a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1037283352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1037283352
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1633580218
Short name T176
Test name
Test status
Simulation time 295654827 ps
CPU time 21.15 seconds
Started Jan 10 12:26:48 PM PST 24
Finished Jan 10 12:27:14 PM PST 24
Peak memory 234956 kb
Host smart-fff70704-3605-45d8-9d34-4cab2af79bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1633580218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1633580218
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2181828386
Short name T756
Test name
Test status
Simulation time 34490387 ps
CPU time 6.05 seconds
Started Jan 10 12:27:33 PM PST 24
Finished Jan 10 12:27:45 PM PST 24
Peak memory 242744 kb
Host smart-a8b94147-e4bf-4145-962b-d696751195b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181828386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2181828386
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3156417231
Short name T845
Test name
Test status
Simulation time 95650331 ps
CPU time 3.9 seconds
Started Jan 10 12:31:16 PM PST 24
Finished Jan 10 12:32:04 PM PST 24
Peak memory 234908 kb
Host smart-09bac9af-4c81-46cc-8b45-7f24a7b921e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3156417231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3156417231
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3153160192
Short name T357
Test name
Test status
Simulation time 9978189 ps
CPU time 1.55 seconds
Started Jan 10 12:27:24 PM PST 24
Finished Jan 10 12:27:31 PM PST 24
Peak memory 235404 kb
Host smart-b2c1ff6d-a897-4c6a-8387-bfad17ed5d3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3153160192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3153160192
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1406299952
Short name T369
Test name
Test status
Simulation time 168140892 ps
CPU time 21.12 seconds
Started Jan 10 12:27:29 PM PST 24
Finished Jan 10 12:27:56 PM PST 24
Peak memory 248396 kb
Host smart-695d1cec-c843-44cb-b216-3ac3b8305686
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1406299952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1406299952
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3206437901
Short name T162
Test name
Test status
Simulation time 2032044439 ps
CPU time 142.3 seconds
Started Jan 10 12:27:53 PM PST 24
Finished Jan 10 12:30:29 PM PST 24
Peak memory 265148 kb
Host smart-01fe979e-d9a4-4e69-9867-093e2aec1b16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3206437901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3206437901
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2472081368
Short name T150
Test name
Test status
Simulation time 4565028591 ps
CPU time 554.81 seconds
Started Jan 10 12:31:05 PM PST 24
Finished Jan 10 12:41:06 PM PST 24
Peak memory 264836 kb
Host smart-f70d58e4-f661-4aa4-9547-6edbd0af900f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472081368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2472081368
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.470124646
Short name T843
Test name
Test status
Simulation time 98020252 ps
CPU time 3.7 seconds
Started Jan 10 12:26:48 PM PST 24
Finished Jan 10 12:26:57 PM PST 24
Peak memory 246548 kb
Host smart-9d31eabe-d023-4900-a9af-975c1f163372
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=470124646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.470124646
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1105277433
Short name T181
Test name
Test status
Simulation time 78395649 ps
CPU time 2.61 seconds
Started Jan 10 12:27:47 PM PST 24
Finished Jan 10 12:28:02 PM PST 24
Peak memory 236396 kb
Host smart-d0b1e466-0cac-46f5-a817-609e77f0f101
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1105277433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1105277433
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3189280727
Short name T740
Test name
Test status
Simulation time 155172984 ps
CPU time 6.84 seconds
Started Jan 10 12:28:31 PM PST 24
Finished Jan 10 12:28:49 PM PST 24
Peak memory 242544 kb
Host smart-4053dceb-5008-4322-bdef-81eee2593cce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189280727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3189280727
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.53438000
Short name T366
Test name
Test status
Simulation time 33893997 ps
CPU time 4.93 seconds
Started Jan 10 12:26:35 PM PST 24
Finished Jan 10 12:26:43 PM PST 24
Peak memory 239404 kb
Host smart-c32b6b0e-b963-4683-a5c4-80bfbe7e2d84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=53438000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.53438000
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1446864341
Short name T361
Test name
Test status
Simulation time 12203105 ps
CPU time 1.62 seconds
Started Jan 10 12:27:54 PM PST 24
Finished Jan 10 12:28:08 PM PST 24
Peak memory 236296 kb
Host smart-2998dcf4-2dda-4ad0-9e3c-5e7e616a9917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1446864341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1446864341
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1198513112
Short name T744
Test name
Test status
Simulation time 497007903 ps
CPU time 15.34 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:31:00 PM PST 24
Peak memory 239124 kb
Host smart-c370f5c1-90ad-421f-b510-0cc0ff50b8c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1198513112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1198513112
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3752385445
Short name T141
Test name
Test status
Simulation time 3604658440 ps
CPU time 182.03 seconds
Started Jan 10 12:31:17 PM PST 24
Finished Jan 10 12:35:06 PM PST 24
Peak memory 256480 kb
Host smart-7b6ce596-1ac2-41c1-8571-ce1a262728a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3752385445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3752385445
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3545134414
Short name T166
Test name
Test status
Simulation time 12406751756 ps
CPU time 410.22 seconds
Started Jan 10 12:30:37 PM PST 24
Finished Jan 10 12:38:10 PM PST 24
Peak memory 268788 kb
Host smart-a678e2d2-d0b6-4aa4-9b9a-423a409d3854
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545134414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3545134414
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.115415153
Short name T752
Test name
Test status
Simulation time 39869117 ps
CPU time 4.78 seconds
Started Jan 10 12:31:15 PM PST 24
Finished Jan 10 12:32:05 PM PST 24
Peak memory 251904 kb
Host smart-d2911622-9424-429c-bcd8-3cac48b83daf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=115415153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.115415153
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2511798558
Short name T189
Test name
Test status
Simulation time 62759927 ps
CPU time 2.7 seconds
Started Jan 10 12:26:39 PM PST 24
Finished Jan 10 12:26:48 PM PST 24
Peak memory 236376 kb
Host smart-cab759fb-56da-4989-b330-662f0e5cbe2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2511798558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2511798558
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3699341500
Short name T555
Test name
Test status
Simulation time 14928910460 ps
CPU time 1120.17 seconds
Started Jan 10 12:28:20 PM PST 24
Finished Jan 10 12:47:13 PM PST 24
Peak memory 289324 kb
Host smart-a103adb3-b9e2-4717-a80d-2186731d56e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699341500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3699341500
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1682364568
Short name T535
Test name
Test status
Simulation time 795538500 ps
CPU time 8.92 seconds
Started Jan 10 12:30:28 PM PST 24
Finished Jan 10 12:31:19 PM PST 24
Peak memory 240092 kb
Host smart-48cb2c0e-51ff-46f3-a475-993a70352fcc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1682364568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1682364568
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.4559254
Short name T472
Test name
Test status
Simulation time 2078576522 ps
CPU time 160.77 seconds
Started Jan 10 12:27:59 PM PST 24
Finished Jan 10 12:30:54 PM PST 24
Peak memory 256140 kb
Host smart-4f93c700-cc37-4f01-b96b-f121f1709821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45592
54 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.4559254
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2637322881
Short name T402
Test name
Test status
Simulation time 810957288 ps
CPU time 43.83 seconds
Started Jan 10 12:28:05 PM PST 24
Finished Jan 10 12:29:04 PM PST 24
Peak memory 254004 kb
Host smart-6658d1dc-3d2b-4857-8457-32c25fcb73b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26373
22881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2637322881
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.902293136
Short name T10
Test name
Test status
Simulation time 114256392403 ps
CPU time 1743.86 seconds
Started Jan 10 12:27:52 PM PST 24
Finished Jan 10 12:57:10 PM PST 24
Peak memory 272420 kb
Host smart-dab7b12b-f45a-4f95-9de1-c2f4cd21f383
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902293136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.902293136
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3561823163
Short name T483
Test name
Test status
Simulation time 77521344112 ps
CPU time 1341.96 seconds
Started Jan 10 12:27:53 PM PST 24
Finished Jan 10 12:50:29 PM PST 24
Peak memory 273068 kb
Host smart-f8590046-f216-4938-b123-56d4b8255c88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561823163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3561823163
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.886351539
Short name T13
Test name
Test status
Simulation time 37152173017 ps
CPU time 243.5 seconds
Started Jan 10 12:27:54 PM PST 24
Finished Jan 10 12:32:10 PM PST 24
Peak memory 246520 kb
Host smart-023926ce-7dff-4e6b-ae8a-960df77cd3dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886351539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.886351539
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1280359211
Short name T498
Test name
Test status
Simulation time 904864628 ps
CPU time 19.71 seconds
Started Jan 10 12:28:07 PM PST 24
Finished Jan 10 12:28:43 PM PST 24
Peak memory 255116 kb
Host smart-961f2ee3-bd9b-449f-bf2a-1f47b8ee5409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12803
59211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1280359211
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.376855556
Short name T410
Test name
Test status
Simulation time 3687707735 ps
CPU time 52.59 seconds
Started Jan 10 12:28:01 PM PST 24
Finished Jan 10 12:29:08 PM PST 24
Peak memory 255576 kb
Host smart-5bfaa8c9-4bc1-4d94-b4da-abf8ae1c1588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37685
5556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.376855556
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1923991212
Short name T15
Test name
Test status
Simulation time 634388085 ps
CPU time 11.12 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 12:30:54 PM PST 24
Peak memory 269228 kb
Host smart-602493fd-f20a-4ee5-9fce-86857d284520
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1923991212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1923991212
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2175280152
Short name T305
Test name
Test status
Simulation time 456830847 ps
CPU time 24.89 seconds
Started Jan 10 12:30:35 PM PST 24
Finished Jan 10 12:31:42 PM PST 24
Peak memory 248296 kb
Host smart-86f8c428-6ade-47ed-b993-15a3bc355218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21752
80152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2175280152
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.588754432
Short name T443
Test name
Test status
Simulation time 50442685 ps
CPU time 5.6 seconds
Started Jan 10 12:29:48 PM PST 24
Finished Jan 10 12:30:27 PM PST 24
Peak memory 248256 kb
Host smart-818d6929-9402-4493-b254-10125eb1ce90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58875
4432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.588754432
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3273745266
Short name T537
Test name
Test status
Simulation time 22938158900 ps
CPU time 2199.79 seconds
Started Jan 10 12:30:41 PM PST 24
Finished Jan 10 01:08:04 PM PST 24
Peak memory 314248 kb
Host smart-929e855f-acd1-4cf9-aa85-f255dfe81977
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273745266 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3273745266
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3190122707
Short name T423
Test name
Test status
Simulation time 74061450442 ps
CPU time 1081.41 seconds
Started Jan 10 12:32:21 PM PST 24
Finished Jan 10 12:51:01 PM PST 24
Peak memory 287000 kb
Host smart-9b96171f-3ca0-48ca-b892-fbed3ebe6be2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190122707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3190122707
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.220419890
Short name T489
Test name
Test status
Simulation time 12667412987 ps
CPU time 51.42 seconds
Started Jan 10 12:31:47 PM PST 24
Finished Jan 10 12:33:27 PM PST 24
Peak memory 247012 kb
Host smart-dfc2cb30-a9da-4176-865c-fe941b5e4148
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=220419890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.220419890
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.765369729
Short name T520
Test name
Test status
Simulation time 970406239 ps
CPU time 19.22 seconds
Started Jan 10 12:28:05 PM PST 24
Finished Jan 10 12:28:40 PM PST 24
Peak memory 255196 kb
Host smart-c058d753-8f6a-4767-80a8-7c7551c15322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76536
9729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.765369729
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3453792742
Short name T592
Test name
Test status
Simulation time 2452868822 ps
CPU time 35.93 seconds
Started Jan 10 12:29:31 PM PST 24
Finished Jan 10 12:30:32 PM PST 24
Peak memory 254272 kb
Host smart-588f53e6-141b-4ecd-8676-b24603cf8011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34537
92742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3453792742
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3396437975
Short name T705
Test name
Test status
Simulation time 417466829161 ps
CPU time 1356.55 seconds
Started Jan 10 12:32:01 PM PST 24
Finished Jan 10 12:55:24 PM PST 24
Peak memory 271496 kb
Host smart-f4670989-1828-4fa2-916b-067726d6592f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396437975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3396437975
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.175565133
Short name T615
Test name
Test status
Simulation time 127241190 ps
CPU time 4.38 seconds
Started Jan 10 12:28:01 PM PST 24
Finished Jan 10 12:28:20 PM PST 24
Peak memory 240308 kb
Host smart-5440ee4b-bcc5-4499-ae59-b43a10a2872e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17556
5133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.175565133
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2228345749
Short name T531
Test name
Test status
Simulation time 880009669 ps
CPU time 36.96 seconds
Started Jan 10 12:30:33 PM PST 24
Finished Jan 10 12:31:52 PM PST 24
Peak memory 254952 kb
Host smart-fc40bbe8-b019-4fa4-8719-64d10441fca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22283
45749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2228345749
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1340068376
Short name T46
Test name
Test status
Simulation time 987355509 ps
CPU time 11.4 seconds
Started Jan 10 12:28:34 PM PST 24
Finished Jan 10 12:28:57 PM PST 24
Peak memory 273364 kb
Host smart-2a16607d-cdbf-4267-85ce-626a92056060
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1340068376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1340068376
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3358359617
Short name T403
Test name
Test status
Simulation time 305408600 ps
CPU time 24.16 seconds
Started Jan 10 12:30:48 PM PST 24
Finished Jan 10 12:32:01 PM PST 24
Peak memory 248516 kb
Host smart-7ac5e790-e1b6-4dff-b51c-c6a724616d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33583
59617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3358359617
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2610545011
Short name T96
Test name
Test status
Simulation time 91980757719 ps
CPU time 2220.04 seconds
Started Jan 10 12:28:15 PM PST 24
Finished Jan 10 01:05:30 PM PST 24
Peak memory 302640 kb
Host smart-8399a774-fa2c-48c0-ad42-a2138d439323
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610545011 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2610545011
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3487117539
Short name T637
Test name
Test status
Simulation time 13430387901 ps
CPU time 647.54 seconds
Started Jan 10 12:28:18 PM PST 24
Finished Jan 10 12:39:19 PM PST 24
Peak memory 264972 kb
Host smart-62912c19-c1d2-42d0-b925-9c0095da06c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487117539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3487117539
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.348668281
Short name T389
Test name
Test status
Simulation time 452254479 ps
CPU time 19.32 seconds
Started Jan 10 12:31:52 PM PST 24
Finished Jan 10 12:32:58 PM PST 24
Peak memory 239932 kb
Host smart-57340e66-b664-4b63-8910-7b57755f1424
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=348668281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.348668281
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.311263442
Short name T663
Test name
Test status
Simulation time 385577616 ps
CPU time 38.49 seconds
Started Jan 10 12:28:25 PM PST 24
Finished Jan 10 12:29:14 PM PST 24
Peak memory 256200 kb
Host smart-305554c4-31b5-4ce7-bb6a-0d3aa465b352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31126
3442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.311263442
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3099686979
Short name T83
Test name
Test status
Simulation time 234179904 ps
CPU time 18.03 seconds
Started Jan 10 12:31:50 PM PST 24
Finished Jan 10 12:32:55 PM PST 24
Peak memory 254352 kb
Host smart-621fe738-a43c-415b-9b51-b25e9b575c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30996
86979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3099686979
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1888862412
Short name T344
Test name
Test status
Simulation time 56545630441 ps
CPU time 1457.99 seconds
Started Jan 10 12:28:27 PM PST 24
Finished Jan 10 12:52:56 PM PST 24
Peak memory 272668 kb
Host smart-99e436a0-a691-49c1-90d4-7ea10effc00c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888862412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1888862412
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1177401019
Short name T651
Test name
Test status
Simulation time 28406742909 ps
CPU time 1478.64 seconds
Started Jan 10 12:34:42 PM PST 24
Finished Jan 10 01:00:02 PM PST 24
Peak memory 271452 kb
Host smart-7561598d-a768-403d-8163-d639f386d3c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177401019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1177401019
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3442817451
Short name T425
Test name
Test status
Simulation time 1070748755 ps
CPU time 32.49 seconds
Started Jan 10 12:31:56 PM PST 24
Finished Jan 10 12:33:15 PM PST 24
Peak memory 248136 kb
Host smart-eb5b4688-380c-4c0a-a596-22b739c69f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34428
17451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3442817451
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1193272865
Short name T706
Test name
Test status
Simulation time 753123094 ps
CPU time 42.86 seconds
Started Jan 10 12:34:39 PM PST 24
Finished Jan 10 12:36:03 PM PST 24
Peak memory 254740 kb
Host smart-49af8dc5-d370-4a96-99b7-bbadef2c8dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11932
72865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1193272865
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3136706076
Short name T727
Test name
Test status
Simulation time 841516302 ps
CPU time 24.95 seconds
Started Jan 10 12:31:49 PM PST 24
Finished Jan 10 12:33:01 PM PST 24
Peak memory 248072 kb
Host smart-c89c1078-1f40-4766-b0e3-bfe92ddd68bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31367
06076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3136706076
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3366126158
Short name T78
Test name
Test status
Simulation time 1129705022 ps
CPU time 19.86 seconds
Started Jan 10 12:34:42 PM PST 24
Finished Jan 10 12:35:43 PM PST 24
Peak memory 248256 kb
Host smart-ffcc2bb9-4445-45da-b951-b9a8a374868c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33661
26158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3366126158
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2917861061
Short name T399
Test name
Test status
Simulation time 213706469 ps
CPU time 11.05 seconds
Started Jan 10 12:31:57 PM PST 24
Finished Jan 10 12:32:55 PM PST 24
Peak memory 252504 kb
Host smart-c2ad8aba-f3e4-4f55-bde7-33460aa49767
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917861061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2917861061
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.305965100
Short name T108
Test name
Test status
Simulation time 38442492159 ps
CPU time 1115.71 seconds
Started Jan 10 12:31:57 PM PST 24
Finished Jan 10 12:51:20 PM PST 24
Peak memory 280628 kb
Host smart-783643a2-683f-4aae-92ae-63d123e7cad8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305965100 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.305965100
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.160558578
Short name T74
Test name
Test status
Simulation time 141053562 ps
CPU time 3.11 seconds
Started Jan 10 12:32:06 PM PST 24
Finished Jan 10 12:32:54 PM PST 24
Peak memory 248304 kb
Host smart-6d8dd461-92e3-49af-807f-b3aef11481c2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=160558578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.160558578
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3105202590
Short name T617
Test name
Test status
Simulation time 13449028450 ps
CPU time 1009.93 seconds
Started Jan 10 12:31:54 PM PST 24
Finished Jan 10 12:49:30 PM PST 24
Peak memory 286124 kb
Host smart-ebe1d076-a792-4538-9965-705fa665db5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105202590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3105202590
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.4195538119
Short name T685
Test name
Test status
Simulation time 704067068 ps
CPU time 29.17 seconds
Started Jan 10 12:28:32 PM PST 24
Finished Jan 10 12:29:13 PM PST 24
Peak memory 240260 kb
Host smart-00cf38b9-0428-4ad5-979c-a7662f331731
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4195538119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.4195538119
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2805310885
Short name T375
Test name
Test status
Simulation time 743459697 ps
CPU time 29.37 seconds
Started Jan 10 12:28:33 PM PST 24
Finished Jan 10 12:29:15 PM PST 24
Peak memory 248024 kb
Host smart-1f23962d-fd8c-4325-95ed-5cfdd59981c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28053
10885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2805310885
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2725927484
Short name T100
Test name
Test status
Simulation time 1491813905 ps
CPU time 21.65 seconds
Started Jan 10 12:31:57 PM PST 24
Finished Jan 10 12:33:06 PM PST 24
Peak memory 251916 kb
Host smart-b519da88-15ab-4ae2-a40c-bb0f464031ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27259
27484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2725927484
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.280343220
Short name T707
Test name
Test status
Simulation time 11852547050 ps
CPU time 1115.06 seconds
Started Jan 10 12:28:25 PM PST 24
Finished Jan 10 12:47:11 PM PST 24
Peak memory 288996 kb
Host smart-fd3e2dc4-0c17-4cc4-98ce-ccfafb19f61b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280343220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.280343220
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2612803962
Short name T681
Test name
Test status
Simulation time 163107868769 ps
CPU time 2569.11 seconds
Started Jan 10 12:32:04 PM PST 24
Finished Jan 10 01:15:39 PM PST 24
Peak memory 289000 kb
Host smart-70456304-11bd-4010-8bd8-3814e11706f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612803962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2612803962
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.856106177
Short name T112
Test name
Test status
Simulation time 899826866 ps
CPU time 26.54 seconds
Started Jan 10 12:28:34 PM PST 24
Finished Jan 10 12:29:13 PM PST 24
Peak memory 248568 kb
Host smart-82009cb9-e772-4b83-ac8c-a2022495cf57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85610
6177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.856106177
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1051855152
Short name T391
Test name
Test status
Simulation time 193963772 ps
CPU time 13.48 seconds
Started Jan 10 12:31:58 PM PST 24
Finished Jan 10 12:32:58 PM PST 24
Peak memory 246880 kb
Host smart-7d44d668-bd62-40d0-8a73-56a88990f5fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10518
55152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1051855152
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3068108302
Short name T496
Test name
Test status
Simulation time 1043935470 ps
CPU time 61.64 seconds
Started Jan 10 12:28:33 PM PST 24
Finished Jan 10 12:29:47 PM PST 24
Peak memory 248560 kb
Host smart-1a489caa-3ba1-444c-9790-6756a9989294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30681
08302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3068108302
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2533639635
Short name T611
Test name
Test status
Simulation time 2518948208 ps
CPU time 23.46 seconds
Started Jan 10 12:31:57 PM PST 24
Finished Jan 10 12:33:07 PM PST 24
Peak memory 246524 kb
Host smart-6d31492e-4623-4ecd-8c0a-ac647f61e561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25336
39635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2533639635
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2939137994
Short name T664
Test name
Test status
Simulation time 29708369177 ps
CPU time 1127.98 seconds
Started Jan 10 12:31:58 PM PST 24
Finished Jan 10 12:51:32 PM PST 24
Peak memory 287564 kb
Host smart-e0381fc3-d32f-4d79-825c-21fcedf8e39b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939137994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2939137994
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.590676800
Short name T568
Test name
Test status
Simulation time 20149502775 ps
CPU time 1118.11 seconds
Started Jan 10 12:32:00 PM PST 24
Finished Jan 10 12:51:25 PM PST 24
Peak memory 270816 kb
Host smart-7b2cffb2-a452-4d0b-9aae-f357fbd40c42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590676800 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.590676800
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.321622306
Short name T200
Test name
Test status
Simulation time 42786727 ps
CPU time 3.28 seconds
Started Jan 10 12:28:28 PM PST 24
Finished Jan 10 12:28:42 PM PST 24
Peak memory 248676 kb
Host smart-e48d1bb8-5606-41a7-b5e5-38412ce62016
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=321622306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.321622306
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.4008157948
Short name T18
Test name
Test status
Simulation time 28608325213 ps
CPU time 1183.53 seconds
Started Jan 10 12:32:18 PM PST 24
Finished Jan 10 12:52:42 PM PST 24
Peak memory 280576 kb
Host smart-63aec032-09d7-4cc8-8b9a-20a9c30c152b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008157948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.4008157948
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1399944737
Short name T459
Test name
Test status
Simulation time 2472484089 ps
CPU time 133.24 seconds
Started Jan 10 12:32:13 PM PST 24
Finished Jan 10 12:35:08 PM PST 24
Peak memory 250232 kb
Host smart-ccac8fe9-206c-4340-8a7e-f1948684f0e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13999
44737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1399944737
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3295173139
Short name T77
Test name
Test status
Simulation time 259662748 ps
CPU time 21.38 seconds
Started Jan 10 12:32:04 PM PST 24
Finished Jan 10 12:33:11 PM PST 24
Peak memory 254480 kb
Host smart-ab3d6941-76c5-445c-a6fc-5fc9c83a008c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32951
73139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3295173139
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1399834965
Short name T266
Test name
Test status
Simulation time 17601142926 ps
CPU time 1214.96 seconds
Started Jan 10 12:32:00 PM PST 24
Finished Jan 10 12:53:02 PM PST 24
Peak memory 287296 kb
Host smart-5b197d2f-8674-4503-a8dc-c8e2942d4b9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399834965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1399834965
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.959342106
Short name T393
Test name
Test status
Simulation time 82776808494 ps
CPU time 2427.06 seconds
Started Jan 10 12:28:28 PM PST 24
Finished Jan 10 01:09:06 PM PST 24
Peak memory 289120 kb
Host smart-5f93a59d-1668-430a-a821-25e940cd3f36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959342106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.959342106
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.742095180
Short name T720
Test name
Test status
Simulation time 6361712568 ps
CPU time 121.64 seconds
Started Jan 10 12:31:59 PM PST 24
Finished Jan 10 12:34:47 PM PST 24
Peak memory 247028 kb
Host smart-efe94d94-074a-4a69-8152-cdcbca1e1db8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742095180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.742095180
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.844741722
Short name T457
Test name
Test status
Simulation time 347119165 ps
CPU time 24.58 seconds
Started Jan 10 12:31:58 PM PST 24
Finished Jan 10 12:33:09 PM PST 24
Peak memory 253624 kb
Host smart-d2f2b8c3-82cf-4825-8a6d-b3d5ad13bbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84474
1722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.844741722
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.4000209363
Short name T490
Test name
Test status
Simulation time 702539686 ps
CPU time 11.46 seconds
Started Jan 10 12:31:58 PM PST 24
Finished Jan 10 12:32:56 PM PST 24
Peak memory 245004 kb
Host smart-d9dd50ac-768b-4dfe-bde9-83657e201a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40002
09363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.4000209363
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3627888983
Short name T487
Test name
Test status
Simulation time 547820724 ps
CPU time 8.91 seconds
Started Jan 10 12:32:00 PM PST 24
Finished Jan 10 12:32:56 PM PST 24
Peak memory 251740 kb
Host smart-c1e34923-5ad4-4792-ab9f-b59ddaa97b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36278
88983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3627888983
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2142081609
Short name T492
Test name
Test status
Simulation time 128010589 ps
CPU time 12.06 seconds
Started Jan 10 12:31:57 PM PST 24
Finished Jan 10 12:32:56 PM PST 24
Peak memory 254484 kb
Host smart-81a4588c-e609-48e1-9da0-66aaf6672496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21420
81609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2142081609
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3435385527
Short name T199
Test name
Test status
Simulation time 42651796 ps
CPU time 2.24 seconds
Started Jan 10 12:28:27 PM PST 24
Finished Jan 10 12:28:40 PM PST 24
Peak memory 248724 kb
Host smart-1f8b1aa7-f8bb-4ad3-bdda-bbc1a2fb2855
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3435385527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3435385527
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2586088662
Short name T117
Test name
Test status
Simulation time 48419379439 ps
CPU time 751.59 seconds
Started Jan 10 12:28:33 PM PST 24
Finished Jan 10 12:41:15 PM PST 24
Peak memory 273240 kb
Host smart-91801ad1-4377-4e4e-a901-5e454db8ce57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586088662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2586088662
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3789365160
Short name T728
Test name
Test status
Simulation time 1388514628 ps
CPU time 51.96 seconds
Started Jan 10 12:32:13 PM PST 24
Finished Jan 10 12:33:47 PM PST 24
Peak memory 239940 kb
Host smart-a819e3c0-9498-48e8-8523-da116583a06d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3789365160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3789365160
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.82575324
Short name T385
Test name
Test status
Simulation time 1058908009 ps
CPU time 16.2 seconds
Started Jan 10 12:28:35 PM PST 24
Finished Jan 10 12:29:03 PM PST 24
Peak memory 255176 kb
Host smart-4e174182-10e2-4519-94ad-99c5bace20b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82575
324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.82575324
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1237063955
Short name T566
Test name
Test status
Simulation time 157531625 ps
CPU time 9.71 seconds
Started Jan 10 12:29:10 PM PST 24
Finished Jan 10 12:29:42 PM PST 24
Peak memory 252484 kb
Host smart-d073f563-4bd2-4ac0-8e9c-5c068eba31f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12370
63955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1237063955
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2388491871
Short name T356
Test name
Test status
Simulation time 19223212978 ps
CPU time 743.26 seconds
Started Jan 10 12:31:50 PM PST 24
Finished Jan 10 12:45:00 PM PST 24
Peak memory 272608 kb
Host smart-d7716657-2953-4495-8263-583cfdaadb03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388491871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2388491871
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.742923915
Short name T636
Test name
Test status
Simulation time 18752441655 ps
CPU time 1415.54 seconds
Started Jan 10 12:31:32 PM PST 24
Finished Jan 10 12:55:58 PM PST 24
Peak memory 288576 kb
Host smart-aa40ce75-3a58-40bd-b076-1f6f29c34602
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742923915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.742923915
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3785338564
Short name T330
Test name
Test status
Simulation time 6225744947 ps
CPU time 233.86 seconds
Started Jan 10 12:32:02 PM PST 24
Finished Jan 10 12:36:42 PM PST 24
Peak memory 247064 kb
Host smart-46a6b663-640d-4f76-b612-f42c9d14d27b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785338564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3785338564
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3754924280
Short name T413
Test name
Test status
Simulation time 1407212929 ps
CPU time 40.48 seconds
Started Jan 10 12:28:52 PM PST 24
Finished Jan 10 12:29:50 PM PST 24
Peak memory 255020 kb
Host smart-244f2ba8-7dc1-4f81-ae17-64fe70b21dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37549
24280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3754924280
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.374896339
Short name T461
Test name
Test status
Simulation time 1154139807 ps
CPU time 25.99 seconds
Started Jan 10 12:32:09 PM PST 24
Finished Jan 10 12:33:19 PM PST 24
Peak memory 246384 kb
Host smart-bcfd87f1-a09d-462e-a018-6a9c45bd3e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37489
6339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.374896339
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1880880430
Short name T672
Test name
Test status
Simulation time 307132569 ps
CPU time 6.02 seconds
Started Jan 10 12:31:50 PM PST 24
Finished Jan 10 12:32:43 PM PST 24
Peak memory 248268 kb
Host smart-b94a4b80-dfd6-4b4a-a1ed-0955c0e65bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18808
80430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1880880430
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.819498855
Short name T484
Test name
Test status
Simulation time 46436343604 ps
CPU time 1245.57 seconds
Started Jan 10 12:28:32 PM PST 24
Finished Jan 10 12:49:28 PM PST 24
Peak memory 285864 kb
Host smart-20bc742c-c8b7-41b1-9903-e1993da545f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819498855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.819498855
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2103317100
Short name T394
Test name
Test status
Simulation time 791185783 ps
CPU time 19.03 seconds
Started Jan 10 12:28:36 PM PST 24
Finished Jan 10 12:29:07 PM PST 24
Peak memory 240352 kb
Host smart-24652ac9-91d2-4a16-9001-f3e0621268eb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2103317100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2103317100
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2021465384
Short name T493
Test name
Test status
Simulation time 434491253 ps
CPU time 18.52 seconds
Started Jan 10 12:28:34 PM PST 24
Finished Jan 10 12:29:05 PM PST 24
Peak memory 248568 kb
Host smart-298c5be0-2cd2-4c08-85e7-e0cb39d93dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20214
65384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2021465384
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2975253358
Short name T567
Test name
Test status
Simulation time 385665746 ps
CPU time 15.18 seconds
Started Jan 10 12:28:27 PM PST 24
Finished Jan 10 12:28:53 PM PST 24
Peak memory 254948 kb
Host smart-6d5f1498-8b98-4c8e-8e96-7d9fa5259fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29752
53358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2975253358
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2920975284
Short name T599
Test name
Test status
Simulation time 16965719331 ps
CPU time 1233.66 seconds
Started Jan 10 12:31:35 PM PST 24
Finished Jan 10 12:53:00 PM PST 24
Peak memory 289104 kb
Host smart-7cc8a00f-17a5-40ff-b808-9520ff6d9a8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920975284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2920975284
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2976758333
Short name T232
Test name
Test status
Simulation time 104729850666 ps
CPU time 693.26 seconds
Started Jan 10 12:31:32 PM PST 24
Finished Jan 10 12:43:56 PM PST 24
Peak memory 265624 kb
Host smart-94296ea1-38e7-4172-9e41-847f8420c608
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976758333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2976758333
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2906168408
Short name T703
Test name
Test status
Simulation time 10665044667 ps
CPU time 424.88 seconds
Started Jan 10 12:28:36 PM PST 24
Finished Jan 10 12:35:53 PM PST 24
Peak memory 248552 kb
Host smart-75a1efff-c70b-4787-820b-c6b56dfbc0a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906168408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2906168408
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.4125922888
Short name T591
Test name
Test status
Simulation time 1023376793 ps
CPU time 26.57 seconds
Started Jan 10 12:28:30 PM PST 24
Finished Jan 10 12:29:07 PM PST 24
Peak memory 255120 kb
Host smart-5f121e96-e2d3-4450-ad4e-bba6f5f90e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41259
22888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.4125922888
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.4020085257
Short name T469
Test name
Test status
Simulation time 1605289072 ps
CPU time 14.67 seconds
Started Jan 10 12:31:04 PM PST 24
Finished Jan 10 12:32:06 PM PST 24
Peak memory 249740 kb
Host smart-c654a839-2d3c-4f23-be8b-15612660b747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40200
85257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.4020085257
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2676998090
Short name T696
Test name
Test status
Simulation time 648108068 ps
CPU time 33.41 seconds
Started Jan 10 12:28:46 PM PST 24
Finished Jan 10 12:29:34 PM PST 24
Peak memory 248496 kb
Host smart-caec0baf-f79f-40b0-b4e4-558d6f802a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26769
98090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2676998090
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3674236746
Short name T558
Test name
Test status
Simulation time 3890343333 ps
CPU time 190.21 seconds
Started Jan 10 12:31:41 PM PST 24
Finished Jan 10 12:35:41 PM PST 24
Peak memory 256384 kb
Host smart-68963f01-329e-489c-a176-91b8366dd566
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674236746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3674236746
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.205234231
Short name T206
Test name
Test status
Simulation time 43444460 ps
CPU time 3.62 seconds
Started Jan 10 12:28:40 PM PST 24
Finished Jan 10 12:28:57 PM PST 24
Peak memory 248736 kb
Host smart-843462cb-f61b-418f-a2de-7e987eadd24c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=205234231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.205234231
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1236229582
Short name T570
Test name
Test status
Simulation time 46136351124 ps
CPU time 1053.87 seconds
Started Jan 10 12:28:32 PM PST 24
Finished Jan 10 12:46:17 PM PST 24
Peak memory 289564 kb
Host smart-56ff331f-0edd-4e71-910b-3ae1a34849d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236229582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1236229582
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.524229009
Short name T398
Test name
Test status
Simulation time 375610601 ps
CPU time 9.59 seconds
Started Jan 10 12:31:05 PM PST 24
Finished Jan 10 12:32:01 PM PST 24
Peak memory 239448 kb
Host smart-38de8c39-bac2-4d57-b35f-10f62188cd25
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=524229009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.524229009
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1655026559
Short name T650
Test name
Test status
Simulation time 221671844 ps
CPU time 7.43 seconds
Started Jan 10 12:31:56 PM PST 24
Finished Jan 10 12:32:50 PM PST 24
Peak memory 239152 kb
Host smart-a07cca40-db67-4b1c-80d8-de0fa64b1eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16550
26559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1655026559
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3114741077
Short name T435
Test name
Test status
Simulation time 682995304 ps
CPU time 37.42 seconds
Started Jan 10 12:31:57 PM PST 24
Finished Jan 10 12:33:21 PM PST 24
Peak memory 253736 kb
Host smart-91ccf3bf-af3f-43f2-91fc-a4e2606e8135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31147
41077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3114741077
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2387054656
Short name T680
Test name
Test status
Simulation time 21401273326 ps
CPU time 1180.81 seconds
Started Jan 10 12:31:56 PM PST 24
Finished Jan 10 12:52:23 PM PST 24
Peak memory 282300 kb
Host smart-686fd7ce-9196-4bef-a958-ece1bcdd1e25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387054656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2387054656
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1847428376
Short name T588
Test name
Test status
Simulation time 26743703672 ps
CPU time 1497.89 seconds
Started Jan 10 12:28:28 PM PST 24
Finished Jan 10 12:53:37 PM PST 24
Peak memory 272024 kb
Host smart-09b5bbb1-d154-4ccc-83ef-7aa595d447b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847428376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1847428376
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1168771255
Short name T645
Test name
Test status
Simulation time 1936413695 ps
CPU time 78.41 seconds
Started Jan 10 12:28:31 PM PST 24
Finished Jan 10 12:29:59 PM PST 24
Peak memory 247312 kb
Host smart-626f4460-ca68-4e98-8e62-0e1ad9e8d9b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168771255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1168771255
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1979499031
Short name T578
Test name
Test status
Simulation time 263261952 ps
CPU time 14.8 seconds
Started Jan 10 12:28:49 PM PST 24
Finished Jan 10 12:29:20 PM PST 24
Peak memory 248536 kb
Host smart-cade25bf-cc4e-4810-940b-11a39b2eec46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19794
99031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1979499031
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3968631533
Short name T517
Test name
Test status
Simulation time 560387524 ps
CPU time 11.62 seconds
Started Jan 10 12:28:59 PM PST 24
Finished Jan 10 12:29:29 PM PST 24
Peak memory 248828 kb
Host smart-eb31822a-7e48-48e3-8d9a-9cbdd8b4c91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39686
31533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3968631533
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2787857503
Short name T124
Test name
Test status
Simulation time 296931176 ps
CPU time 27.95 seconds
Started Jan 10 12:28:28 PM PST 24
Finished Jan 10 12:29:06 PM PST 24
Peak memory 246792 kb
Host smart-baf35860-3ae8-4cd1-a0d8-00984bd31de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27878
57503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2787857503
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1573648232
Short name T208
Test name
Test status
Simulation time 136758841 ps
CPU time 4.61 seconds
Started Jan 10 12:31:38 PM PST 24
Finished Jan 10 12:32:33 PM PST 24
Peak memory 239932 kb
Host smart-608c20c0-d152-4ea6-b7d9-3609d3996489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15736
48232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1573648232
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1626539141
Short name T265
Test name
Test status
Simulation time 107011236543 ps
CPU time 2711.49 seconds
Started Jan 10 12:28:47 PM PST 24
Finished Jan 10 01:14:14 PM PST 24
Peak memory 289580 kb
Host smart-806cf39b-8a0a-4740-aaa2-db7f7db620ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626539141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1626539141
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.703655776
Short name T494
Test name
Test status
Simulation time 130170405399 ps
CPU time 9834.59 seconds
Started Jan 10 12:31:41 PM PST 24
Finished Jan 10 03:16:27 PM PST 24
Peak memory 393700 kb
Host smart-fca3ec88-5206-404b-9831-fd32478698e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703655776 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.703655776
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1374049847
Short name T23
Test name
Test status
Simulation time 22449519 ps
CPU time 2.33 seconds
Started Jan 10 12:28:27 PM PST 24
Finished Jan 10 12:28:40 PM PST 24
Peak memory 248740 kb
Host smart-55a7f3d5-e7db-44ce-b0e3-1fd70d9d2ca8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1374049847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1374049847
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3893690239
Short name T355
Test name
Test status
Simulation time 19093210995 ps
CPU time 1245.28 seconds
Started Jan 10 12:28:26 PM PST 24
Finished Jan 10 12:49:22 PM PST 24
Peak memory 272780 kb
Host smart-4b350e2f-2289-4e1e-897e-9f6bf5f00721
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893690239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3893690239
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2508006053
Short name T230
Test name
Test status
Simulation time 2114096219 ps
CPU time 9.85 seconds
Started Jan 10 12:28:27 PM PST 24
Finished Jan 10 12:28:47 PM PST 24
Peak memory 240440 kb
Host smart-5f428636-9a7a-4ff5-81c1-adab62e0402c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2508006053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2508006053
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.655060579
Short name T732
Test name
Test status
Simulation time 4717210770 ps
CPU time 67.98 seconds
Started Jan 10 12:28:41 PM PST 24
Finished Jan 10 12:30:01 PM PST 24
Peak memory 256424 kb
Host smart-aa85e7e2-a560-464d-add2-18f934c72a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65506
0579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.655060579
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1154331319
Short name T642
Test name
Test status
Simulation time 570205999 ps
CPU time 29.52 seconds
Started Jan 10 12:28:33 PM PST 24
Finished Jan 10 12:29:15 PM PST 24
Peak memory 255108 kb
Host smart-4dc2fc69-ab10-4fd5-9a11-66149443030b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11543
31319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1154331319
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.289775105
Short name T679
Test name
Test status
Simulation time 26914577814 ps
CPU time 1552.73 seconds
Started Jan 10 12:32:11 PM PST 24
Finished Jan 10 12:58:47 PM PST 24
Peak memory 272096 kb
Host smart-469f3128-5772-4d5c-a546-5b605c8ac79f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289775105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.289775105
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1418498478
Short name T724
Test name
Test status
Simulation time 116296552819 ps
CPU time 2055.65 seconds
Started Jan 10 12:28:35 PM PST 24
Finished Jan 10 01:03:02 PM PST 24
Peak memory 284188 kb
Host smart-2ef1b8a3-632c-4e90-b86e-03fb24af23f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418498478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1418498478
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3967256399
Short name T306
Test name
Test status
Simulation time 19105118086 ps
CPU time 170.94 seconds
Started Jan 10 12:28:32 PM PST 24
Finished Jan 10 12:31:34 PM PST 24
Peak memory 247472 kb
Host smart-8e1f25fa-6e3b-464c-b626-6da964d74ab3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967256399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3967256399
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.313318733
Short name T436
Test name
Test status
Simulation time 544212151 ps
CPU time 5.95 seconds
Started Jan 10 12:31:32 PM PST 24
Finished Jan 10 12:32:28 PM PST 24
Peak memory 248212 kb
Host smart-dd662063-607b-4e69-b800-f27e27fe3e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31331
8733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.313318733
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2218301498
Short name T565
Test name
Test status
Simulation time 1318298709 ps
CPU time 25.85 seconds
Started Jan 10 12:28:49 PM PST 24
Finished Jan 10 12:29:31 PM PST 24
Peak memory 248160 kb
Host smart-8a91310f-deeb-4da0-b204-1db27d62729b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22183
01498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2218301498
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.4129749451
Short name T688
Test name
Test status
Simulation time 890572348 ps
CPU time 49.24 seconds
Started Jan 10 12:28:54 PM PST 24
Finished Jan 10 12:30:02 PM PST 24
Peak memory 256740 kb
Host smart-d4961882-56f3-4680-8435-5925693f11de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41297
49451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.4129749451
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3352625706
Short name T500
Test name
Test status
Simulation time 124349516 ps
CPU time 8.27 seconds
Started Jan 10 12:31:31 PM PST 24
Finished Jan 10 12:32:28 PM PST 24
Peak memory 248132 kb
Host smart-55c06e49-6c71-4bea-b1dc-7284589d1f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33526
25706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3352625706
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1683078753
Short name T196
Test name
Test status
Simulation time 450412446 ps
CPU time 3.74 seconds
Started Jan 10 12:29:06 PM PST 24
Finished Jan 10 12:29:30 PM PST 24
Peak memory 248844 kb
Host smart-f0098c33-e5ec-4c14-9901-3ac7eeb5f989
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1683078753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1683078753
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.344468075
Short name T272
Test name
Test status
Simulation time 10961917592 ps
CPU time 838.63 seconds
Started Jan 10 12:29:07 PM PST 24
Finished Jan 10 12:43:27 PM PST 24
Peak memory 268044 kb
Host smart-97fa689f-d150-4cd2-8159-e883f0d4bd61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344468075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.344468075
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3118293493
Short name T225
Test name
Test status
Simulation time 786831416 ps
CPU time 11.02 seconds
Started Jan 10 12:28:49 PM PST 24
Finished Jan 10 12:29:17 PM PST 24
Peak memory 240244 kb
Host smart-ef5644b6-9863-4e2e-831d-26fe6eede0bc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3118293493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3118293493
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.34296238
Short name T372
Test name
Test status
Simulation time 9819710143 ps
CPU time 91.06 seconds
Started Jan 10 12:28:47 PM PST 24
Finished Jan 10 12:30:32 PM PST 24
Peak memory 256252 kb
Host smart-4980165e-b66e-46c9-a373-277a1f009459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34296
238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.34296238
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2854139373
Short name T86
Test name
Test status
Simulation time 1097001978 ps
CPU time 42.68 seconds
Started Jan 10 12:28:33 PM PST 24
Finished Jan 10 12:29:28 PM PST 24
Peak memory 248272 kb
Host smart-7a05cffe-825c-474e-8b48-630ab78e37f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28541
39373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2854139373
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.17151070
Short name T634
Test name
Test status
Simulation time 32407182556 ps
CPU time 1829.39 seconds
Started Jan 10 12:28:44 PM PST 24
Finished Jan 10 12:59:28 PM PST 24
Peak memory 273028 kb
Host smart-aaf62752-150a-4e74-9b9a-d518cda71e0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17151070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.17151070
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.625483097
Short name T312
Test name
Test status
Simulation time 14450367135 ps
CPU time 435.45 seconds
Started Jan 10 12:28:39 PM PST 24
Finished Jan 10 12:36:07 PM PST 24
Peak memory 247560 kb
Host smart-bc71d54a-a6b4-4163-9b20-53eb4221cdcb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625483097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.625483097
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1923397431
Short name T687
Test name
Test status
Simulation time 1082952481 ps
CPU time 48.3 seconds
Started Jan 10 12:28:25 PM PST 24
Finished Jan 10 12:29:25 PM PST 24
Peak memory 248520 kb
Host smart-ab8cc02f-af0b-4a35-8408-402ef12d2fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19233
97431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1923397431
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3338137645
Short name T214
Test name
Test status
Simulation time 1302044581 ps
CPU time 19.34 seconds
Started Jan 10 12:31:39 PM PST 24
Finished Jan 10 12:32:51 PM PST 24
Peak memory 247632 kb
Host smart-8ca8a766-876c-44a2-910f-373ef407f2aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33381
37645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3338137645
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1560143446
Short name T396
Test name
Test status
Simulation time 513486260 ps
CPU time 7.42 seconds
Started Jan 10 12:28:39 PM PST 24
Finished Jan 10 12:28:59 PM PST 24
Peak memory 253944 kb
Host smart-cd0cb0ad-dd90-46a6-b889-02fe13d686ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15601
43446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1560143446
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.102114169
Short name T414
Test name
Test status
Simulation time 649403506 ps
CPU time 17.31 seconds
Started Jan 10 12:28:43 PM PST 24
Finished Jan 10 12:29:14 PM PST 24
Peak memory 248808 kb
Host smart-af55a15d-1bdf-48cc-b524-b14821b62523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10211
4169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.102114169
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1027341451
Short name T295
Test name
Test status
Simulation time 128943489942 ps
CPU time 1697.12 seconds
Started Jan 10 12:29:11 PM PST 24
Finished Jan 10 12:57:50 PM PST 24
Peak memory 281716 kb
Host smart-07ea7704-9b9a-4b9b-b5d5-af941cd3f78f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027341451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1027341451
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1050061042
Short name T201
Test name
Test status
Simulation time 54752944 ps
CPU time 4.29 seconds
Started Jan 10 12:28:43 PM PST 24
Finished Jan 10 12:29:01 PM PST 24
Peak memory 248728 kb
Host smart-2dd0d8c5-4251-445a-a8f2-f7063e17f212
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1050061042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1050061042
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.846807843
Short name T418
Test name
Test status
Simulation time 8460502751 ps
CPU time 789.58 seconds
Started Jan 10 12:29:05 PM PST 24
Finished Jan 10 12:42:35 PM PST 24
Peak memory 272788 kb
Host smart-f9b4fbb3-0822-4611-a77b-e6fc8fe2c731
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846807843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.846807843
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1213681429
Short name T438
Test name
Test status
Simulation time 446652049 ps
CPU time 15.19 seconds
Started Jan 10 12:28:48 PM PST 24
Finished Jan 10 12:29:19 PM PST 24
Peak memory 240308 kb
Host smart-696dd99d-3cb4-4c95-9597-33e32371d402
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1213681429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1213681429
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1835480317
Short name T235
Test name
Test status
Simulation time 1076478053 ps
CPU time 82.87 seconds
Started Jan 10 12:29:13 PM PST 24
Finished Jan 10 12:30:59 PM PST 24
Peak memory 256432 kb
Host smart-81022480-00cb-48b5-86fb-dc0c9e7a7c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18354
80317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1835480317
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1677811577
Short name T460
Test name
Test status
Simulation time 744842790 ps
CPU time 41.42 seconds
Started Jan 10 12:28:34 PM PST 24
Finished Jan 10 12:29:28 PM PST 24
Peak memory 254352 kb
Host smart-149a2e7c-e19b-4c3a-a93d-a014d0a67762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16778
11577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1677811577
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1961752553
Short name T350
Test name
Test status
Simulation time 52897773436 ps
CPU time 946.58 seconds
Started Jan 10 12:29:00 PM PST 24
Finished Jan 10 12:45:06 PM PST 24
Peak memory 272572 kb
Host smart-b6fcae21-5c2e-4978-8548-ae6a294441f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961752553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1961752553
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2858361678
Short name T505
Test name
Test status
Simulation time 207890903472 ps
CPU time 2841.51 seconds
Started Jan 10 12:31:12 PM PST 24
Finished Jan 10 01:19:19 PM PST 24
Peak memory 289176 kb
Host smart-d283798f-bceb-4e16-b2d3-c21e791f051d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858361678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2858361678
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.555293171
Short name T539
Test name
Test status
Simulation time 4455643672 ps
CPU time 91.01 seconds
Started Jan 10 12:28:38 PM PST 24
Finished Jan 10 12:30:22 PM PST 24
Peak memory 247184 kb
Host smart-4da732c5-7f3a-4e72-94d8-1273624b8bde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555293171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.555293171
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3964001717
Short name T601
Test name
Test status
Simulation time 1532616276 ps
CPU time 24.52 seconds
Started Jan 10 12:28:50 PM PST 24
Finished Jan 10 12:29:31 PM PST 24
Peak memory 248512 kb
Host smart-2504ff04-9816-4df6-ae5e-fe72088d4bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39640
01717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3964001717
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1443526037
Short name T662
Test name
Test status
Simulation time 4183526201 ps
CPU time 23.94 seconds
Started Jan 10 12:29:08 PM PST 24
Finished Jan 10 12:29:53 PM PST 24
Peak memory 255292 kb
Host smart-ff5c3fc8-4fae-4e54-ad4e-11882ed5060a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14435
26037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1443526037
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.639310998
Short name T257
Test name
Test status
Simulation time 759960650 ps
CPU time 21.36 seconds
Started Jan 10 12:28:42 PM PST 24
Finished Jan 10 12:29:17 PM PST 24
Peak memory 246940 kb
Host smart-873d2bfc-adc9-4e92-81f2-b9f38539b2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63931
0998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.639310998
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2521415039
Short name T676
Test name
Test status
Simulation time 156194222 ps
CPU time 5.99 seconds
Started Jan 10 12:28:45 PM PST 24
Finished Jan 10 12:29:05 PM PST 24
Peak memory 248428 kb
Host smart-797f8714-1329-486c-a799-571a7bd4f9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25214
15039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2521415039
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2959118033
Short name T121
Test name
Test status
Simulation time 40410266240 ps
CPU time 2258.08 seconds
Started Jan 10 12:28:57 PM PST 24
Finished Jan 10 01:06:54 PM PST 24
Peak memory 289628 kb
Host smart-d4231cbc-e881-4763-89f2-0f8422dc8310
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959118033 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2959118033
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1685507419
Short name T194
Test name
Test status
Simulation time 228133799 ps
CPU time 2.77 seconds
Started Jan 10 12:29:07 PM PST 24
Finished Jan 10 12:29:31 PM PST 24
Peak memory 248796 kb
Host smart-9d5569e8-ce20-4ba7-aa7c-a65b64828db0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1685507419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1685507419
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.245653641
Short name T4
Test name
Test status
Simulation time 9556715060 ps
CPU time 725.08 seconds
Started Jan 10 12:30:40 PM PST 24
Finished Jan 10 12:43:28 PM PST 24
Peak memory 272116 kb
Host smart-52d460f9-fab7-4b40-9a03-c724fe1f8ecc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245653641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.245653641
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.888037695
Short name T387
Test name
Test status
Simulation time 219800958 ps
CPU time 11.81 seconds
Started Jan 10 12:28:38 PM PST 24
Finished Jan 10 12:29:03 PM PST 24
Peak memory 240304 kb
Host smart-d14db30a-4298-4a15-ba7f-ecfe0127ecba
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=888037695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.888037695
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1873271410
Short name T626
Test name
Test status
Simulation time 3799352831 ps
CPU time 108.89 seconds
Started Jan 10 12:28:49 PM PST 24
Finished Jan 10 12:30:54 PM PST 24
Peak memory 248664 kb
Host smart-71803c68-b5d9-40a5-88e4-fe99e8308c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18732
71410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1873271410
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2057529161
Short name T25
Test name
Test status
Simulation time 673844595 ps
CPU time 13.49 seconds
Started Jan 10 12:28:55 PM PST 24
Finished Jan 10 12:29:27 PM PST 24
Peak memory 252684 kb
Host smart-ec93f0ac-e202-4001-8edf-a42e2bf29a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20575
29161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2057529161
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3096833439
Short name T347
Test name
Test status
Simulation time 11701723599 ps
CPU time 856.41 seconds
Started Jan 10 12:29:05 PM PST 24
Finished Jan 10 12:43:42 PM PST 24
Peak memory 289016 kb
Host smart-6e5bef7a-077a-440b-92b6-6ad295cbead7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096833439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3096833439
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.19447371
Short name T506
Test name
Test status
Simulation time 63618365290 ps
CPU time 1775.09 seconds
Started Jan 10 12:28:39 PM PST 24
Finished Jan 10 12:58:27 PM PST 24
Peak memory 266172 kb
Host smart-56d85e17-060f-4640-8b0a-4681078aa168
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19447371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.19447371
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3465245629
Short name T334
Test name
Test status
Simulation time 70664370288 ps
CPU time 672.98 seconds
Started Jan 10 12:28:57 PM PST 24
Finished Jan 10 12:40:28 PM PST 24
Peak memory 247192 kb
Host smart-fac794c4-1b7a-49da-ab3c-db44ab8cb3ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465245629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3465245629
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3637400160
Short name T657
Test name
Test status
Simulation time 751491105 ps
CPU time 38.83 seconds
Started Jan 10 12:28:48 PM PST 24
Finished Jan 10 12:29:42 PM PST 24
Peak memory 248624 kb
Host smart-c91634b4-b782-458f-9a67-2056378f0db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36374
00160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3637400160
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3857532637
Short name T453
Test name
Test status
Simulation time 241092365 ps
CPU time 4.59 seconds
Started Jan 10 12:28:52 PM PST 24
Finished Jan 10 12:29:14 PM PST 24
Peak memory 238948 kb
Host smart-6be9da7b-1b5d-4546-a7db-01eb1054a67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38575
32637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3857532637
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.478591848
Short name T239
Test name
Test status
Simulation time 1978559488 ps
CPU time 34.19 seconds
Started Jan 10 12:28:53 PM PST 24
Finished Jan 10 12:29:46 PM PST 24
Peak memory 255560 kb
Host smart-e56f3764-a596-40b3-a46d-0e5de1fabe20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47859
1848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.478591848
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2256780825
Short name T533
Test name
Test status
Simulation time 295816326 ps
CPU time 21.35 seconds
Started Jan 10 12:28:57 PM PST 24
Finished Jan 10 12:29:37 PM PST 24
Peak memory 248660 kb
Host smart-5c1d4a75-b954-420d-9777-8706312b7a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22567
80825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2256780825
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3727429946
Short name T277
Test name
Test status
Simulation time 5205014764 ps
CPU time 149.07 seconds
Started Jan 10 12:28:54 PM PST 24
Finished Jan 10 12:31:42 PM PST 24
Peak memory 256596 kb
Host smart-00b15b14-815b-4430-a1b3-4554cc339752
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727429946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3727429946
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1987415987
Short name T260
Test name
Test status
Simulation time 178129665469 ps
CPU time 3190.91 seconds
Started Jan 10 12:28:43 PM PST 24
Finished Jan 10 01:22:08 PM PST 24
Peak memory 288564 kb
Host smart-94a605d4-add6-40d5-95ab-9333801a5979
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987415987 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1987415987
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2183549292
Short name T193
Test name
Test status
Simulation time 97958818 ps
CPU time 4.15 seconds
Started Jan 10 12:31:10 PM PST 24
Finished Jan 10 12:32:00 PM PST 24
Peak memory 248248 kb
Host smart-d97a2a46-9848-4a66-ad24-e37e899b79d1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2183549292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2183549292
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3590065949
Short name T598
Test name
Test status
Simulation time 35555327986 ps
CPU time 2139.1 seconds
Started Jan 10 12:32:08 PM PST 24
Finished Jan 10 01:08:32 PM PST 24
Peak memory 289064 kb
Host smart-7ace6d3a-1762-4223-8b14-f055755c6994
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590065949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3590065949
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2240160928
Short name T654
Test name
Test status
Simulation time 15450714599 ps
CPU time 45.39 seconds
Started Jan 10 12:32:09 PM PST 24
Finished Jan 10 12:33:38 PM PST 24
Peak memory 248188 kb
Host smart-89e10f24-577f-404e-8bf9-f051ec071ade
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2240160928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2240160928
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2384929465
Short name T49
Test name
Test status
Simulation time 3429645855 ps
CPU time 186.93 seconds
Started Jan 10 12:32:08 PM PST 24
Finished Jan 10 12:35:59 PM PST 24
Peak memory 250228 kb
Host smart-c60c8ba6-28f6-40a9-bb86-d75030079cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23849
29465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2384929465
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3575780106
Short name T382
Test name
Test status
Simulation time 60255282 ps
CPU time 2.74 seconds
Started Jan 10 12:32:08 PM PST 24
Finished Jan 10 12:32:55 PM PST 24
Peak memory 238968 kb
Host smart-fb39ef21-6775-4cd1-bfaa-ddbcfdb0f844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35757
80106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3575780106
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2007921788
Short name T268
Test name
Test status
Simulation time 40859070957 ps
CPU time 1006.7 seconds
Started Jan 10 12:32:17 PM PST 24
Finished Jan 10 12:49:44 PM PST 24
Peak memory 280996 kb
Host smart-bd392fa2-23f1-496d-9745-70a5b45a8342
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007921788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2007921788
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1601532228
Short name T292
Test name
Test status
Simulation time 227501158086 ps
CPU time 1087.81 seconds
Started Jan 10 12:32:11 PM PST 24
Finished Jan 10 12:51:02 PM PST 24
Peak memory 271924 kb
Host smart-c219b673-9220-47f4-bd88-338dd04274fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601532228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1601532228
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2479805188
Short name T282
Test name
Test status
Simulation time 954247257 ps
CPU time 52.02 seconds
Started Jan 10 12:32:14 PM PST 24
Finished Jan 10 12:33:48 PM PST 24
Peak memory 248120 kb
Host smart-220a0ddc-9fd0-4177-9253-881cad3ab83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24798
05188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2479805188
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.783428289
Short name T602
Test name
Test status
Simulation time 2775758196 ps
CPU time 34.79 seconds
Started Jan 10 12:31:47 PM PST 24
Finished Jan 10 12:33:10 PM PST 24
Peak memory 246316 kb
Host smart-e3dacec5-9d35-4003-8a84-83a1725ed8e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78342
8289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.783428289
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3096277177
Short name T516
Test name
Test status
Simulation time 1025350484 ps
CPU time 22.96 seconds
Started Jan 10 12:32:10 PM PST 24
Finished Jan 10 12:33:17 PM PST 24
Peak memory 247728 kb
Host smart-256cf52a-f27a-4b06-86a4-6b2e42f306f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30962
77177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3096277177
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1116466762
Short name T726
Test name
Test status
Simulation time 344183827 ps
CPU time 29.3 seconds
Started Jan 10 12:31:46 PM PST 24
Finished Jan 10 12:33:03 PM PST 24
Peak memory 246328 kb
Host smart-f32c28ff-c8af-4cc3-8a9b-5de39eed54e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11164
66762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1116466762
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2387234690
Short name T215
Test name
Test status
Simulation time 6658266984 ps
CPU time 123.96 seconds
Started Jan 10 12:31:10 PM PST 24
Finished Jan 10 12:34:00 PM PST 24
Peak memory 256248 kb
Host smart-f9de1c76-f19e-4bab-aa1a-4fec55a77bef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387234690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2387234690
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.179624037
Short name T70
Test name
Test status
Simulation time 36542816190 ps
CPU time 1859.09 seconds
Started Jan 10 12:31:09 PM PST 24
Finished Jan 10 01:02:55 PM PST 24
Peak memory 303372 kb
Host smart-14680a10-1e05-4e9b-9707-1ba82f78921d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179624037 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.179624037
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3408436760
Short name T614
Test name
Test status
Simulation time 1533030508 ps
CPU time 96.63 seconds
Started Jan 10 12:28:43 PM PST 24
Finished Jan 10 12:30:34 PM PST 24
Peak memory 248092 kb
Host smart-196946d8-871e-4fb5-88b5-561e81b5a005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34084
36760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3408436760
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.516596680
Short name T548
Test name
Test status
Simulation time 594527928 ps
CPU time 20.12 seconds
Started Jan 10 12:28:44 PM PST 24
Finished Jan 10 12:29:19 PM PST 24
Peak memory 248508 kb
Host smart-dfa5547e-694f-4e5e-814e-d6b3df403fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51659
6680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.516596680
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1156996721
Short name T301
Test name
Test status
Simulation time 39701886294 ps
CPU time 2080.74 seconds
Started Jan 10 12:31:56 PM PST 24
Finished Jan 10 01:07:23 PM PST 24
Peak memory 286384 kb
Host smart-e5d35b0a-4b10-492c-b2a6-005c2a2afcb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156996721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1156996721
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.307632911
Short name T406
Test name
Test status
Simulation time 20028412126 ps
CPU time 649.35 seconds
Started Jan 10 12:29:18 PM PST 24
Finished Jan 10 12:40:32 PM PST 24
Peak memory 272928 kb
Host smart-5ce5df9a-fb13-44ef-8a8d-43f8f1a3f7da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307632911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.307632911
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.875864166
Short name T313
Test name
Test status
Simulation time 13806850772 ps
CPU time 531.76 seconds
Started Jan 10 12:28:40 PM PST 24
Finished Jan 10 12:37:44 PM PST 24
Peak memory 247208 kb
Host smart-58e853a6-674a-43f1-a24c-2998049bb215
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875864166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.875864166
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2327786456
Short name T584
Test name
Test status
Simulation time 2324200099 ps
CPU time 21.7 seconds
Started Jan 10 12:28:46 PM PST 24
Finished Jan 10 12:29:22 PM PST 24
Peak memory 248676 kb
Host smart-b4f3cc40-4cf5-4ea4-848b-8b4b58de2dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23277
86456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2327786456
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3228417426
Short name T415
Test name
Test status
Simulation time 71427817 ps
CPU time 3.76 seconds
Started Jan 10 12:28:50 PM PST 24
Finished Jan 10 12:29:10 PM PST 24
Peak memory 238748 kb
Host smart-aa491821-ee5b-4610-b580-ace370ea5baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32284
17426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3228417426
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3598435992
Short name T79
Test name
Test status
Simulation time 800406717 ps
CPU time 45.57 seconds
Started Jan 10 12:28:44 PM PST 24
Finished Jan 10 12:29:44 PM PST 24
Peak memory 254796 kb
Host smart-59f16974-6463-4380-bc6b-2a3c1e0e97b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35984
35992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3598435992
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1097642199
Short name T560
Test name
Test status
Simulation time 2617712816 ps
CPU time 35.71 seconds
Started Jan 10 12:28:41 PM PST 24
Finished Jan 10 12:29:30 PM PST 24
Peak memory 248628 kb
Host smart-e0cd5449-c5dc-4365-8152-a6e06a54ed04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10976
42199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1097642199
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3699395783
Short name T287
Test name
Test status
Simulation time 128929191503 ps
CPU time 2145.08 seconds
Started Jan 10 12:29:13 PM PST 24
Finished Jan 10 01:05:20 PM PST 24
Peak memory 286460 kb
Host smart-7b9d3885-06a2-4139-bbde-1b8802dfe51e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699395783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3699395783
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.711809959
Short name T271
Test name
Test status
Simulation time 126419722013 ps
CPU time 3395.59 seconds
Started Jan 10 12:29:04 PM PST 24
Finished Jan 10 01:26:01 PM PST 24
Peak memory 337364 kb
Host smart-2c94a94f-74a1-4811-b841-9256ac47191f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711809959 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.711809959
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3552845565
Short name T422
Test name
Test status
Simulation time 9828720586 ps
CPU time 233.19 seconds
Started Jan 10 12:29:14 PM PST 24
Finished Jan 10 12:33:30 PM PST 24
Peak memory 256524 kb
Host smart-3fa91c21-82c2-4728-a517-ba4c8c65ade8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35528
45565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3552845565
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1894884926
Short name T718
Test name
Test status
Simulation time 126907497 ps
CPU time 8.31 seconds
Started Jan 10 12:31:56 PM PST 24
Finished Jan 10 12:32:51 PM PST 24
Peak memory 250960 kb
Host smart-abaea343-3d04-4c7a-8e9f-ec35d5f2a25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18948
84926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1894884926
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3947809252
Short name T683
Test name
Test status
Simulation time 19793065390 ps
CPU time 1120.16 seconds
Started Jan 10 12:29:14 PM PST 24
Finished Jan 10 12:48:17 PM PST 24
Peak memory 265116 kb
Host smart-682b2dea-a30a-4837-919a-1a58ab795404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947809252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3947809252
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1321609997
Short name T332
Test name
Test status
Simulation time 3477941419 ps
CPU time 95.79 seconds
Started Jan 10 12:28:53 PM PST 24
Finished Jan 10 12:30:48 PM PST 24
Peak memory 247448 kb
Host smart-9b6e65be-640b-4336-81a8-2b8c4379af61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321609997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1321609997
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1884761019
Short name T482
Test name
Test status
Simulation time 41541774 ps
CPU time 4.72 seconds
Started Jan 10 12:31:57 PM PST 24
Finished Jan 10 12:32:49 PM PST 24
Peak memory 251956 kb
Host smart-3535d5e8-9b4a-49bf-b637-2394ef19c07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18847
61019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1884761019
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.761025562
Short name T411
Test name
Test status
Simulation time 132053355 ps
CPU time 14.84 seconds
Started Jan 10 12:28:52 PM PST 24
Finished Jan 10 12:29:23 PM PST 24
Peak memory 254808 kb
Host smart-acf7bc2c-ae89-4bcc-8bc7-f0b8f108c4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76102
5562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.761025562
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.4078608415
Short name T675
Test name
Test status
Simulation time 3797296654 ps
CPU time 52.72 seconds
Started Jan 10 12:28:48 PM PST 24
Finished Jan 10 12:29:57 PM PST 24
Peak memory 256552 kb
Host smart-103eeac8-9276-48b9-8dc8-e0dc81acac7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40786
08415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.4078608415
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1440200283
Short name T448
Test name
Test status
Simulation time 659645208 ps
CPU time 37.58 seconds
Started Jan 10 12:29:03 PM PST 24
Finished Jan 10 12:30:01 PM PST 24
Peak memory 248616 kb
Host smart-be648b10-0902-4415-a663-9032b16f25e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14402
00283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1440200283
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2411949785
Short name T57
Test name
Test status
Simulation time 30445230304 ps
CPU time 420.92 seconds
Started Jan 10 12:29:07 PM PST 24
Finished Jan 10 12:36:29 PM PST 24
Peak memory 256828 kb
Host smart-85d36063-9e7e-4d9d-910b-aa874af6d136
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411949785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2411949785
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.4256927732
Short name T290
Test name
Test status
Simulation time 45824111314 ps
CPU time 1411.47 seconds
Started Jan 10 12:29:08 PM PST 24
Finished Jan 10 12:53:01 PM PST 24
Peak memory 272696 kb
Host smart-a0094e34-6b80-411a-a42b-7a1ed4de86ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256927732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.4256927732
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2877170758
Short name T456
Test name
Test status
Simulation time 1021994563 ps
CPU time 51.91 seconds
Started Jan 10 12:29:07 PM PST 24
Finished Jan 10 12:30:21 PM PST 24
Peak memory 256056 kb
Host smart-de28d61c-18fa-41c5-855a-267e5cd81900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28771
70758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2877170758
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1394883496
Short name T559
Test name
Test status
Simulation time 2309375754 ps
CPU time 34.17 seconds
Started Jan 10 12:29:10 PM PST 24
Finished Jan 10 12:30:06 PM PST 24
Peak memory 255344 kb
Host smart-d430df51-7fa0-45fc-a299-9c2b96927055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13948
83496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1394883496
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.4143885454
Short name T336
Test name
Test status
Simulation time 20015003178 ps
CPU time 661.91 seconds
Started Jan 10 12:31:57 PM PST 24
Finished Jan 10 12:43:46 PM PST 24
Peak memory 264584 kb
Host smart-aa03d0d9-5dfa-4b8a-903b-6c6206a2ad72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143885454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.4143885454
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1812075325
Short name T624
Test name
Test status
Simulation time 22936844143 ps
CPU time 936.09 seconds
Started Jan 10 12:28:56 PM PST 24
Finished Jan 10 12:44:50 PM PST 24
Peak memory 270784 kb
Host smart-e20359ca-378c-4b3f-be65-317239594506
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812075325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1812075325
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2000159663
Short name T218
Test name
Test status
Simulation time 7679359187 ps
CPU time 222.53 seconds
Started Jan 10 12:28:55 PM PST 24
Finished Jan 10 12:32:56 PM PST 24
Peak memory 247432 kb
Host smart-ad8801eb-7e4e-4df1-8fba-555fe6a0b1dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000159663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2000159663
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3444830451
Short name T427
Test name
Test status
Simulation time 917795771 ps
CPU time 55.22 seconds
Started Jan 10 12:28:59 PM PST 24
Finished Jan 10 12:30:13 PM PST 24
Peak memory 248664 kb
Host smart-5dbe096d-b20e-4524-b86c-3a5f4ea2acde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34448
30451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3444830451
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3126499330
Short name T97
Test name
Test status
Simulation time 2387716547 ps
CPU time 31.5 seconds
Started Jan 10 12:29:05 PM PST 24
Finished Jan 10 12:29:57 PM PST 24
Peak memory 254884 kb
Host smart-d3a891d6-6989-4dfb-b731-1c0745a54fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31264
99330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3126499330
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3423083453
Short name T580
Test name
Test status
Simulation time 2136231461 ps
CPU time 31.5 seconds
Started Jan 10 12:28:47 PM PST 24
Finished Jan 10 12:29:33 PM PST 24
Peak memory 255284 kb
Host smart-a7cb0c47-e812-43ff-9c6a-ed9137133f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34230
83453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3423083453
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2104555589
Short name T668
Test name
Test status
Simulation time 692003179 ps
CPU time 21.25 seconds
Started Jan 10 12:31:56 PM PST 24
Finished Jan 10 12:33:04 PM PST 24
Peak memory 247864 kb
Host smart-fb8048ec-4a7e-4df1-ac41-48387202cb3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21045
55589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2104555589
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.438350222
Short name T603
Test name
Test status
Simulation time 18062819748 ps
CPU time 1431.35 seconds
Started Jan 10 12:28:52 PM PST 24
Finished Jan 10 12:53:01 PM PST 24
Peak memory 289876 kb
Host smart-37b77229-4fd3-406f-9e72-eeb57cea0af1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438350222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.438350222
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.1138858772
Short name T119
Test name
Test status
Simulation time 27566407809 ps
CPU time 2884.79 seconds
Started Jan 10 12:29:09 PM PST 24
Finished Jan 10 01:17:35 PM PST 24
Peak memory 321080 kb
Host smart-61812405-4075-4575-9ebb-cb50479860b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138858772 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.1138858772
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3706021628
Short name T455
Test name
Test status
Simulation time 3494459411 ps
CPU time 52.45 seconds
Started Jan 10 12:29:10 PM PST 24
Finished Jan 10 12:30:24 PM PST 24
Peak memory 247960 kb
Host smart-6245190b-fdcd-447e-b052-3ec56614fa4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37060
21628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3706021628
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4053494907
Short name T113
Test name
Test status
Simulation time 1577360667 ps
CPU time 22.87 seconds
Started Jan 10 12:29:04 PM PST 24
Finished Jan 10 12:29:47 PM PST 24
Peak memory 248172 kb
Host smart-c3d3b3a4-aa0e-4fd9-b810-1592fe464510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40534
94907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4053494907
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2258333929
Short name T321
Test name
Test status
Simulation time 161669392888 ps
CPU time 2146.97 seconds
Started Jan 10 12:29:21 PM PST 24
Finished Jan 10 01:05:34 PM PST 24
Peak memory 284360 kb
Host smart-9ed1e8d9-ac0a-4e47-b0e7-f6c6167f6110
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258333929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2258333929
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2469041586
Short name T462
Test name
Test status
Simulation time 181206416416 ps
CPU time 2734.42 seconds
Started Jan 10 12:29:08 PM PST 24
Finished Jan 10 01:15:04 PM PST 24
Peak memory 286936 kb
Host smart-618947e1-66e2-4749-bdc2-1e1428d6671b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469041586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2469041586
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2405607329
Short name T723
Test name
Test status
Simulation time 52974793197 ps
CPU time 504.52 seconds
Started Jan 10 12:29:11 PM PST 24
Finished Jan 10 12:37:58 PM PST 24
Peak memory 247424 kb
Host smart-7c783286-8261-46f3-97d9-2d49181a277b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405607329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2405607329
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3835744598
Short name T217
Test name
Test status
Simulation time 7068003611 ps
CPU time 42.52 seconds
Started Jan 10 12:29:14 PM PST 24
Finished Jan 10 12:30:19 PM PST 24
Peak memory 248712 kb
Host smart-cab5116e-dcf5-4ebc-8d3f-192e028dc075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38357
44598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3835744598
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2501687612
Short name T118
Test name
Test status
Simulation time 929562034 ps
CPU time 26.21 seconds
Started Jan 10 12:28:53 PM PST 24
Finished Jan 10 12:29:37 PM PST 24
Peak memory 255600 kb
Host smart-3102f9c6-4ebf-401c-9df6-0340795b88f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25016
87612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2501687612
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2824371626
Short name T210
Test name
Test status
Simulation time 257114350 ps
CPU time 6.82 seconds
Started Jan 10 12:29:03 PM PST 24
Finished Jan 10 12:29:29 PM PST 24
Peak memory 246936 kb
Host smart-a5c4c171-bb28-4893-8450-2a3b8f3183b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28243
71626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2824371626
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2373435153
Short name T532
Test name
Test status
Simulation time 1495692328 ps
CPU time 20.11 seconds
Started Jan 10 12:31:56 PM PST 24
Finished Jan 10 12:33:03 PM PST 24
Peak memory 248040 kb
Host smart-84437187-d211-4297-89f3-907748b6f738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23734
35153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2373435153
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3863375437
Short name T713
Test name
Test status
Simulation time 23450875958 ps
CPU time 2014.02 seconds
Started Jan 10 12:29:09 PM PST 24
Finished Jan 10 01:03:06 PM PST 24
Peak memory 305736 kb
Host smart-aa092bcb-b0a2-46f8-901b-d53637258c61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863375437 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3863375437
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2577291705
Short name T563
Test name
Test status
Simulation time 27222772897 ps
CPU time 1366.85 seconds
Started Jan 10 12:29:09 PM PST 24
Finished Jan 10 12:52:17 PM PST 24
Peak memory 265000 kb
Host smart-e3f62468-4507-4386-b866-92660b1d400e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577291705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2577291705
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.741635981
Short name T618
Test name
Test status
Simulation time 8782475557 ps
CPU time 234.3 seconds
Started Jan 10 12:29:14 PM PST 24
Finished Jan 10 12:33:31 PM PST 24
Peak memory 256812 kb
Host smart-3de6e117-6af4-4764-b0d6-0e952c9dc39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74163
5981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.741635981
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3827989564
Short name T552
Test name
Test status
Simulation time 607441436 ps
CPU time 21.39 seconds
Started Jan 10 12:29:11 PM PST 24
Finished Jan 10 12:29:55 PM PST 24
Peak memory 253872 kb
Host smart-bde70888-9092-430d-ab01-426bedabf1cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38279
89564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3827989564
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.233552035
Short name T631
Test name
Test status
Simulation time 28470742741 ps
CPU time 1294.65 seconds
Started Jan 10 12:29:03 PM PST 24
Finished Jan 10 12:50:57 PM PST 24
Peak memory 283788 kb
Host smart-7c095a82-9283-4e5d-a6ee-6efc42d89c87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233552035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.233552035
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.384778900
Short name T480
Test name
Test status
Simulation time 68779960747 ps
CPU time 1184.94 seconds
Started Jan 10 12:29:11 PM PST 24
Finished Jan 10 12:49:18 PM PST 24
Peak memory 283524 kb
Host smart-07b8e5a1-cf2f-4af2-9d4c-59470f17e3ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384778900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.384778900
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1477340481
Short name T326
Test name
Test status
Simulation time 46729327022 ps
CPU time 423.01 seconds
Started Jan 10 12:29:09 PM PST 24
Finished Jan 10 12:36:35 PM PST 24
Peak memory 247176 kb
Host smart-83d4aeae-a815-4384-b2d6-7b1b18813c94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477340481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1477340481
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.593363190
Short name T521
Test name
Test status
Simulation time 471360626 ps
CPU time 24.6 seconds
Started Jan 10 12:28:58 PM PST 24
Finished Jan 10 12:29:42 PM PST 24
Peak memory 248548 kb
Host smart-2aa40267-cd0d-4f3c-837a-8f34d2797aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59336
3190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.593363190
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.717506156
Short name T697
Test name
Test status
Simulation time 773674953 ps
CPU time 32.48 seconds
Started Jan 10 12:29:30 PM PST 24
Finished Jan 10 12:30:29 PM PST 24
Peak memory 255736 kb
Host smart-790a634d-db21-43c1-8441-a32a1c52b62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71750
6156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.717506156
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.4018025402
Short name T285
Test name
Test status
Simulation time 475099595 ps
CPU time 10.15 seconds
Started Jan 10 12:29:11 PM PST 24
Finished Jan 10 12:29:43 PM PST 24
Peak memory 253248 kb
Host smart-a7877d91-7052-4688-bfc6-85fe945d7dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40180
25402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.4018025402
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.899156151
Short name T712
Test name
Test status
Simulation time 2402881527 ps
CPU time 25.99 seconds
Started Jan 10 12:29:15 PM PST 24
Finished Jan 10 12:30:05 PM PST 24
Peak memory 248716 kb
Host smart-7c949c74-a426-400e-9db7-1f6caa59812b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89915
6151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.899156151
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1152665891
Short name T255
Test name
Test status
Simulation time 8806894507 ps
CPU time 360.54 seconds
Started Jan 10 12:29:07 PM PST 24
Finished Jan 10 12:35:29 PM PST 24
Peak memory 264900 kb
Host smart-2c0a72ca-8456-4e60-8966-25113faad430
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152665891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1152665891
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3267921379
Short name T424
Test name
Test status
Simulation time 65950298311 ps
CPU time 2644.98 seconds
Started Jan 10 12:29:10 PM PST 24
Finished Jan 10 01:13:37 PM PST 24
Peak memory 286260 kb
Host smart-ac4c02af-863c-403e-b00c-8e38a7821313
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267921379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3267921379
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.223005252
Short name T395
Test name
Test status
Simulation time 1767153329 ps
CPU time 134.91 seconds
Started Jan 10 12:29:08 PM PST 24
Finished Jan 10 12:31:44 PM PST 24
Peak memory 256068 kb
Host smart-514b037a-bdc9-445f-849f-256adbf3157f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22300
5252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.223005252
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2312398639
Short name T426
Test name
Test status
Simulation time 2195337796 ps
CPU time 31.23 seconds
Started Jan 10 12:29:08 PM PST 24
Finished Jan 10 12:30:01 PM PST 24
Peak memory 248104 kb
Host smart-b2d64d75-fa9a-4bed-adb9-4e8868d9f42d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23123
98639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2312398639
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3867504044
Short name T523
Test name
Test status
Simulation time 85322801309 ps
CPU time 2628.52 seconds
Started Jan 10 12:29:09 PM PST 24
Finished Jan 10 01:13:20 PM PST 24
Peak memory 288888 kb
Host smart-19b80f49-dffa-4003-af54-23b2ea54ef8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867504044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3867504044
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3789560757
Short name T314
Test name
Test status
Simulation time 28347040242 ps
CPU time 259.1 seconds
Started Jan 10 12:29:32 PM PST 24
Finished Jan 10 12:34:17 PM PST 24
Peak memory 247432 kb
Host smart-f5c1a9f5-e5be-4968-8d56-0398248a97f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789560757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3789560757
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.318963020
Short name T442
Test name
Test status
Simulation time 1198725154 ps
CPU time 64.12 seconds
Started Jan 10 12:29:06 PM PST 24
Finished Jan 10 12:30:32 PM PST 24
Peak memory 255320 kb
Host smart-782d9849-5641-4143-a6e9-69c3598655ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31896
3020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.318963020
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2451377527
Short name T519
Test name
Test status
Simulation time 2923898354 ps
CPU time 26.8 seconds
Started Jan 10 12:29:04 PM PST 24
Finished Jan 10 12:29:51 PM PST 24
Peak memory 255508 kb
Host smart-6b95c5a0-7525-47dd-a7e0-7d48f84e50f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24513
77527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2451377527
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3417758816
Short name T534
Test name
Test status
Simulation time 636057126 ps
CPU time 14.56 seconds
Started Jan 10 12:29:12 PM PST 24
Finished Jan 10 12:29:49 PM PST 24
Peak memory 254876 kb
Host smart-8b114ad4-48de-4a99-a738-14a786d55dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34177
58816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3417758816
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3424215462
Short name T373
Test name
Test status
Simulation time 560339680 ps
CPU time 30.81 seconds
Started Jan 10 12:29:59 PM PST 24
Finished Jan 10 12:31:10 PM PST 24
Peak memory 248576 kb
Host smart-a6127be6-c0e9-49fa-80e2-679e7077dc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34242
15462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3424215462
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2790696712
Short name T653
Test name
Test status
Simulation time 4405036700 ps
CPU time 79.04 seconds
Started Jan 10 12:29:29 PM PST 24
Finished Jan 10 12:31:14 PM PST 24
Peak memory 256744 kb
Host smart-2e6e1866-16ec-4269-b4bd-089b30451d1e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790696712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2790696712
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.4167641740
Short name T76
Test name
Test status
Simulation time 48703772693 ps
CPU time 1186.84 seconds
Started Jan 10 12:29:05 PM PST 24
Finished Jan 10 12:49:14 PM PST 24
Peak memory 283456 kb
Host smart-5d013bf1-ec0a-444b-9dc4-edd0d09fc653
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167641740 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.4167641740
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.60212033
Short name T610
Test name
Test status
Simulation time 70031364514 ps
CPU time 1101.2 seconds
Started Jan 10 12:29:10 PM PST 24
Finished Jan 10 12:47:54 PM PST 24
Peak memory 284296 kb
Host smart-b1501600-6ded-4db9-a7c6-281e11929cc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60212033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.60212033
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1166414646
Short name T619
Test name
Test status
Simulation time 6134652700 ps
CPU time 81.85 seconds
Started Jan 10 12:29:16 PM PST 24
Finished Jan 10 12:31:02 PM PST 24
Peak memory 256168 kb
Host smart-982e051c-331f-447b-9eb5-29ea789b837d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11664
14646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1166414646
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3571470636
Short name T47
Test name
Test status
Simulation time 9329119155 ps
CPU time 63.08 seconds
Started Jan 10 12:29:17 PM PST 24
Finished Jan 10 12:30:44 PM PST 24
Peak memory 256280 kb
Host smart-95484651-21a7-4328-aa67-4bb5e33fa7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35714
70636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3571470636
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.848794105
Short name T465
Test name
Test status
Simulation time 58733365642 ps
CPU time 1771.37 seconds
Started Jan 10 12:29:20 PM PST 24
Finished Jan 10 12:59:17 PM PST 24
Peak memory 273228 kb
Host smart-a5b616ed-4d48-4988-8aac-cb881c45c02e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848794105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.848794105
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.692995972
Short name T446
Test name
Test status
Simulation time 323418077 ps
CPU time 19.01 seconds
Started Jan 10 12:29:11 PM PST 24
Finished Jan 10 12:29:52 PM PST 24
Peak memory 255260 kb
Host smart-178dcd72-8b47-4a61-ba1a-325b72a4226f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69299
5972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.692995972
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.4248305608
Short name T374
Test name
Test status
Simulation time 121324236 ps
CPU time 14.28 seconds
Started Jan 10 12:29:08 PM PST 24
Finished Jan 10 12:29:44 PM PST 24
Peak memory 246828 kb
Host smart-ffb3e65f-922b-4b45-862a-4329d9f33651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42483
05608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.4248305608
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.749363943
Short name T222
Test name
Test status
Simulation time 401205215 ps
CPU time 21.61 seconds
Started Jan 10 12:29:16 PM PST 24
Finished Jan 10 12:30:01 PM PST 24
Peak memory 246820 kb
Host smart-5c7d9be2-74c7-459e-8c22-6bf354b8c223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74936
3943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.749363943
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.698044017
Short name T575
Test name
Test status
Simulation time 401002534 ps
CPU time 10.8 seconds
Started Jan 10 12:29:11 PM PST 24
Finished Jan 10 12:29:44 PM PST 24
Peak memory 248492 kb
Host smart-db95a40f-fc20-448d-8dd3-439e0ed4787a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69804
4017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.698044017
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3434356335
Short name T715
Test name
Test status
Simulation time 63332984226 ps
CPU time 2087.81 seconds
Started Jan 10 12:29:24 PM PST 24
Finished Jan 10 01:04:39 PM PST 24
Peak memory 288992 kb
Host smart-74878db1-3194-4c08-88bb-f9f4c0e121db
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434356335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3434356335
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2953098089
Short name T441
Test name
Test status
Simulation time 68389865446 ps
CPU time 6463.16 seconds
Started Jan 10 12:29:16 PM PST 24
Finished Jan 10 02:17:23 PM PST 24
Peak memory 354932 kb
Host smart-2e06df1f-7354-416a-80ec-3695ac094861
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953098089 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2953098089
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3748177741
Short name T85
Test name
Test status
Simulation time 16863726764 ps
CPU time 1226.47 seconds
Started Jan 10 12:29:13 PM PST 24
Finished Jan 10 12:50:03 PM PST 24
Peak memory 288420 kb
Host smart-562bb4da-23fa-45ad-b684-7615cbf10226
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748177741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3748177741
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2691363397
Short name T90
Test name
Test status
Simulation time 17461219592 ps
CPU time 229.79 seconds
Started Jan 10 12:29:16 PM PST 24
Finished Jan 10 12:33:29 PM PST 24
Peak memory 256820 kb
Host smart-830fb9dc-47e7-46b6-833e-0a884c9ca338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26913
63397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2691363397
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2575705443
Short name T474
Test name
Test status
Simulation time 313644489 ps
CPU time 23.69 seconds
Started Jan 10 12:29:12 PM PST 24
Finished Jan 10 12:30:03 PM PST 24
Peak memory 248548 kb
Host smart-5610c947-8217-42c2-8b6e-5ce990570fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25757
05443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2575705443
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.385855349
Short name T288
Test name
Test status
Simulation time 211057125440 ps
CPU time 1249.06 seconds
Started Jan 10 12:29:16 PM PST 24
Finished Jan 10 12:50:29 PM PST 24
Peak memory 272320 kb
Host smart-93c4471a-df8b-403b-b5ac-f27835add170
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385855349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.385855349
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3754577989
Short name T273
Test name
Test status
Simulation time 96506326470 ps
CPU time 1426.43 seconds
Started Jan 10 12:29:12 PM PST 24
Finished Jan 10 12:53:21 PM PST 24
Peak memory 272196 kb
Host smart-ebf851c8-e1c7-4f9e-bf8d-c01fe9b4dd32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754577989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3754577989
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.670009576
Short name T635
Test name
Test status
Simulation time 7456703394 ps
CPU time 79.47 seconds
Started Jan 10 12:29:25 PM PST 24
Finished Jan 10 12:31:11 PM PST 24
Peak memory 247572 kb
Host smart-e41fb454-4afb-4797-9836-c67247b535ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670009576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.670009576
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1236444045
Short name T51
Test name
Test status
Simulation time 468039999 ps
CPU time 25.44 seconds
Started Jan 10 12:29:42 PM PST 24
Finished Jan 10 12:30:41 PM PST 24
Peak memory 255364 kb
Host smart-d1f143aa-e7b5-44db-9a15-2d6584c7b2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12364
44045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1236444045
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.976852480
Short name T579
Test name
Test status
Simulation time 200368090 ps
CPU time 17.6 seconds
Started Jan 10 12:29:16 PM PST 24
Finished Jan 10 12:29:58 PM PST 24
Peak memory 254940 kb
Host smart-386a54d0-6dfb-41e5-8541-14111341724b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97685
2480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.976852480
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.4193144237
Short name T247
Test name
Test status
Simulation time 362609405 ps
CPU time 22.3 seconds
Started Jan 10 12:29:25 PM PST 24
Finished Jan 10 12:30:14 PM PST 24
Peak memory 246792 kb
Host smart-d0bc2eb8-cbac-46bc-b322-1db1637a2df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41931
44237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.4193144237
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.368850065
Short name T408
Test name
Test status
Simulation time 2026056622 ps
CPU time 31.24 seconds
Started Jan 10 12:29:20 PM PST 24
Finished Jan 10 12:30:17 PM PST 24
Peak memory 248584 kb
Host smart-411d0fcd-c75e-4472-ae68-30f837fc2807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36885
0065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.368850065
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1539564529
Short name T263
Test name
Test status
Simulation time 192885468905 ps
CPU time 3228.88 seconds
Started Jan 10 12:29:23 PM PST 24
Finished Jan 10 01:23:39 PM PST 24
Peak memory 299492 kb
Host smart-fc31ffac-eb17-4248-9f8f-1ed3415037bf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539564529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1539564529
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2905590630
Short name T541
Test name
Test status
Simulation time 143041344462 ps
CPU time 3381.57 seconds
Started Jan 10 12:29:13 PM PST 24
Finished Jan 10 01:25:57 PM PST 24
Peak memory 335660 kb
Host smart-e92d81a1-cd2a-4cfe-af1f-6df754a107aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905590630 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2905590630
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.236581481
Short name T710
Test name
Test status
Simulation time 5863197766 ps
CPU time 628.83 seconds
Started Jan 10 12:29:23 PM PST 24
Finished Jan 10 12:40:19 PM PST 24
Peak memory 272812 kb
Host smart-09bbfe84-96ac-4be8-8539-5510f0a8e916
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236581481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.236581481
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.164129624
Short name T475
Test name
Test status
Simulation time 13257486243 ps
CPU time 186.23 seconds
Started Jan 10 12:29:15 PM PST 24
Finished Jan 10 12:32:44 PM PST 24
Peak memory 255804 kb
Host smart-9beb4366-307f-457d-b731-7034c1f71cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16412
9624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.164129624
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.489977172
Short name T551
Test name
Test status
Simulation time 34510122 ps
CPU time 3.82 seconds
Started Jan 10 12:29:17 PM PST 24
Finished Jan 10 12:29:44 PM PST 24
Peak memory 238632 kb
Host smart-e2b71f14-d5fa-4868-aee7-6f8b73fddb6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48997
7172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.489977172
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2357277550
Short name T320
Test name
Test status
Simulation time 31558244766 ps
CPU time 1553.28 seconds
Started Jan 10 12:29:21 PM PST 24
Finished Jan 10 12:55:40 PM PST 24
Peak memory 272048 kb
Host smart-25145e8a-5be2-4e9f-9f5f-1fb63c5fef6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357277550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2357277550
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3988538358
Short name T605
Test name
Test status
Simulation time 53250844397 ps
CPU time 493.53 seconds
Started Jan 10 12:29:16 PM PST 24
Finished Jan 10 12:37:52 PM PST 24
Peak memory 264616 kb
Host smart-0cbbd51e-4a7e-4faa-9e18-4a7a67a75867
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988538358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3988538358
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1318041983
Short name T670
Test name
Test status
Simulation time 26223442120 ps
CPU time 269.45 seconds
Started Jan 10 12:29:37 PM PST 24
Finished Jan 10 12:34:36 PM PST 24
Peak memory 247448 kb
Host smart-3be3348c-e327-425f-89ab-120c51979c0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318041983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1318041983
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3154559792
Short name T503
Test name
Test status
Simulation time 2814307356 ps
CPU time 44.04 seconds
Started Jan 10 12:29:14 PM PST 24
Finished Jan 10 12:30:21 PM PST 24
Peak memory 256804 kb
Host smart-c8f348ff-1342-494a-b02b-c520b256ec77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31545
59792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3154559792
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3132785994
Short name T583
Test name
Test status
Simulation time 321185135 ps
CPU time 19.32 seconds
Started Jan 10 12:29:15 PM PST 24
Finished Jan 10 12:29:57 PM PST 24
Peak memory 248068 kb
Host smart-2913974c-07ea-4ca3-8d64-8c5f130ffe15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31327
85994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3132785994
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3978150756
Short name T276
Test name
Test status
Simulation time 841559324 ps
CPU time 23.3 seconds
Started Jan 10 12:29:58 PM PST 24
Finished Jan 10 12:31:03 PM PST 24
Peak memory 248432 kb
Host smart-11a6e012-270b-4447-9179-6442bed7f422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39781
50756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3978150756
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2647209622
Short name T700
Test name
Test status
Simulation time 77246809 ps
CPU time 7.15 seconds
Started Jan 10 12:29:47 PM PST 24
Finished Jan 10 12:30:28 PM PST 24
Peak memory 248452 kb
Host smart-a114742a-c408-49fa-8b51-8639063be55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26472
09622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2647209622
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3026887064
Short name T281
Test name
Test status
Simulation time 281944775846 ps
CPU time 2968.39 seconds
Started Jan 10 12:29:09 PM PST 24
Finished Jan 10 01:19:00 PM PST 24
Peak memory 303604 kb
Host smart-c9d09696-d282-4413-9f09-e9382eb6f495
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026887064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3026887064
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.287577227
Short name T466
Test name
Test status
Simulation time 290322663830 ps
CPU time 2920.79 seconds
Started Jan 10 12:29:12 PM PST 24
Finished Jan 10 01:18:15 PM PST 24
Peak memory 321484 kb
Host smart-dfd67688-af5c-4022-99eb-2a5bd26ce3cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287577227 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.287577227
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1202371714
Short name T439
Test name
Test status
Simulation time 10743994495 ps
CPU time 722.95 seconds
Started Jan 10 12:29:32 PM PST 24
Finished Jan 10 12:42:00 PM PST 24
Peak memory 273164 kb
Host smart-4c9e230a-70c1-425c-abc0-c5e1ea29f25d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202371714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1202371714
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.793735705
Short name T647
Test name
Test status
Simulation time 7839073473 ps
CPU time 124.49 seconds
Started Jan 10 12:29:20 PM PST 24
Finished Jan 10 12:31:49 PM PST 24
Peak memory 256168 kb
Host smart-d936e13a-5732-4141-8e37-3e3316d96491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79373
5705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.793735705
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.464445037
Short name T604
Test name
Test status
Simulation time 2002440930 ps
CPU time 28.28 seconds
Started Jan 10 12:29:16 PM PST 24
Finished Jan 10 12:30:09 PM PST 24
Peak memory 248528 kb
Host smart-d69f70b3-4b06-47a8-9c66-585a5cb1569d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46444
5037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.464445037
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2418810650
Short name T353
Test name
Test status
Simulation time 76931982762 ps
CPU time 1467.38 seconds
Started Jan 10 12:29:31 PM PST 24
Finished Jan 10 12:54:24 PM PST 24
Peak memory 289236 kb
Host smart-245f4ca6-de9e-4143-a652-4591e6fee563
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418810650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2418810650
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.4065741731
Short name T308
Test name
Test status
Simulation time 11130565397 ps
CPU time 98.82 seconds
Started Jan 10 12:29:20 PM PST 24
Finished Jan 10 12:31:24 PM PST 24
Peak memory 246536 kb
Host smart-10cc1f5a-894b-4120-acc0-2eb71d016cd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065741731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.4065741731
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.412707961
Short name T48
Test name
Test status
Simulation time 2045287121 ps
CPU time 26.13 seconds
Started Jan 10 12:29:24 PM PST 24
Finished Jan 10 12:30:17 PM PST 24
Peak memory 248628 kb
Host smart-008b3fd6-4f93-4e10-b57b-560ab10fb25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41270
7961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.412707961
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.644822040
Short name T491
Test name
Test status
Simulation time 1245027945 ps
CPU time 34.13 seconds
Started Jan 10 12:29:20 PM PST 24
Finished Jan 10 12:30:19 PM PST 24
Peak memory 254228 kb
Host smart-83dcdf52-4a6b-4fd8-8ce2-7d60d852ca4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64482
2040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.644822040
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2713269004
Short name T569
Test name
Test status
Simulation time 1504041120 ps
CPU time 18.34 seconds
Started Jan 10 12:29:33 PM PST 24
Finished Jan 10 12:30:18 PM PST 24
Peak memory 248548 kb
Host smart-4c67a541-3089-4eed-9d48-1ed3eac7c3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27132
69004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2713269004
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2348392942
Short name T479
Test name
Test status
Simulation time 5195678731 ps
CPU time 67.75 seconds
Started Jan 10 12:29:34 PM PST 24
Finished Jan 10 12:31:09 PM PST 24
Peak memory 248616 kb
Host smart-adfc1d45-2959-41cb-aa82-e117d1248b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23483
92942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2348392942
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3949643438
Short name T270
Test name
Test status
Simulation time 46834793993 ps
CPU time 2784.67 seconds
Started Jan 10 12:29:15 PM PST 24
Finished Jan 10 01:16:03 PM PST 24
Peak memory 306060 kb
Host smart-00f93872-a09f-4976-b9d0-7e8b64610c11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949643438 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3949643438
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1378268987
Short name T195
Test name
Test status
Simulation time 13683361 ps
CPU time 2.3 seconds
Started Jan 10 12:32:12 PM PST 24
Finished Jan 10 12:32:57 PM PST 24
Peak memory 248504 kb
Host smart-2ec4ccab-ba53-499c-a8ff-148ffbe1922e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1378268987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1378268987
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2195541585
Short name T56
Test name
Test status
Simulation time 28427718466 ps
CPU time 985.1 seconds
Started Jan 10 12:28:31 PM PST 24
Finished Jan 10 12:45:07 PM PST 24
Peak memory 273256 kb
Host smart-5b5428fb-57af-45c5-9d8d-8a83afc80f57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195541585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2195541585
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1708755869
Short name T502
Test name
Test status
Simulation time 355251523 ps
CPU time 16.57 seconds
Started Jan 10 12:28:27 PM PST 24
Finished Jan 10 12:28:54 PM PST 24
Peak memory 240328 kb
Host smart-b953a525-afb8-4598-b9fc-de1120cf17f1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1708755869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1708755869
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3153627348
Short name T209
Test name
Test status
Simulation time 4832033968 ps
CPU time 233.73 seconds
Started Jan 10 12:32:01 PM PST 24
Finished Jan 10 12:36:41 PM PST 24
Peak memory 256376 kb
Host smart-59d89a5e-911c-487a-8b29-8f032b9b1dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31536
27348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3153627348
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2536073189
Short name T463
Test name
Test status
Simulation time 1415795247 ps
CPU time 30.09 seconds
Started Jan 10 12:31:56 PM PST 24
Finished Jan 10 12:33:12 PM PST 24
Peak memory 248076 kb
Host smart-d6dd3888-6865-4e48-a027-8f24e611b702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25360
73189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2536073189
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.503483760
Short name T674
Test name
Test status
Simulation time 148868145688 ps
CPU time 1575.55 seconds
Started Jan 10 12:28:22 PM PST 24
Finished Jan 10 12:54:50 PM PST 24
Peak memory 289276 kb
Host smart-d1c32770-3e2f-46c8-b55f-3e8bd403616c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503483760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.503483760
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.620332351
Short name T473
Test name
Test status
Simulation time 48332342652 ps
CPU time 1474.9 seconds
Started Jan 10 12:34:41 PM PST 24
Finished Jan 10 12:59:57 PM PST 24
Peak memory 272700 kb
Host smart-c1748755-a19d-4c63-a8b5-cb212676a491
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620332351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.620332351
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3470901746
Short name T340
Test name
Test status
Simulation time 11107979618 ps
CPU time 226.7 seconds
Started Jan 10 12:28:28 PM PST 24
Finished Jan 10 12:32:26 PM PST 24
Peak memory 247532 kb
Host smart-ba8729f0-cb0e-4588-a12f-cdf0d045e0f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470901746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3470901746
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2498549493
Short name T392
Test name
Test status
Simulation time 116622558 ps
CPU time 4.75 seconds
Started Jan 10 12:31:54 PM PST 24
Finished Jan 10 12:32:45 PM PST 24
Peak memory 239924 kb
Host smart-a5eea880-59b0-48fd-8af3-27c11da4646d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24985
49493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2498549493
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2127203602
Short name T509
Test name
Test status
Simulation time 218750091 ps
CPU time 10.9 seconds
Started Jan 10 12:31:55 PM PST 24
Finished Jan 10 12:32:53 PM PST 24
Peak memory 254548 kb
Host smart-a613730e-7017-4c61-9bd0-acef86e2388d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21272
03602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2127203602
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.644796553
Short name T45
Test name
Test status
Simulation time 1004897451 ps
CPU time 20.31 seconds
Started Jan 10 12:31:25 PM PST 24
Finished Jan 10 12:32:35 PM PST 24
Peak memory 275064 kb
Host smart-be74034c-a4bd-4949-a101-8b17983dcbd8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=644796553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.644796553
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2046602974
Short name T499
Test name
Test status
Simulation time 571610337 ps
CPU time 27.75 seconds
Started Jan 10 12:34:42 PM PST 24
Finished Jan 10 12:35:51 PM PST 24
Peak memory 256032 kb
Host smart-f2ee45dc-09ae-4d93-9674-ecb0c1d246da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20466
02974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2046602974
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1894350844
Short name T103
Test name
Test status
Simulation time 329970492 ps
CPU time 25.99 seconds
Started Jan 10 12:31:09 PM PST 24
Finished Jan 10 12:32:21 PM PST 24
Peak memory 246788 kb
Host smart-5d3ee56c-e4a6-450a-8bc9-34d8401ad40c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18943
50844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1894350844
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3717980462
Short name T597
Test name
Test status
Simulation time 19186977356 ps
CPU time 1414.56 seconds
Started Jan 10 12:28:31 PM PST 24
Finished Jan 10 12:52:16 PM PST 24
Peak memory 281620 kb
Host smart-e1ba7933-cd56-40b8-a958-891b1ef20f05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717980462 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3717980462
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3870479476
Short name T371
Test name
Test status
Simulation time 3671355884 ps
CPU time 74.03 seconds
Started Jan 10 12:29:29 PM PST 24
Finished Jan 10 12:31:13 PM PST 24
Peak memory 255852 kb
Host smart-62b6d67b-80d4-491b-b202-da3043eaa62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38704
79476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3870479476
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1557672795
Short name T522
Test name
Test status
Simulation time 721112701 ps
CPU time 36.65 seconds
Started Jan 10 12:29:15 PM PST 24
Finished Jan 10 12:30:15 PM PST 24
Peak memory 254868 kb
Host smart-93b296f3-18cb-48ee-a84c-133202952b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15576
72795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1557672795
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3555440411
Short name T114
Test name
Test status
Simulation time 27677987593 ps
CPU time 1791.83 seconds
Started Jan 10 12:29:22 PM PST 24
Finished Jan 10 12:59:41 PM PST 24
Peak memory 282012 kb
Host smart-9b264477-d92a-454e-afde-afe8de693fe0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555440411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3555440411
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1035206963
Short name T325
Test name
Test status
Simulation time 8886074853 ps
CPU time 278.43 seconds
Started Jan 10 12:29:24 PM PST 24
Finished Jan 10 12:34:30 PM PST 24
Peak memory 247536 kb
Host smart-61d721b6-2d54-429e-8b97-e5593ae9f6a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035206963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1035206963
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.4206899696
Short name T589
Test name
Test status
Simulation time 1549921805 ps
CPU time 44.51 seconds
Started Jan 10 12:29:14 PM PST 24
Finished Jan 10 12:30:21 PM PST 24
Peak memory 248448 kb
Host smart-8c1ddc38-caf6-416f-b95c-40c9997674d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42068
99696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4206899696
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2705258238
Short name T627
Test name
Test status
Simulation time 5039816248 ps
CPU time 22.08 seconds
Started Jan 10 12:29:13 PM PST 24
Finished Jan 10 12:29:57 PM PST 24
Peak memory 246756 kb
Host smart-a275eca8-24ca-4fb7-b318-4a07ec3807af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27052
58238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2705258238
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2696488953
Short name T246
Test name
Test status
Simulation time 1928117533 ps
CPU time 57.42 seconds
Started Jan 10 12:29:28 PM PST 24
Finished Jan 10 12:30:52 PM PST 24
Peak memory 254692 kb
Host smart-90551113-65aa-4574-9df2-a84d1ae6cfc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26964
88953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2696488953
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2467377911
Short name T390
Test name
Test status
Simulation time 971769058 ps
CPU time 21.41 seconds
Started Jan 10 12:29:13 PM PST 24
Finished Jan 10 12:29:56 PM PST 24
Peak memory 255284 kb
Host smart-2e4dea7a-8e7f-4a7f-a56a-be34332f482e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24673
77911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2467377911
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3556849566
Short name T98
Test name
Test status
Simulation time 27143643487 ps
CPU time 1655.13 seconds
Started Jan 10 12:29:25 PM PST 24
Finished Jan 10 12:57:27 PM PST 24
Peak memory 281300 kb
Host smart-6fd3ac68-703b-4539-bad7-4a00864cf2e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556849566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3556849566
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1597454660
Short name T63
Test name
Test status
Simulation time 78402512359 ps
CPU time 4772.78 seconds
Started Jan 10 12:29:23 PM PST 24
Finished Jan 10 01:49:24 PM PST 24
Peak memory 305492 kb
Host smart-9148a77b-64c9-4812-886d-872dca6ff794
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597454660 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1597454660
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1636850972
Short name T543
Test name
Test status
Simulation time 55541566747 ps
CPU time 1861.6 seconds
Started Jan 10 12:29:29 PM PST 24
Finished Jan 10 01:00:56 PM PST 24
Peak memory 273224 kb
Host smart-c95f67b3-d5b4-485f-b4ed-27a95e7866f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636850972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1636850972
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1496628093
Short name T513
Test name
Test status
Simulation time 42914225604 ps
CPU time 314.9 seconds
Started Jan 10 12:29:27 PM PST 24
Finished Jan 10 12:35:09 PM PST 24
Peak memory 250608 kb
Host smart-e73d57e6-f43a-4901-bf5e-3f4f76dadcb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14966
28093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1496628093
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3611443585
Short name T80
Test name
Test status
Simulation time 585535846 ps
CPU time 29.16 seconds
Started Jan 10 12:29:59 PM PST 24
Finished Jan 10 12:31:10 PM PST 24
Peak memory 255016 kb
Host smart-602809f6-b406-451c-8397-98c33e6e64b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36114
43585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3611443585
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.203097480
Short name T576
Test name
Test status
Simulation time 124053474753 ps
CPU time 1803.78 seconds
Started Jan 10 12:29:45 PM PST 24
Finished Jan 10 01:00:23 PM PST 24
Peak memory 272432 kb
Host smart-5712f34a-dcf8-4a8c-9dce-96a49792e730
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203097480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.203097480
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.203825154
Short name T458
Test name
Test status
Simulation time 154949210347 ps
CPU time 2489.01 seconds
Started Jan 10 12:29:30 PM PST 24
Finished Jan 10 01:11:26 PM PST 24
Peak memory 284724 kb
Host smart-6d4a3626-e2d4-4ff6-b636-ff3295723d4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203825154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.203825154
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3031551149
Short name T512
Test name
Test status
Simulation time 1546254084 ps
CPU time 34.16 seconds
Started Jan 10 12:29:20 PM PST 24
Finished Jan 10 12:30:20 PM PST 24
Peak memory 248624 kb
Host smart-b60463a6-dd37-4024-8c54-2f1d37018715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30315
51149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3031551149
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2858752668
Short name T607
Test name
Test status
Simulation time 927832777 ps
CPU time 53.52 seconds
Started Jan 10 12:29:27 PM PST 24
Finished Jan 10 12:30:47 PM PST 24
Peak memory 255840 kb
Host smart-ffd71b51-e56d-468f-bfcc-4b28d8ef8bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28587
52668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2858752668
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2909493926
Short name T259
Test name
Test status
Simulation time 1402973375 ps
CPU time 42.35 seconds
Started Jan 10 12:29:14 PM PST 24
Finished Jan 10 12:30:19 PM PST 24
Peak memory 255536 kb
Host smart-68500673-2556-4669-812c-7249e8ea5a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29094
93926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2909493926
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3491026728
Short name T652
Test name
Test status
Simulation time 3718028360 ps
CPU time 56.24 seconds
Started Jan 10 12:29:48 PM PST 24
Finished Jan 10 12:31:17 PM PST 24
Peak memory 248584 kb
Host smart-513ff03e-e56f-472a-a5b6-30b9fb2fbc49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34910
26728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3491026728
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2265978181
Short name T220
Test name
Test status
Simulation time 19020683826 ps
CPU time 167.24 seconds
Started Jan 10 12:29:34 PM PST 24
Finished Jan 10 12:32:48 PM PST 24
Peak memory 256848 kb
Host smart-a256a2da-1a97-4267-96ed-c840980d3110
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265978181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2265978181
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3210339404
Short name T109
Test name
Test status
Simulation time 17670785789 ps
CPU time 1443.65 seconds
Started Jan 10 12:29:55 PM PST 24
Finished Jan 10 12:54:37 PM PST 24
Peak memory 289232 kb
Host smart-ea683cd7-4e5d-424a-8a40-e0c93caa81b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210339404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3210339404
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1464127313
Short name T397
Test name
Test status
Simulation time 6709374343 ps
CPU time 127.62 seconds
Started Jan 10 12:30:06 PM PST 24
Finished Jan 10 12:32:54 PM PST 24
Peak memory 256668 kb
Host smart-85eb25ab-bb66-4118-8ccf-a2c0edeca267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14641
27313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1464127313
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.562293017
Short name T258
Test name
Test status
Simulation time 421536549 ps
CPU time 24.04 seconds
Started Jan 10 12:29:48 PM PST 24
Finished Jan 10 12:30:45 PM PST 24
Peak memory 255588 kb
Host smart-ae79e600-7ba1-4a75-a8f3-59254b6bf6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56229
3017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.562293017
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3882528802
Short name T481
Test name
Test status
Simulation time 95035798483 ps
CPU time 3273.09 seconds
Started Jan 10 12:29:46 PM PST 24
Finished Jan 10 01:24:53 PM PST 24
Peak memory 289220 kb
Host smart-49706c38-d4ce-43d6-93ee-1b7658aa55d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882528802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3882528802
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.961918062
Short name T331
Test name
Test status
Simulation time 15049852425 ps
CPU time 580.74 seconds
Started Jan 10 12:29:31 PM PST 24
Finished Jan 10 12:39:37 PM PST 24
Peak memory 247480 kb
Host smart-7a5247ac-b287-4b9e-b125-155fcdd2200d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961918062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.961918062
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1154808717
Short name T221
Test name
Test status
Simulation time 477996371 ps
CPU time 3.68 seconds
Started Jan 10 12:30:12 PM PST 24
Finished Jan 10 12:30:56 PM PST 24
Peak memory 240232 kb
Host smart-9bb61b8e-0669-47f3-8089-43e257c71937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11548
08717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1154808717
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3444418112
Short name T280
Test name
Test status
Simulation time 1405312312 ps
CPU time 38.71 seconds
Started Jan 10 12:29:45 PM PST 24
Finished Jan 10 12:30:57 PM PST 24
Peak memory 246996 kb
Host smart-d13e9f0b-e705-43eb-920f-384c9f5590ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34444
18112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3444418112
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.904360777
Short name T540
Test name
Test status
Simulation time 264694030 ps
CPU time 14.61 seconds
Started Jan 10 12:29:53 PM PST 24
Finished Jan 10 12:30:45 PM PST 24
Peak memory 254796 kb
Host smart-7fc95550-82fc-4129-ab0f-059f29051cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90436
0777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.904360777
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1359397484
Short name T538
Test name
Test status
Simulation time 243094783 ps
CPU time 24.01 seconds
Started Jan 10 12:29:46 PM PST 24
Finished Jan 10 12:30:43 PM PST 24
Peak memory 248628 kb
Host smart-e616e38e-3456-41fd-be5a-50b05c1a7416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13593
97484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1359397484
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1195209081
Short name T585
Test name
Test status
Simulation time 14300454160 ps
CPU time 1162.11 seconds
Started Jan 10 12:29:51 PM PST 24
Finished Jan 10 12:49:49 PM PST 24
Peak memory 288692 kb
Host smart-2fa8f798-78d8-4284-ac9a-401bfb337be2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195209081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1195209081
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2353167594
Short name T593
Test name
Test status
Simulation time 17547088743 ps
CPU time 1282.31 seconds
Started Jan 10 12:29:38 PM PST 24
Finished Jan 10 12:51:31 PM PST 24
Peak memory 286440 kb
Host smart-634e4b36-f671-4aba-b269-77c0a089fd1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353167594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2353167594
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3772745425
Short name T278
Test name
Test status
Simulation time 15833327512 ps
CPU time 196.01 seconds
Started Jan 10 12:29:36 PM PST 24
Finished Jan 10 12:33:21 PM PST 24
Peak memory 248856 kb
Host smart-05d52853-974e-4b4b-9ed3-1dcebe323048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37727
45425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3772745425
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2971287227
Short name T594
Test name
Test status
Simulation time 4634100656 ps
CPU time 61.67 seconds
Started Jan 10 12:29:36 PM PST 24
Finished Jan 10 12:31:07 PM PST 24
Peak memory 254356 kb
Host smart-4e612b20-045c-48e5-b18e-4c564ceb52c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29712
87227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2971287227
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2986302823
Short name T704
Test name
Test status
Simulation time 44106452546 ps
CPU time 2528.82 seconds
Started Jan 10 12:29:43 PM PST 24
Finished Jan 10 01:12:25 PM PST 24
Peak memory 289128 kb
Host smart-f669eab3-bd58-418c-adc2-b025f4682262
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986302823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2986302823
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3537045863
Short name T106
Test name
Test status
Simulation time 45361783200 ps
CPU time 1162.55 seconds
Started Jan 10 12:30:23 PM PST 24
Finished Jan 10 12:50:26 PM PST 24
Peak memory 264952 kb
Host smart-c7f86540-c906-4d93-868b-5c6f990421bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537045863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3537045863
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3030202819
Short name T316
Test name
Test status
Simulation time 16376287840 ps
CPU time 147.1 seconds
Started Jan 10 12:32:11 PM PST 24
Finished Jan 10 12:35:21 PM PST 24
Peak memory 248264 kb
Host smart-537a3f40-7c96-48e1-841d-b281e96f4228
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030202819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3030202819
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1286364243
Short name T529
Test name
Test status
Simulation time 1161996474 ps
CPU time 32.09 seconds
Started Jan 10 12:29:49 PM PST 24
Finished Jan 10 12:30:55 PM PST 24
Peak memory 248492 kb
Host smart-a1aa1753-b43b-4ce4-b3fa-744c12ec7397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12863
64243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1286364243
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1637973531
Short name T477
Test name
Test status
Simulation time 819878994 ps
CPU time 21.45 seconds
Started Jan 10 12:29:49 PM PST 24
Finished Jan 10 12:30:45 PM PST 24
Peak memory 254612 kb
Host smart-bb97d604-9ff4-4d1e-94d9-c0b1ab174f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16379
73531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1637973531
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1370908975
Short name T574
Test name
Test status
Simulation time 872960133 ps
CPU time 8.81 seconds
Started Jan 10 12:29:45 PM PST 24
Finished Jan 10 12:30:28 PM PST 24
Peak memory 240384 kb
Host smart-51ab9e45-d5c3-4742-82b8-49e17d49ce8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13709
08975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1370908975
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3380717161
Short name T582
Test name
Test status
Simulation time 1139209441 ps
CPU time 94.48 seconds
Started Jan 10 12:30:21 PM PST 24
Finished Jan 10 12:32:36 PM PST 24
Peak memory 250192 kb
Host smart-8bdf90d2-77f4-420a-898f-2250d7bd7aed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380717161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3380717161
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.726368896
Short name T695
Test name
Test status
Simulation time 278368158463 ps
CPU time 7089.77 seconds
Started Jan 10 12:29:46 PM PST 24
Finished Jan 10 02:28:29 PM PST 24
Peak memory 371320 kb
Host smart-0be9d8fe-2d6e-4db2-8b16-ef6cb900fd3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726368896 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.726368896
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3844947095
Short name T659
Test name
Test status
Simulation time 82007248021 ps
CPU time 2101.94 seconds
Started Jan 10 12:29:44 PM PST 24
Finished Jan 10 01:05:20 PM PST 24
Peak memory 288844 kb
Host smart-4a423dcc-d5a1-4852-ab0c-fc49ce94edb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844947095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3844947095
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.4193434078
Short name T471
Test name
Test status
Simulation time 7007317685 ps
CPU time 33.46 seconds
Started Jan 10 12:29:45 PM PST 24
Finished Jan 10 12:30:52 PM PST 24
Peak memory 248220 kb
Host smart-3504190d-d5f1-4d5d-b2a4-eefc384a87c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41934
34078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.4193434078
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1642119693
Short name T84
Test name
Test status
Simulation time 738477994 ps
CPU time 42.03 seconds
Started Jan 10 12:29:31 PM PST 24
Finished Jan 10 12:30:38 PM PST 24
Peak memory 254912 kb
Host smart-65780227-350c-4b96-8c1e-7cb5ed2533c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16421
19693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1642119693
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1490375125
Short name T286
Test name
Test status
Simulation time 27206026404 ps
CPU time 973.67 seconds
Started Jan 10 12:29:44 PM PST 24
Finished Jan 10 12:46:31 PM PST 24
Peak memory 272272 kb
Host smart-7d4cd838-54ec-4c11-8c37-3583b899765c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490375125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1490375125
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1585399321
Short name T11
Test name
Test status
Simulation time 60242815758 ps
CPU time 253.48 seconds
Started Jan 10 12:29:47 PM PST 24
Finished Jan 10 12:34:34 PM PST 24
Peak memory 254808 kb
Host smart-5402d988-1174-47dc-9cfa-4c582d4a1ecb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585399321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1585399321
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1124685608
Short name T678
Test name
Test status
Simulation time 407439309 ps
CPU time 19.78 seconds
Started Jan 10 12:29:29 PM PST 24
Finished Jan 10 12:30:15 PM PST 24
Peak memory 248548 kb
Host smart-3abcd097-2a7a-4e12-ab5b-70b0fde2d53b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11246
85608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1124685608
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2796376984
Short name T544
Test name
Test status
Simulation time 142384176 ps
CPU time 8.87 seconds
Started Jan 10 12:29:32 PM PST 24
Finished Jan 10 12:30:06 PM PST 24
Peak memory 250340 kb
Host smart-fb28b0ed-a0c5-4863-9d05-8d4a4c868081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27963
76984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2796376984
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2755744419
Short name T254
Test name
Test status
Simulation time 513192381 ps
CPU time 27.02 seconds
Started Jan 10 12:32:10 PM PST 24
Finished Jan 10 12:33:21 PM PST 24
Peak memory 248236 kb
Host smart-63ea0a5e-49da-4e99-96e7-3e103d52c8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27557
44419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2755744419
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1584585159
Short name T407
Test name
Test status
Simulation time 2388404802 ps
CPU time 40.3 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:31:25 PM PST 24
Peak memory 248756 kb
Host smart-0b3e5d40-fe40-4762-809c-e35304ef832d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15845
85159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1584585159
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.916688836
Short name T561
Test name
Test status
Simulation time 69233689359 ps
CPU time 583.73 seconds
Started Jan 10 12:29:54 PM PST 24
Finished Jan 10 12:40:15 PM PST 24
Peak memory 256820 kb
Host smart-be482e39-3de2-4626-8b0b-4657155cec2f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916688836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.916688836
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2412068056
Short name T550
Test name
Test status
Simulation time 27823210543 ps
CPU time 2645.49 seconds
Started Jan 10 12:29:31 PM PST 24
Finished Jan 10 01:14:02 PM PST 24
Peak memory 315752 kb
Host smart-bf8e397b-82f6-4140-9af9-76eaa1b4bd6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412068056 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2412068056
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3234958659
Short name T92
Test name
Test status
Simulation time 107727712086 ps
CPU time 1479.99 seconds
Started Jan 10 12:30:16 PM PST 24
Finished Jan 10 12:55:36 PM PST 24
Peak memory 272500 kb
Host smart-f4d757fa-10d2-4105-87b0-669b39624c38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234958659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3234958659
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1237254635
Short name T401
Test name
Test status
Simulation time 8940930791 ps
CPU time 134.73 seconds
Started Jan 10 12:29:38 PM PST 24
Finished Jan 10 12:32:23 PM PST 24
Peak memory 256412 kb
Host smart-27474e79-9829-47b1-a396-d0d1ba48ab64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12372
54635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1237254635
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2058639200
Short name T379
Test name
Test status
Simulation time 380513026 ps
CPU time 29.03 seconds
Started Jan 10 12:29:39 PM PST 24
Finished Jan 10 12:30:38 PM PST 24
Peak memory 248604 kb
Host smart-b11af844-9f39-4b03-af99-dd99990250d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20586
39200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2058639200
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1884423464
Short name T349
Test name
Test status
Simulation time 98170253955 ps
CPU time 1578.31 seconds
Started Jan 10 12:29:38 PM PST 24
Finished Jan 10 12:56:25 PM PST 24
Peak memory 272516 kb
Host smart-5694f409-a420-487e-907e-77cb361e5238
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884423464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1884423464
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3595241211
Short name T553
Test name
Test status
Simulation time 37580120622 ps
CPU time 2101.98 seconds
Started Jan 10 12:29:39 PM PST 24
Finished Jan 10 01:05:11 PM PST 24
Peak memory 287984 kb
Host smart-bb3d20b9-2df9-46e3-8d53-c51a39a1feb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595241211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3595241211
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2780203740
Short name T44
Test name
Test status
Simulation time 832905015 ps
CPU time 51.12 seconds
Started Jan 10 12:29:48 PM PST 24
Finished Jan 10 12:31:13 PM PST 24
Peak memory 248444 kb
Host smart-e6cb977c-0761-4203-a266-e92dddf2109c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27802
03740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2780203740
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1737383407
Short name T60
Test name
Test status
Simulation time 208556674 ps
CPU time 22.82 seconds
Started Jan 10 12:29:36 PM PST 24
Finished Jan 10 12:30:27 PM PST 24
Peak memory 246956 kb
Host smart-9822007c-3e72-48a6-beba-a4e78666f740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17373
83407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1737383407
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3985008136
Short name T691
Test name
Test status
Simulation time 220588442 ps
CPU time 23.49 seconds
Started Jan 10 12:29:50 PM PST 24
Finished Jan 10 12:30:49 PM PST 24
Peak memory 248444 kb
Host smart-0a3ac5c9-db6a-4768-93f3-8cb89b4663db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39850
08136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3985008136
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2366210151
Short name T545
Test name
Test status
Simulation time 2139423484 ps
CPU time 28.05 seconds
Started Jan 10 12:29:31 PM PST 24
Finished Jan 10 12:30:24 PM PST 24
Peak memory 248460 kb
Host smart-f8a588b4-27c8-4e7b-be2e-6e17219c4cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23662
10151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2366210151
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2434433421
Short name T640
Test name
Test status
Simulation time 652928479818 ps
CPU time 2227.03 seconds
Started Jan 10 12:29:50 PM PST 24
Finished Jan 10 01:07:32 PM PST 24
Peak memory 281352 kb
Host smart-dc1d0a8a-1f6d-4c14-a0e2-e07bd3c01095
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434433421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2434433421
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1989325239
Short name T476
Test name
Test status
Simulation time 13968566146 ps
CPU time 1156.15 seconds
Started Jan 10 12:30:22 PM PST 24
Finished Jan 10 12:50:19 PM PST 24
Peak memory 288800 kb
Host smart-dfdd8930-fecf-4a54-894d-e63f36eab694
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989325239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1989325239
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1206675726
Short name T267
Test name
Test status
Simulation time 5806087285 ps
CPU time 300.21 seconds
Started Jan 10 12:29:50 PM PST 24
Finished Jan 10 12:35:25 PM PST 24
Peak memory 256172 kb
Host smart-5ca3d7e6-194a-4d41-9b9f-b0bb7b5eadc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12066
75726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1206675726
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2878982146
Short name T510
Test name
Test status
Simulation time 590156327 ps
CPU time 20.15 seconds
Started Jan 10 12:29:45 PM PST 24
Finished Jan 10 12:30:39 PM PST 24
Peak memory 256624 kb
Host smart-eccc10ed-6320-414f-b23a-7f2c12c44a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28789
82146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2878982146
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2805526615
Short name T665
Test name
Test status
Simulation time 16214953245 ps
CPU time 1359.36 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 12:53:07 PM PST 24
Peak memory 287572 kb
Host smart-68cd79b4-330b-4150-b322-095641c7ebea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805526615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2805526615
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3149463466
Short name T504
Test name
Test status
Simulation time 36990983707 ps
CPU time 842.31 seconds
Started Jan 10 12:29:50 PM PST 24
Finished Jan 10 12:44:28 PM PST 24
Peak memory 269000 kb
Host smart-22941f29-b57e-452c-b8df-1f9caa7a466f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149463466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3149463466
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2264622754
Short name T730
Test name
Test status
Simulation time 22858406750 ps
CPU time 437.79 seconds
Started Jan 10 12:30:31 PM PST 24
Finished Jan 10 12:38:31 PM PST 24
Peak memory 247204 kb
Host smart-de747cdb-8cfd-40b4-bf78-ceeb5694f987
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264622754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2264622754
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1200469063
Short name T699
Test name
Test status
Simulation time 1047040732 ps
CPU time 29.29 seconds
Started Jan 10 12:29:34 PM PST 24
Finished Jan 10 12:30:30 PM PST 24
Peak memory 255192 kb
Host smart-7b0724e8-289d-408f-ac06-92e59f51ca79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12004
69063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1200469063
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3516710600
Short name T682
Test name
Test status
Simulation time 880793072 ps
CPU time 19.54 seconds
Started Jan 10 12:29:45 PM PST 24
Finished Jan 10 12:30:38 PM PST 24
Peak memory 248556 kb
Host smart-d15b02a4-0a65-48b6-b941-73ac2d722f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35167
10600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3516710600
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2927345800
Short name T101
Test name
Test status
Simulation time 132353048 ps
CPU time 12.82 seconds
Started Jan 10 12:30:05 PM PST 24
Finished Jan 10 12:30:59 PM PST 24
Peak memory 254912 kb
Host smart-34406669-6dcd-4f3d-9934-60fbd470875d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29273
45800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2927345800
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3236432500
Short name T684
Test name
Test status
Simulation time 4398456066 ps
CPU time 26.94 seconds
Started Jan 10 12:29:50 PM PST 24
Finished Jan 10 12:30:53 PM PST 24
Peak memory 255460 kb
Host smart-741525a3-0111-47a0-a0d3-d3a6d3d6017a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32364
32500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3236432500
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1538728420
Short name T644
Test name
Test status
Simulation time 38772749092 ps
CPU time 1688.02 seconds
Started Jan 10 12:29:45 PM PST 24
Finished Jan 10 12:58:27 PM PST 24
Peak memory 284676 kb
Host smart-1c51e5b8-88bd-4a3e-8cb1-e27e6fb9c2e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538728420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1538728420
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1359517739
Short name T622
Test name
Test status
Simulation time 64657665541 ps
CPU time 1001.41 seconds
Started Jan 10 12:30:21 PM PST 24
Finished Jan 10 12:47:43 PM PST 24
Peak memory 272388 kb
Host smart-0c2e1762-9d3b-4510-bb13-d9970fb0f92b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359517739 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1359517739
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2476846177
Short name T600
Test name
Test status
Simulation time 42580292261 ps
CPU time 2224.51 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 01:07:33 PM PST 24
Peak memory 284592 kb
Host smart-efdcac7c-2499-4900-85ea-b4098e80ceb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476846177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2476846177
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3841595019
Short name T377
Test name
Test status
Simulation time 153113172 ps
CPU time 4.16 seconds
Started Jan 10 12:30:26 PM PST 24
Finished Jan 10 12:31:11 PM PST 24
Peak memory 250168 kb
Host smart-4e5ace88-4cf3-4d2d-b6db-5652488bfea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38415
95019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3841595019
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1222637614
Short name T501
Test name
Test status
Simulation time 690080454 ps
CPU time 18.41 seconds
Started Jan 10 12:29:29 PM PST 24
Finished Jan 10 12:30:13 PM PST 24
Peak memory 253788 kb
Host smart-d85a9646-cf3e-4d80-94ce-ce053de98495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12226
37614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1222637614
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.4237167096
Short name T536
Test name
Test status
Simulation time 17388053361 ps
CPU time 538.87 seconds
Started Jan 10 12:29:45 PM PST 24
Finished Jan 10 12:39:18 PM PST 24
Peak memory 264984 kb
Host smart-7ebd79f6-24b0-4c1b-8ac9-78ab09c44059
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237167096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.4237167096
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3080653399
Short name T495
Test name
Test status
Simulation time 209170671190 ps
CPU time 2699.8 seconds
Started Jan 10 12:29:51 PM PST 24
Finished Jan 10 01:15:27 PM PST 24
Peak memory 287508 kb
Host smart-47098141-056d-4837-a63e-0c1e3f05d718
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080653399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3080653399
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2712512521
Short name T328
Test name
Test status
Simulation time 30960748072 ps
CPU time 323.4 seconds
Started Jan 10 12:29:56 PM PST 24
Finished Jan 10 12:35:58 PM PST 24
Peak memory 247568 kb
Host smart-c6b380e2-ebce-4094-b007-29ba84da5e02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712512521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2712512521
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.837826594
Short name T586
Test name
Test status
Simulation time 2562018668 ps
CPU time 25.82 seconds
Started Jan 10 12:29:46 PM PST 24
Finished Jan 10 12:30:45 PM PST 24
Peak memory 255276 kb
Host smart-4bcbc110-ef76-47ce-a7c7-2c6a8fc08dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83782
6594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.837826594
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.714649754
Short name T39
Test name
Test status
Simulation time 69899995 ps
CPU time 3.93 seconds
Started Jan 10 12:29:50 PM PST 24
Finished Jan 10 12:30:37 PM PST 24
Peak memory 238576 kb
Host smart-c98575c0-ce30-4f4c-9128-fcdc76e31c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71464
9754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.714649754
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1530922205
Short name T690
Test name
Test status
Simulation time 57072753 ps
CPU time 6.32 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 12:30:35 PM PST 24
Peak memory 240372 kb
Host smart-456fd42c-2be4-4bcc-b7ca-36b542c5c349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15309
22205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1530922205
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.311386278
Short name T590
Test name
Test status
Simulation time 860001432 ps
CPU time 18.91 seconds
Started Jan 10 12:30:29 PM PST 24
Finished Jan 10 12:31:29 PM PST 24
Peak memory 255164 kb
Host smart-7bb822b2-8cd6-43e9-aa4c-4222e5fe1386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31138
6278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.311386278
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.4257279408
Short name T120
Test name
Test status
Simulation time 114394299303 ps
CPU time 3469.87 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 01:28:34 PM PST 24
Peak memory 289332 kb
Host smart-9c95c5b2-bb14-46fe-abad-4cd49ee77bba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257279408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.4257279408
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.394188085
Short name T87
Test name
Test status
Simulation time 243913448822 ps
CPU time 2964.52 seconds
Started Jan 10 12:29:51 PM PST 24
Finished Jan 10 01:19:51 PM PST 24
Peak memory 305048 kb
Host smart-870bf233-af56-486e-abb9-4122e5265a85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394188085 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.394188085
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3005989543
Short name T294
Test name
Test status
Simulation time 16811688038 ps
CPU time 917.12 seconds
Started Jan 10 12:29:48 PM PST 24
Finished Jan 10 12:45:39 PM PST 24
Peak memory 283168 kb
Host smart-e0427140-d4d0-4def-bec7-a7249a8887d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005989543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3005989543
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.92362690
Short name T698
Test name
Test status
Simulation time 6688434542 ps
CPU time 189.91 seconds
Started Jan 10 12:29:37 PM PST 24
Finished Jan 10 12:33:16 PM PST 24
Peak memory 249556 kb
Host smart-dd866e08-4fa1-4d6b-94ff-90c5e11c4de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92362
690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.92362690
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.559956197
Short name T528
Test name
Test status
Simulation time 82359476 ps
CPU time 6.75 seconds
Started Jan 10 12:29:47 PM PST 24
Finished Jan 10 12:30:27 PM PST 24
Peak memory 252364 kb
Host smart-a7d0aae7-232b-4ede-a96f-f3e4680c92b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55995
6197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.559956197
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.754605107
Short name T623
Test name
Test status
Simulation time 98591203541 ps
CPU time 1507.05 seconds
Started Jan 10 12:30:06 PM PST 24
Finished Jan 10 12:55:54 PM PST 24
Peak memory 272456 kb
Host smart-e12751f3-ed32-4c6b-85e4-ff0fc976ba6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754605107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.754605107
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2873714591
Short name T7
Test name
Test status
Simulation time 6693823348 ps
CPU time 645.08 seconds
Started Jan 10 12:30:19 PM PST 24
Finished Jan 10 12:41:44 PM PST 24
Peak memory 265000 kb
Host smart-0da2a59a-219c-4338-9188-8bcf60df2e73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873714591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2873714591
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2159590582
Short name T613
Test name
Test status
Simulation time 7810637944 ps
CPU time 307.72 seconds
Started Jan 10 12:29:46 PM PST 24
Finished Jan 10 12:35:27 PM PST 24
Peak memory 247396 kb
Host smart-3078149b-b6b2-4977-8cbd-3a9fe56afe37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159590582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2159590582
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2426874505
Short name T497
Test name
Test status
Simulation time 1163829655 ps
CPU time 55.35 seconds
Started Jan 10 12:30:18 PM PST 24
Finished Jan 10 12:31:52 PM PST 24
Peak memory 248492 kb
Host smart-bc46ab8f-e8b8-4f74-b66f-74e86bc97e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24268
74505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2426874505
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2935825317
Short name T725
Test name
Test status
Simulation time 197380798 ps
CPU time 15.5 seconds
Started Jan 10 12:29:51 PM PST 24
Finished Jan 10 12:30:42 PM PST 24
Peak memory 248668 kb
Host smart-6ecd93d1-6b1d-4fc3-8df1-a734604a473e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29358
25317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2935825317
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3994381346
Short name T587
Test name
Test status
Simulation time 117336824 ps
CPU time 2.66 seconds
Started Jan 10 12:29:46 PM PST 24
Finished Jan 10 12:30:22 PM PST 24
Peak memory 238568 kb
Host smart-16421a75-690b-40c6-9474-a35ea7a76e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39943
81346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3994381346
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3625816665
Short name T388
Test name
Test status
Simulation time 880475193 ps
CPU time 24.7 seconds
Started Jan 10 12:29:54 PM PST 24
Finished Jan 10 12:30:56 PM PST 24
Peak memory 248664 kb
Host smart-639e2d49-f004-49e7-b61f-02718b9d1894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36258
16665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3625816665
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1270175727
Short name T55
Test name
Test status
Simulation time 743080516 ps
CPU time 10.86 seconds
Started Jan 10 12:30:21 PM PST 24
Finished Jan 10 12:31:13 PM PST 24
Peak memory 248852 kb
Host smart-3be98b8b-aaaf-4121-b204-f33d38093e9f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270175727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1270175727
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1406597842
Short name T71
Test name
Test status
Simulation time 11019539917 ps
CPU time 743.01 seconds
Started Jan 10 12:29:38 PM PST 24
Finished Jan 10 12:42:31 PM PST 24
Peak memory 268972 kb
Host smart-db74ee80-08df-45df-af5a-efa5d1f8f36c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406597842 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1406597842
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1690861353
Short name T702
Test name
Test status
Simulation time 47982729617 ps
CPU time 1318 seconds
Started Jan 10 12:29:36 PM PST 24
Finished Jan 10 12:52:01 PM PST 24
Peak memory 289428 kb
Host smart-a7eedc72-c7d8-4868-9492-a5d35c916696
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690861353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1690861353
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2607343266
Short name T716
Test name
Test status
Simulation time 1406809540 ps
CPU time 88.43 seconds
Started Jan 10 12:29:39 PM PST 24
Finished Jan 10 12:31:38 PM PST 24
Peak memory 248572 kb
Host smart-885f7301-b4d8-4daf-980c-1e3fde59662d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26073
43266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2607343266
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.187066339
Short name T525
Test name
Test status
Simulation time 526343455 ps
CPU time 22.28 seconds
Started Jan 10 12:30:18 PM PST 24
Finished Jan 10 12:31:20 PM PST 24
Peak memory 246936 kb
Host smart-6e254f6a-c132-46e2-8da8-5603340e8bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18706
6339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.187066339
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.4176653422
Short name T348
Test name
Test status
Simulation time 62417416786 ps
CPU time 1080.08 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:48:45 PM PST 24
Peak memory 264996 kb
Host smart-62a7a113-9df5-4bdb-bb42-c125ac59ddbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176653422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.4176653422
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2477224626
Short name T577
Test name
Test status
Simulation time 228551296500 ps
CPU time 2974.16 seconds
Started Jan 10 12:29:53 PM PST 24
Finished Jan 10 01:20:05 PM PST 24
Peak memory 287436 kb
Host smart-72d51709-d0d5-46db-bfb1-b510aa7c7961
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477224626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2477224626
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1617389578
Short name T104
Test name
Test status
Simulation time 10261860262 ps
CPU time 202.97 seconds
Started Jan 10 12:29:57 PM PST 24
Finished Jan 10 12:33:59 PM PST 24
Peak memory 247500 kb
Host smart-a69f23b0-8342-454b-842c-c2c89cf0efe5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617389578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1617389578
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1041568233
Short name T440
Test name
Test status
Simulation time 1863681080 ps
CPU time 26.96 seconds
Started Jan 10 12:29:56 PM PST 24
Finished Jan 10 12:31:03 PM PST 24
Peak memory 248440 kb
Host smart-c75f7635-b9c5-4eee-9bb5-323849e30584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10415
68233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1041568233
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.386630678
Short name T93
Test name
Test status
Simulation time 1229229040 ps
CPU time 28.79 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 12:30:57 PM PST 24
Peak memory 247172 kb
Host smart-99d60363-d5fb-42f9-b2d1-6f77370de0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38663
0678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.386630678
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1110632064
Short name T661
Test name
Test status
Simulation time 1015906658 ps
CPU time 58.76 seconds
Started Jan 10 12:29:56 PM PST 24
Finished Jan 10 12:31:33 PM PST 24
Peak memory 254732 kb
Host smart-914c3726-2cd9-4b8a-9aa7-718ca3bc0e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11106
32064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1110632064
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3578144130
Short name T557
Test name
Test status
Simulation time 1650429762 ps
CPU time 33.98 seconds
Started Jan 10 12:30:32 PM PST 24
Finished Jan 10 12:31:48 PM PST 24
Peak memory 248696 kb
Host smart-d5d5f870-3b3a-4cd6-9b89-aac31acfcfe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35781
44130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3578144130
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3396217826
Short name T122
Test name
Test status
Simulation time 7605315270 ps
CPU time 103.82 seconds
Started Jan 10 12:29:47 PM PST 24
Finished Jan 10 12:32:04 PM PST 24
Peak memory 256692 kb
Host smart-27cd41db-9f83-4859-b2e2-8c4d581096a6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396217826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3396217826
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1755812836
Short name T69
Test name
Test status
Simulation time 40954032239 ps
CPU time 3718.48 seconds
Started Jan 10 12:29:55 PM PST 24
Finished Jan 10 01:32:33 PM PST 24
Peak memory 338828 kb
Host smart-7a8deae1-269e-47da-83b4-e3346e6384cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755812836 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1755812836
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.763453606
Short name T197
Test name
Test status
Simulation time 36695193 ps
CPU time 3.11 seconds
Started Jan 10 12:31:59 PM PST 24
Finished Jan 10 12:32:49 PM PST 24
Peak memory 247936 kb
Host smart-561ea63c-d46d-4d72-95ee-ed005274ddca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=763453606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.763453606
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.975291739
Short name T648
Test name
Test status
Simulation time 47724190006 ps
CPU time 2498.1 seconds
Started Jan 10 12:32:01 PM PST 24
Finished Jan 10 01:14:25 PM PST 24
Peak memory 288740 kb
Host smart-a25cc5ca-3ad1-4e97-9397-73d861545905
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975291739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.975291739
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3755839482
Short name T231
Test name
Test status
Simulation time 1084761815 ps
CPU time 36.93 seconds
Started Jan 10 12:32:01 PM PST 24
Finished Jan 10 12:33:24 PM PST 24
Peak memory 248116 kb
Host smart-07167d90-e103-4460-b0a3-1e3a7f29a916
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3755839482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3755839482
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1057957104
Short name T719
Test name
Test status
Simulation time 16842299019 ps
CPU time 252.75 seconds
Started Jan 10 12:32:29 PM PST 24
Finished Jan 10 12:37:16 PM PST 24
Peak memory 255944 kb
Host smart-f275af20-aab2-477e-b7b8-0c2df65cff15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10579
57104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1057957104
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.126978390
Short name T616
Test name
Test status
Simulation time 1333316596 ps
CPU time 38.53 seconds
Started Jan 10 12:28:20 PM PST 24
Finished Jan 10 12:29:12 PM PST 24
Peak memory 254280 kb
Host smart-e67d62ae-f8af-4414-b996-88a0868317b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12697
8390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.126978390
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.4170280782
Short name T721
Test name
Test status
Simulation time 28000125998 ps
CPU time 1104.87 seconds
Started Jan 10 12:32:28 PM PST 24
Finished Jan 10 12:51:28 PM PST 24
Peak memory 281972 kb
Host smart-9fa298eb-c7f5-4bf8-b5e1-eaa3b9144e49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170280782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.4170280782
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.948965756
Short name T318
Test name
Test status
Simulation time 12189246820 ps
CPU time 243.94 seconds
Started Jan 10 12:32:28 PM PST 24
Finished Jan 10 12:37:07 PM PST 24
Peak memory 248196 kb
Host smart-5f9d7762-1159-4365-80d2-dbd2e9b09213
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948965756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.948965756
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.668509886
Short name T445
Test name
Test status
Simulation time 360669380 ps
CPU time 18.37 seconds
Started Jan 10 12:31:25 PM PST 24
Finished Jan 10 12:32:33 PM PST 24
Peak memory 253856 kb
Host smart-3d070ac8-b6d2-458f-a94b-62d6d3ba0bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66850
9886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.668509886
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1773535095
Short name T689
Test name
Test status
Simulation time 238544777 ps
CPU time 4.03 seconds
Started Jan 10 12:28:29 PM PST 24
Finished Jan 10 12:28:43 PM PST 24
Peak memory 238628 kb
Host smart-f80ad58d-058b-4cf2-901e-25c139e43371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17735
35095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1773535095
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1034539612
Short name T14
Test name
Test status
Simulation time 1236072716 ps
CPU time 18.58 seconds
Started Jan 10 12:32:03 PM PST 24
Finished Jan 10 12:33:08 PM PST 24
Peak memory 270524 kb
Host smart-50535838-ed16-42ac-a6f2-9ac05d2b7f21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1034539612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1034539612
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1065248808
Short name T452
Test name
Test status
Simulation time 493995191 ps
CPU time 30.82 seconds
Started Jan 10 12:31:57 PM PST 24
Finished Jan 10 12:33:15 PM PST 24
Peak memory 248280 kb
Host smart-32b87837-e28a-4a1e-b010-9e8cb2026442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10652
48808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1065248808
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3389371483
Short name T554
Test name
Test status
Simulation time 16203438352 ps
CPU time 597.87 seconds
Started Jan 10 12:32:10 PM PST 24
Finished Jan 10 12:42:52 PM PST 24
Peak memory 264160 kb
Host smart-f89227bd-187c-4114-84c1-b1808b924b39
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389371483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3389371483
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1374863242
Short name T67
Test name
Test status
Simulation time 29148711892 ps
CPU time 1738.1 seconds
Started Jan 10 12:32:01 PM PST 24
Finished Jan 10 01:01:46 PM PST 24
Peak memory 281100 kb
Host smart-5b7a7363-330c-4494-9fa4-4293212bed59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374863242 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1374863242
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1720624962
Short name T464
Test name
Test status
Simulation time 524522316943 ps
CPU time 2316.55 seconds
Started Jan 10 12:29:35 PM PST 24
Finished Jan 10 01:08:39 PM PST 24
Peak memory 289532 kb
Host smart-a583050c-485c-4748-8b5d-0f47fbd8394d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720624962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1720624962
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.438146806
Short name T711
Test name
Test status
Simulation time 3729903744 ps
CPU time 219.82 seconds
Started Jan 10 12:30:25 PM PST 24
Finished Jan 10 12:34:46 PM PST 24
Peak memory 256564 kb
Host smart-593fe482-39a8-40df-86d5-c8af1b6857da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43814
6806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.438146806
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3916589096
Short name T530
Test name
Test status
Simulation time 3024098521 ps
CPU time 30.51 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 12:30:59 PM PST 24
Peak memory 248516 kb
Host smart-120df732-4b68-4fb1-b699-59a34e3cd3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39165
89096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3916589096
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1075896346
Short name T556
Test name
Test status
Simulation time 11854834562 ps
CPU time 1002.72 seconds
Started Jan 10 12:30:27 PM PST 24
Finished Jan 10 12:47:51 PM PST 24
Peak memory 272804 kb
Host smart-e62ee9b1-5b67-4698-a6e8-8032a4b731a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075896346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1075896346
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1332686267
Short name T6
Test name
Test status
Simulation time 47336576414 ps
CPU time 1004.55 seconds
Started Jan 10 12:29:55 PM PST 24
Finished Jan 10 12:47:18 PM PST 24
Peak memory 288508 kb
Host smart-58ddc498-fb2c-478f-8cbd-b7bea2d32b7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332686267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1332686267
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3102623268
Short name T709
Test name
Test status
Simulation time 57677865055 ps
CPU time 521.1 seconds
Started Jan 10 12:29:43 PM PST 24
Finished Jan 10 12:38:57 PM PST 24
Peak memory 247436 kb
Host smart-0c5fd219-e601-450d-b5e6-ea1026a9082f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102623268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3102623268
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1041048855
Short name T729
Test name
Test status
Simulation time 433402043 ps
CPU time 18.73 seconds
Started Jan 10 12:29:51 PM PST 24
Finished Jan 10 12:30:45 PM PST 24
Peak memory 248484 kb
Host smart-bfdef2ee-3e54-478b-a0df-f8b7045dabc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10410
48855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1041048855
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1317107729
Short name T123
Test name
Test status
Simulation time 10462505975 ps
CPU time 51.4 seconds
Started Jan 10 12:30:19 PM PST 24
Finished Jan 10 12:31:50 PM PST 24
Peak memory 254908 kb
Host smart-ee063fc7-3a45-4d2d-af0f-974e589c818a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13171
07729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1317107729
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.4236378343
Short name T486
Test name
Test status
Simulation time 60842424 ps
CPU time 4.64 seconds
Started Jan 10 12:30:23 PM PST 24
Finished Jan 10 12:31:09 PM PST 24
Peak memory 238740 kb
Host smart-db84359f-34e6-4780-9bc7-511a2c5bd3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42363
78343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.4236378343
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.508745732
Short name T431
Test name
Test status
Simulation time 233024385 ps
CPU time 15.48 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 12:30:43 PM PST 24
Peak memory 248452 kb
Host smart-ad44e12e-b821-4b78-b945-6b14378588f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50874
5732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.508745732
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.567117412
Short name T595
Test name
Test status
Simulation time 5465752934 ps
CPU time 75.09 seconds
Started Jan 10 12:30:07 PM PST 24
Finished Jan 10 12:32:03 PM PST 24
Peak memory 248540 kb
Host smart-bc1ba00d-983b-4c08-8bb3-f2662a51c808
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567117412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.567117412
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3499531007
Short name T3
Test name
Test status
Simulation time 45273790060 ps
CPU time 3873.02 seconds
Started Jan 10 12:29:54 PM PST 24
Finished Jan 10 01:35:06 PM PST 24
Peak memory 337400 kb
Host smart-6e908c52-106d-4cee-b430-6b87e003f842
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499531007 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3499531007
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2761082988
Short name T62
Test name
Test status
Simulation time 8327274451 ps
CPU time 676.06 seconds
Started Jan 10 12:29:56 PM PST 24
Finished Jan 10 12:41:51 PM PST 24
Peak memory 272628 kb
Host smart-06406216-e0e4-498b-ba36-cac8db6b6c2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761082988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2761082988
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3227932325
Short name T612
Test name
Test status
Simulation time 1850793229 ps
CPU time 133.08 seconds
Started Jan 10 12:30:00 PM PST 24
Finished Jan 10 12:32:54 PM PST 24
Peak memory 256076 kb
Host smart-fd8a0516-953d-4491-afce-fca25dba11e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32279
32325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3227932325
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1779119520
Short name T660
Test name
Test status
Simulation time 1232706006 ps
CPU time 16.19 seconds
Started Jan 10 12:29:57 PM PST 24
Finished Jan 10 12:30:54 PM PST 24
Peak memory 254796 kb
Host smart-1ef872fe-e512-4e76-9925-14d69c18a350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17791
19520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1779119520
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3941705899
Short name T351
Test name
Test status
Simulation time 95226267945 ps
CPU time 1441.2 seconds
Started Jan 10 12:30:00 PM PST 24
Finished Jan 10 12:54:44 PM PST 24
Peak memory 272380 kb
Host smart-5063083e-f572-4988-804c-7373a7d69baf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941705899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3941705899
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.850952699
Short name T50
Test name
Test status
Simulation time 95337420289 ps
CPU time 1360.91 seconds
Started Jan 10 12:29:46 PM PST 24
Finished Jan 10 12:53:01 PM PST 24
Peak memory 272196 kb
Host smart-b531264c-0b1f-46dc-b94e-2bbae3a5adbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850952699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.850952699
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.772709736
Short name T304
Test name
Test status
Simulation time 10618856625 ps
CPU time 104.33 seconds
Started Jan 10 12:29:47 PM PST 24
Finished Jan 10 12:32:05 PM PST 24
Peak memory 247192 kb
Host smart-b0419e7f-8548-4b63-bc48-52f40ea0071d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772709736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.772709736
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.108941647
Short name T467
Test name
Test status
Simulation time 20117909684 ps
CPU time 70.85 seconds
Started Jan 10 12:30:14 PM PST 24
Finished Jan 10 12:32:04 PM PST 24
Peak memory 248692 kb
Host smart-d93fb85a-47a5-463a-84e2-025932d7309f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10894
1647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.108941647
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.378845416
Short name T274
Test name
Test status
Simulation time 1427515403 ps
CPU time 39.93 seconds
Started Jan 10 12:30:16 PM PST 24
Finished Jan 10 12:31:35 PM PST 24
Peak memory 255292 kb
Host smart-58dd304c-f6e4-4b6a-a15f-4e23ac50ead6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37884
5416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.378845416
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.286013438
Short name T437
Test name
Test status
Simulation time 594297231 ps
CPU time 10.48 seconds
Started Jan 10 12:29:58 PM PST 24
Finished Jan 10 12:30:49 PM PST 24
Peak memory 248524 kb
Host smart-572b6ad4-9d61-4492-8d6f-1d65bbd62df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28601
3438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.286013438
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.769347619
Short name T731
Test name
Test status
Simulation time 5071100163 ps
CPU time 52.97 seconds
Started Jan 10 12:30:16 PM PST 24
Finished Jan 10 12:31:48 PM PST 24
Peak memory 248936 kb
Host smart-760d4611-6ff9-4efa-a034-1359ae4ec877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76934
7619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.769347619
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.76434329
Short name T450
Test name
Test status
Simulation time 102803008986 ps
CPU time 2814.22 seconds
Started Jan 10 12:30:21 PM PST 24
Finished Jan 10 01:17:57 PM PST 24
Peak memory 288572 kb
Host smart-a5f29dbc-3d5b-4fe9-adaa-1a4c140a47f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76434329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_hand
ler_stress_all.76434329
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.964024121
Short name T99
Test name
Test status
Simulation time 20775129356 ps
CPU time 1180.58 seconds
Started Jan 10 12:29:57 PM PST 24
Finished Jan 10 12:50:18 PM PST 24
Peak memory 282412 kb
Host smart-e3b037b8-7089-485c-a2a8-422475c961ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964024121 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.964024121
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3940812720
Short name T671
Test name
Test status
Simulation time 10519464412 ps
CPU time 974.09 seconds
Started Jan 10 12:29:55 PM PST 24
Finished Jan 10 12:46:48 PM PST 24
Peak memory 286464 kb
Host smart-52fff0cc-d166-4d49-ae6e-7ccae8d1a25a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940812720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3940812720
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1957602011
Short name T224
Test name
Test status
Simulation time 873803568 ps
CPU time 21.33 seconds
Started Jan 10 12:29:58 PM PST 24
Finished Jan 10 12:31:01 PM PST 24
Peak memory 248048 kb
Host smart-ebad8e82-dff7-4b11-8bed-72768ded44dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19576
02011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1957602011
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3464741378
Short name T549
Test name
Test status
Simulation time 328749204 ps
CPU time 29.67 seconds
Started Jan 10 12:29:53 PM PST 24
Finished Jan 10 12:31:00 PM PST 24
Peak memory 254160 kb
Host smart-ef709a1b-f2e1-4789-ad79-0aee499eb60d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34647
41378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3464741378
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.4017111002
Short name T667
Test name
Test status
Simulation time 103092869061 ps
CPU time 1535.65 seconds
Started Jan 10 12:29:55 PM PST 24
Finished Jan 10 12:56:09 PM PST 24
Peak memory 271932 kb
Host smart-251f6a65-2920-4f7b-ad2f-cdce0dc31521
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017111002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.4017111002
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1366795344
Short name T571
Test name
Test status
Simulation time 51558984457 ps
CPU time 1038.8 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 12:48:02 PM PST 24
Peak memory 272804 kb
Host smart-270d1fd4-f080-46a9-b09a-03a528e8bcbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366795344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1366795344
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.4045104590
Short name T524
Test name
Test status
Simulation time 9422460849 ps
CPU time 95.43 seconds
Started Jan 10 12:29:45 PM PST 24
Finished Jan 10 12:31:54 PM PST 24
Peak memory 247388 kb
Host smart-dea6a22c-4c38-4a2a-99bb-4f7452ed7cac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045104590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.4045104590
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2006871750
Short name T110
Test name
Test status
Simulation time 1435586461 ps
CPU time 21.1 seconds
Started Jan 10 12:29:53 PM PST 24
Finished Jan 10 12:30:50 PM PST 24
Peak memory 256700 kb
Host smart-d690696d-2680-4984-b6ac-c72478af7d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20068
71750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2006871750
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.41649009
Short name T211
Test name
Test status
Simulation time 99522014 ps
CPU time 2.77 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 12:30:46 PM PST 24
Peak memory 238340 kb
Host smart-0fdd5faf-965a-4ac7-8129-e4d1700cf3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41649
009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.41649009
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2574111
Short name T54
Test name
Test status
Simulation time 256791305 ps
CPU time 14.87 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 12:30:43 PM PST 24
Peak memory 255224 kb
Host smart-628bf86c-d3a4-467d-a0f5-4fd603494849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25741
11 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2574111
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1571836430
Short name T632
Test name
Test status
Simulation time 777968770 ps
CPU time 43.8 seconds
Started Jan 10 12:29:49 PM PST 24
Finished Jan 10 12:31:07 PM PST 24
Peak memory 248568 kb
Host smart-87901cdc-9360-435c-9a48-32b22bdda585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15718
36430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1571836430
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3133215442
Short name T58
Test name
Test status
Simulation time 9879850095 ps
CPU time 221.15 seconds
Started Jan 10 12:29:46 PM PST 24
Finished Jan 10 12:34:01 PM PST 24
Peak memory 254136 kb
Host smart-60e44ffc-79d5-4263-8adf-24c285694a80
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133215442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3133215442
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3452015727
Short name T43
Test name
Test status
Simulation time 251649556171 ps
CPU time 1969.29 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 01:03:17 PM PST 24
Peak memory 289628 kb
Host smart-5f59ac91-9bc6-45dd-ab1f-8d75573ef558
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452015727 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3452015727
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1112158225
Short name T299
Test name
Test status
Simulation time 34037877678 ps
CPU time 1086.75 seconds
Started Jan 10 12:29:49 PM PST 24
Finished Jan 10 12:48:29 PM PST 24
Peak memory 273060 kb
Host smart-22548638-3255-4748-baf3-2272fe59eb35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112158225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1112158225
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1910328812
Short name T381
Test name
Test status
Simulation time 1096994761 ps
CPU time 31.09 seconds
Started Jan 10 12:30:12 PM PST 24
Finished Jan 10 12:31:23 PM PST 24
Peak memory 255804 kb
Host smart-8c480eda-2514-407d-8b1f-a3f9e33bf4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19103
28812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1910328812
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2807994256
Short name T518
Test name
Test status
Simulation time 3005201651 ps
CPU time 42.6 seconds
Started Jan 10 12:30:12 PM PST 24
Finished Jan 10 12:31:35 PM PST 24
Peak memory 254200 kb
Host smart-f08dc21e-c4a0-4422-8589-9aaaf57daf46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28079
94256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2807994256
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.4138799095
Short name T352
Test name
Test status
Simulation time 104679957164 ps
CPU time 1423.99 seconds
Started Jan 10 12:29:55 PM PST 24
Finished Jan 10 12:54:17 PM PST 24
Peak memory 264868 kb
Host smart-b9e8c887-1960-4431-81bd-82799b385a52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138799095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.4138799095
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2832584706
Short name T219
Test name
Test status
Simulation time 10483902114 ps
CPU time 1001.04 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 12:47:09 PM PST 24
Peak memory 273052 kb
Host smart-e8bad0ef-1eb6-41da-a300-123b9ad9e6e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832584706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2832584706
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3132640459
Short name T329
Test name
Test status
Simulation time 8136399890 ps
CPU time 169.27 seconds
Started Jan 10 12:29:41 PM PST 24
Finished Jan 10 12:33:02 PM PST 24
Peak memory 248544 kb
Host smart-9436884e-0716-450a-ac22-e27ff3490957
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132640459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3132640459
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.869065094
Short name T581
Test name
Test status
Simulation time 1671333341 ps
CPU time 24.81 seconds
Started Jan 10 12:29:51 PM PST 24
Finished Jan 10 12:30:51 PM PST 24
Peak memory 248488 kb
Host smart-451f4497-09c6-4a2a-a70b-bd3e98b9ca6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86906
5094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.869065094
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3178784850
Short name T564
Test name
Test status
Simulation time 752831171 ps
CPU time 42.81 seconds
Started Jan 10 12:29:55 PM PST 24
Finished Jan 10 12:31:16 PM PST 24
Peak memory 254656 kb
Host smart-fd14f2c6-bda1-461e-b082-2d68f7fa430d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31787
84850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3178784850
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.474124453
Short name T470
Test name
Test status
Simulation time 1432584515 ps
CPU time 21.85 seconds
Started Jan 10 12:30:26 PM PST 24
Finished Jan 10 12:31:28 PM PST 24
Peak memory 253408 kb
Host smart-599e7baf-13ae-43f6-bc4d-efaa8a1b040b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47412
4453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.474124453
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1327109096
Short name T81
Test name
Test status
Simulation time 456851921 ps
CPU time 7.5 seconds
Started Jan 10 12:29:53 PM PST 24
Finished Jan 10 12:30:37 PM PST 24
Peak memory 240328 kb
Host smart-b47df209-e2a3-4400-b77c-ec64fb46eb34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13271
09096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1327109096
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3893547290
Short name T242
Test name
Test status
Simulation time 644284857342 ps
CPU time 9582.23 seconds
Started Jan 10 12:29:58 PM PST 24
Finished Jan 10 03:10:22 PM PST 24
Peak memory 363524 kb
Host smart-adeeafdc-c9a1-45a2-8964-7b39ef641fb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893547290 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3893547290
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2808698605
Short name T485
Test name
Test status
Simulation time 40192331176 ps
CPU time 2273.58 seconds
Started Jan 10 12:30:21 PM PST 24
Finished Jan 10 01:08:56 PM PST 24
Peak memory 288944 kb
Host smart-bd9dfec1-0cd0-49b7-9f94-4de1ea55408c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808698605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2808698605
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3640703016
Short name T542
Test name
Test status
Simulation time 2840818825 ps
CPU time 132.89 seconds
Started Jan 10 12:29:57 PM PST 24
Finished Jan 10 12:32:50 PM PST 24
Peak memory 256284 kb
Host smart-89b3c94b-954d-43f4-b9ba-f458d8965612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36407
03016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3640703016
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.340142837
Short name T451
Test name
Test status
Simulation time 228416756 ps
CPU time 18.17 seconds
Started Jan 10 12:29:54 PM PST 24
Finished Jan 10 12:30:50 PM PST 24
Peak memory 254676 kb
Host smart-12673256-fb5f-4c95-8412-a34fd4a38ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34014
2837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.340142837
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.312635583
Short name T421
Test name
Test status
Simulation time 23906982615 ps
CPU time 1179.71 seconds
Started Jan 10 12:30:26 PM PST 24
Finished Jan 10 12:50:47 PM PST 24
Peak memory 287736 kb
Host smart-1178ffe4-fc1f-4e93-a9a5-6fd5cdbcca4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312635583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.312635583
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.4064797322
Short name T335
Test name
Test status
Simulation time 2977145416 ps
CPU time 108.49 seconds
Started Jan 10 12:29:46 PM PST 24
Finished Jan 10 12:32:08 PM PST 24
Peak memory 247456 kb
Host smart-a03bbd10-d9a6-4c4e-9b24-caa850f327a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064797322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.4064797322
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2311841447
Short name T515
Test name
Test status
Simulation time 1123474439 ps
CPU time 24.78 seconds
Started Jan 10 12:29:44 PM PST 24
Finished Jan 10 12:30:42 PM PST 24
Peak memory 255132 kb
Host smart-b9a0abd7-e0c2-47b6-86ca-261e295faecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23118
41447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2311841447
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.4024379604
Short name T701
Test name
Test status
Simulation time 375381400 ps
CPU time 16.91 seconds
Started Jan 10 12:29:51 PM PST 24
Finished Jan 10 12:30:44 PM PST 24
Peak memory 254672 kb
Host smart-75c59f17-67fa-447f-948b-608063a99a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40243
79604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.4024379604
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3711936381
Short name T609
Test name
Test status
Simulation time 487158406 ps
CPU time 27.55 seconds
Started Jan 10 12:29:59 PM PST 24
Finished Jan 10 12:31:09 PM PST 24
Peak memory 248364 kb
Host smart-6d366dff-dacf-4634-b1aa-f6e1c4014176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37119
36381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3711936381
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.427473805
Short name T656
Test name
Test status
Simulation time 4076315239 ps
CPU time 270.15 seconds
Started Jan 10 12:29:57 PM PST 24
Finished Jan 10 12:35:06 PM PST 24
Peak memory 256736 kb
Host smart-a989c416-1a58-472d-9fef-e1067fe2766e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427473805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.427473805
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.437021785
Short name T216
Test name
Test status
Simulation time 18044389001 ps
CPU time 1063.58 seconds
Started Jan 10 12:30:24 PM PST 24
Finished Jan 10 12:48:48 PM PST 24
Peak memory 271880 kb
Host smart-a28c6287-47e1-4954-8276-c3403aba6c59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437021785 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.437021785
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.326373894
Short name T66
Test name
Test status
Simulation time 20402990279 ps
CPU time 1269.57 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 12:51:52 PM PST 24
Peak memory 289440 kb
Host smart-39b9e3e5-f78a-49e0-a96d-4b594279d0c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326373894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.326373894
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2124543758
Short name T639
Test name
Test status
Simulation time 256598885 ps
CPU time 11.7 seconds
Started Jan 10 12:30:00 PM PST 24
Finished Jan 10 12:30:53 PM PST 24
Peak memory 247864 kb
Host smart-0ecd64df-eb22-4073-9e28-6ef0c2cc0904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21245
43758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2124543758
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2321991443
Short name T444
Test name
Test status
Simulation time 1146031549 ps
CPU time 32 seconds
Started Jan 10 12:29:57 PM PST 24
Finished Jan 10 12:31:09 PM PST 24
Peak memory 255880 kb
Host smart-643f09a4-5c99-464a-bf40-48ee4870cecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23219
91443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2321991443
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.4032574816
Short name T343
Test name
Test status
Simulation time 402714158373 ps
CPU time 2282.69 seconds
Started Jan 10 12:30:00 PM PST 24
Finished Jan 10 01:08:44 PM PST 24
Peak memory 273204 kb
Host smart-5f5d4239-b884-4e2e-9044-6e5c42085fd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032574816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.4032574816
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.850031748
Short name T88
Test name
Test status
Simulation time 15703836790 ps
CPU time 931.34 seconds
Started Jan 10 12:30:05 PM PST 24
Finished Jan 10 12:46:18 PM PST 24
Peak memory 282632 kb
Host smart-9e867749-756c-45ae-82e1-072aa059f63b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850031748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.850031748
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.4281727587
Short name T52
Test name
Test status
Simulation time 409463667 ps
CPU time 24.67 seconds
Started Jan 10 12:30:21 PM PST 24
Finished Jan 10 12:31:25 PM PST 24
Peak memory 255380 kb
Host smart-e0210471-d821-46e7-a15c-bb7e52253ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42817
27587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.4281727587
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.768328104
Short name T693
Test name
Test status
Simulation time 1868530333 ps
CPU time 50.58 seconds
Started Jan 10 12:29:59 PM PST 24
Finished Jan 10 12:31:32 PM PST 24
Peak memory 255276 kb
Host smart-4c697a7c-1375-4f95-a48f-16ebffa3cb90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76832
8104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.768328104
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2874549296
Short name T264
Test name
Test status
Simulation time 144846842 ps
CPU time 9.15 seconds
Started Jan 10 12:30:11 PM PST 24
Finished Jan 10 12:31:05 PM PST 24
Peak memory 246764 kb
Host smart-e5a5cf03-e2f7-472e-91b5-f4ca47d5db4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28745
49296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2874549296
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3303568179
Short name T24
Test name
Test status
Simulation time 181493190 ps
CPU time 17.66 seconds
Started Jan 10 12:29:45 PM PST 24
Finished Jan 10 12:30:36 PM PST 24
Peak memory 248572 kb
Host smart-4aa03d29-d7a6-463f-9b70-51e2d078bfb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33035
68179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3303568179
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3329412007
Short name T291
Test name
Test status
Simulation time 67934867603 ps
CPU time 2370.89 seconds
Started Jan 10 12:29:53 PM PST 24
Finished Jan 10 01:10:02 PM PST 24
Peak memory 288560 kb
Host smart-f1d17ac6-d802-4780-9818-995884508678
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329412007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3329412007
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.3658370873
Short name T433
Test name
Test status
Simulation time 54511488554 ps
CPU time 2751.44 seconds
Started Jan 10 12:29:56 PM PST 24
Finished Jan 10 01:16:27 PM PST 24
Peak memory 321756 kb
Host smart-79c632aa-f2ad-41f8-95b2-3b04ba9bfb37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658370873 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3658370873
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3742945944
Short name T666
Test name
Test status
Simulation time 39588936347 ps
CPU time 2036.64 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 01:04:40 PM PST 24
Peak memory 272880 kb
Host smart-c768bb3d-a2e2-47bd-a67e-7974c02bb6f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742945944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3742945944
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2142758947
Short name T405
Test name
Test status
Simulation time 397211133 ps
CPU time 10.09 seconds
Started Jan 10 12:29:58 PM PST 24
Finished Jan 10 12:30:48 PM PST 24
Peak memory 253400 kb
Host smart-a2de12eb-9bae-4da9-8bba-94c86a4adbd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21427
58947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2142758947
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1496074120
Short name T468
Test name
Test status
Simulation time 816011303 ps
CPU time 11.49 seconds
Started Jan 10 12:29:58 PM PST 24
Finished Jan 10 12:30:50 PM PST 24
Peak memory 252212 kb
Host smart-e7a59b0d-72f1-4184-b2ed-8148970d521d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14960
74120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1496074120
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.895111012
Short name T354
Test name
Test status
Simulation time 33739675228 ps
CPU time 1238.93 seconds
Started Jan 10 12:30:08 PM PST 24
Finished Jan 10 12:51:27 PM PST 24
Peak memory 288904 kb
Host smart-2758dfc6-dcf5-456a-bb91-40cb18664825
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895111012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.895111012
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.254919371
Short name T692
Test name
Test status
Simulation time 47619550017 ps
CPU time 969.31 seconds
Started Jan 10 12:30:05 PM PST 24
Finished Jan 10 12:46:56 PM PST 24
Peak memory 272796 kb
Host smart-57ecb134-b364-4eca-b1dc-990a968295c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254919371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.254919371
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2640425531
Short name T311
Test name
Test status
Simulation time 10202063869 ps
CPU time 411.64 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:37:36 PM PST 24
Peak memory 247532 kb
Host smart-81f1858b-7151-4323-b44a-e7f8811e501d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640425531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2640425531
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.282399493
Short name T454
Test name
Test status
Simulation time 253719750 ps
CPU time 17.89 seconds
Started Jan 10 12:30:19 PM PST 24
Finished Jan 10 12:31:16 PM PST 24
Peak memory 248512 kb
Host smart-a7f31907-fefe-41e6-80d8-91e24fa96bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28239
9493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.282399493
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1643007981
Short name T41
Test name
Test status
Simulation time 223040660 ps
CPU time 15.38 seconds
Started Jan 10 12:30:05 PM PST 24
Finished Jan 10 12:31:02 PM PST 24
Peak memory 254916 kb
Host smart-e8a95ac1-eeef-4c99-b63b-0e9ef4bae994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16430
07981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1643007981
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1211311437
Short name T449
Test name
Test status
Simulation time 2383914890 ps
CPU time 36.12 seconds
Started Jan 10 12:29:56 PM PST 24
Finished Jan 10 12:31:10 PM PST 24
Peak memory 248492 kb
Host smart-5c713469-0e5b-4914-b5c9-4bc94c07d98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12113
11437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1211311437
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3083886861
Short name T380
Test name
Test status
Simulation time 781266433 ps
CPU time 13.03 seconds
Started Jan 10 12:29:53 PM PST 24
Finished Jan 10 12:30:43 PM PST 24
Peak memory 248404 kb
Host smart-d5889971-790b-4f19-829a-c34f11926fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30838
86861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3083886861
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3232510473
Short name T249
Test name
Test status
Simulation time 27543800048 ps
CPU time 1319.53 seconds
Started Jan 10 12:29:53 PM PST 24
Finished Jan 10 12:52:30 PM PST 24
Peak memory 273124 kb
Host smart-0ac5cf45-8a79-4b99-9fbe-1b2f6e894383
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232510473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3232510473
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2723500431
Short name T27
Test name
Test status
Simulation time 56724510104 ps
CPU time 5384.54 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 02:00:13 PM PST 24
Peak memory 338464 kb
Host smart-ae56b4a9-a046-4058-92f7-b69686935d60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723500431 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2723500431
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1861567193
Short name T409
Test name
Test status
Simulation time 6509936258 ps
CPU time 561.7 seconds
Started Jan 10 12:30:05 PM PST 24
Finished Jan 10 12:40:08 PM PST 24
Peak memory 264996 kb
Host smart-9188745f-7a6a-442a-b529-9b9f8b4d05f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861567193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1861567193
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.22644264
Short name T669
Test name
Test status
Simulation time 91922830 ps
CPU time 3.68 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 12:30:46 PM PST 24
Peak memory 240048 kb
Host smart-c526fcda-4723-491d-a685-cd813063c2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22644
264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.22644264
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.743115775
Short name T628
Test name
Test status
Simulation time 413175635 ps
CPU time 25.72 seconds
Started Jan 10 12:30:05 PM PST 24
Finished Jan 10 12:31:12 PM PST 24
Peak memory 255512 kb
Host smart-ceb2582a-69e3-4ed3-846c-04cdfd863e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74311
5775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.743115775
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.895653101
Short name T303
Test name
Test status
Simulation time 15963574559 ps
CPU time 958.55 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:46:43 PM PST 24
Peak memory 283136 kb
Host smart-c51b978e-8f36-4dad-b422-641ae2d546b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895653101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.895653101
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.637984901
Short name T213
Test name
Test status
Simulation time 67754536079 ps
CPU time 2066.6 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 01:05:11 PM PST 24
Peak memory 284156 kb
Host smart-edc06eb9-d2fd-4517-b36a-2fdbfdf1cd18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637984901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.637984901
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2355994564
Short name T420
Test name
Test status
Simulation time 268371974 ps
CPU time 7.84 seconds
Started Jan 10 12:29:55 PM PST 24
Finished Jan 10 12:30:42 PM PST 24
Peak memory 248616 kb
Host smart-984c7c28-a970-4eef-b83f-228394a40a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23559
94564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2355994564
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.65979195
Short name T111
Test name
Test status
Simulation time 188524555 ps
CPU time 11.32 seconds
Started Jan 10 12:30:02 PM PST 24
Finished Jan 10 12:30:55 PM PST 24
Peak memory 251444 kb
Host smart-f86a2759-eb50-42d4-8518-9aa8c72d8132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65979
195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.65979195
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2229218987
Short name T655
Test name
Test status
Simulation time 357996750 ps
CPU time 10.5 seconds
Started Jan 10 12:30:10 PM PST 24
Finished Jan 10 12:31:01 PM PST 24
Peak memory 248484 kb
Host smart-84348891-4383-47d2-bf4c-3cd8ad53917e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22292
18987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2229218987
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2114559989
Short name T638
Test name
Test status
Simulation time 2174796714 ps
CPU time 164.55 seconds
Started Jan 10 12:29:54 PM PST 24
Finished Jan 10 12:33:17 PM PST 24
Peak memory 256796 kb
Host smart-0d08382c-6845-427e-8c8b-3dc43a707392
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114559989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2114559989
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.615932029
Short name T236
Test name
Test status
Simulation time 98427696330 ps
CPU time 3873.56 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 01:35:17 PM PST 24
Peak memory 316780 kb
Host smart-fc812a4c-d3c2-4335-855e-b2d2f88c3eac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615932029 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.615932029
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.18500159
Short name T733
Test name
Test status
Simulation time 7121858951 ps
CPU time 607.06 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:40:51 PM PST 24
Peak memory 264912 kb
Host smart-2b645e3f-050e-489a-bcf9-644203118dc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18500159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.18500159
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2945859053
Short name T573
Test name
Test status
Simulation time 2243137290 ps
CPU time 127.3 seconds
Started Jan 10 12:29:58 PM PST 24
Finished Jan 10 12:32:47 PM PST 24
Peak memory 249684 kb
Host smart-54be50c4-6705-48a3-a7b6-5b1cf0e84674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29458
59053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2945859053
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3083222740
Short name T342
Test name
Test status
Simulation time 48646521012 ps
CPU time 2428.48 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 01:11:11 PM PST 24
Peak memory 281480 kb
Host smart-f540ff0c-657a-4624-addf-b9223527bf9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083222740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3083222740
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2170114886
Short name T641
Test name
Test status
Simulation time 131629882703 ps
CPU time 1632.03 seconds
Started Jan 10 12:30:00 PM PST 24
Finished Jan 10 12:57:55 PM PST 24
Peak memory 272044 kb
Host smart-9267d427-5425-4433-85df-b8fed97039dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170114886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2170114886
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3681533703
Short name T338
Test name
Test status
Simulation time 130104296154 ps
CPU time 505.79 seconds
Started Jan 10 12:30:23 PM PST 24
Finished Jan 10 12:39:29 PM PST 24
Peak memory 248588 kb
Host smart-b7f0375e-7fa1-4044-9dc3-1fe6c0dcd813
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681533703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3681533703
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1964004091
Short name T378
Test name
Test status
Simulation time 1163502664 ps
CPU time 65.92 seconds
Started Jan 10 12:30:02 PM PST 24
Finished Jan 10 12:31:50 PM PST 24
Peak memory 248600 kb
Host smart-e6a97655-5e88-42f1-839f-a45857c73ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19640
04091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1964004091
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3853875363
Short name T40
Test name
Test status
Simulation time 340710122 ps
CPU time 29.64 seconds
Started Jan 10 12:29:48 PM PST 24
Finished Jan 10 12:30:51 PM PST 24
Peak memory 254084 kb
Host smart-bd46f40b-2dd2-473d-a8da-6f2f097dea8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38538
75363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3853875363
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3637695128
Short name T717
Test name
Test status
Simulation time 38081137 ps
CPU time 4.22 seconds
Started Jan 10 12:29:55 PM PST 24
Finished Jan 10 12:30:38 PM PST 24
Peak memory 238568 kb
Host smart-2f8c5f20-7a3b-490b-bb0d-1c57a4c35b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36376
95128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3637695128
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2545112306
Short name T384
Test name
Test status
Simulation time 43733183 ps
CPU time 3.78 seconds
Started Jan 10 12:29:57 PM PST 24
Finished Jan 10 12:30:41 PM PST 24
Peak memory 240372 kb
Host smart-461bcfbf-929f-4560-9fc4-99a681a37ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25451
12306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2545112306
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.712352428
Short name T646
Test name
Test status
Simulation time 90572980238 ps
CPU time 2606.73 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 01:14:10 PM PST 24
Peak memory 289268 kb
Host smart-2cf7767f-fd8b-4a27-9439-d2484dc89315
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712352428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.712352428
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3048827658
Short name T507
Test name
Test status
Simulation time 109112797202 ps
CPU time 1472.47 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:55:17 PM PST 24
Peak memory 272712 kb
Host smart-09e9507b-e1fb-483b-8579-1bc5a356c155
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048827658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3048827658
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2447180403
Short name T376
Test name
Test status
Simulation time 920302361 ps
CPU time 37.81 seconds
Started Jan 10 12:30:27 PM PST 24
Finished Jan 10 12:31:46 PM PST 24
Peak memory 248112 kb
Host smart-589df3d8-26d1-49c5-93e2-b0eeeed2cbe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24471
80403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2447180403
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2595651823
Short name T526
Test name
Test status
Simulation time 3517885886 ps
CPU time 47.4 seconds
Started Jan 10 12:30:14 PM PST 24
Finished Jan 10 12:31:41 PM PST 24
Peak memory 254924 kb
Host smart-35fcd8ac-99a8-4c1a-a9fc-32a71532e251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25956
51823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2595651823
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1623991257
Short name T621
Test name
Test status
Simulation time 151253637475 ps
CPU time 2109.03 seconds
Started Jan 10 12:30:14 PM PST 24
Finished Jan 10 01:06:03 PM PST 24
Peak memory 287212 kb
Host smart-6e6c57da-ed7d-4be3-b127-666c49116815
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623991257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1623991257
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3014942771
Short name T714
Test name
Test status
Simulation time 294894565124 ps
CPU time 2487.04 seconds
Started Jan 10 12:30:21 PM PST 24
Finished Jan 10 01:12:29 PM PST 24
Peak memory 281456 kb
Host smart-f49c447d-828b-491e-b09e-7a2056a75ed0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014942771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3014942771
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1272681306
Short name T341
Test name
Test status
Simulation time 22268594827 ps
CPU time 404.85 seconds
Started Jan 10 12:29:53 PM PST 24
Finished Jan 10 12:37:15 PM PST 24
Peak memory 247136 kb
Host smart-7ffbbff8-e2db-4418-8737-86386af2c97a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272681306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1272681306
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2733112387
Short name T275
Test name
Test status
Simulation time 1955289091 ps
CPU time 35.49 seconds
Started Jan 10 12:29:56 PM PST 24
Finished Jan 10 12:31:09 PM PST 24
Peak memory 255176 kb
Host smart-4deb7e9a-2353-4db8-8bcd-6bf9ae7e4fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27331
12387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2733112387
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3523605114
Short name T478
Test name
Test status
Simulation time 417170181 ps
CPU time 5.21 seconds
Started Jan 10 12:30:02 PM PST 24
Finished Jan 10 12:30:49 PM PST 24
Peak memory 253020 kb
Host smart-0e8108b8-175c-405c-8749-c800d8f7e56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35236
05114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3523605114
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2324413643
Short name T527
Test name
Test status
Simulation time 467762586 ps
CPU time 26.84 seconds
Started Jan 10 12:30:15 PM PST 24
Finished Jan 10 12:31:21 PM PST 24
Peak memory 255388 kb
Host smart-6046e628-4994-410e-a2bf-681d9347f4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23244
13643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2324413643
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1232129420
Short name T72
Test name
Test status
Simulation time 2253488749 ps
CPU time 60.62 seconds
Started Jan 10 12:30:27 PM PST 24
Finished Jan 10 12:32:09 PM PST 24
Peak memory 248536 kb
Host smart-14494825-6f62-4866-bd1f-338713d27f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12321
29420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1232129420
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3095137899
Short name T256
Test name
Test status
Simulation time 138446709862 ps
CPU time 2068.93 seconds
Started Jan 10 12:30:26 PM PST 24
Finished Jan 10 01:05:36 PM PST 24
Peak memory 273172 kb
Host smart-56c3fcf8-3955-4cba-b7c0-028f6c44a784
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095137899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3095137899
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3453483358
Short name T279
Test name
Test status
Simulation time 10214737416 ps
CPU time 539.54 seconds
Started Jan 10 12:30:06 PM PST 24
Finished Jan 10 12:39:47 PM PST 24
Peak memory 265116 kb
Host smart-8134b78c-782f-4663-ae36-857190bb1a20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453483358 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3453483358
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3210750848
Short name T191
Test name
Test status
Simulation time 43256119 ps
CPU time 3.16 seconds
Started Jan 10 12:32:09 PM PST 24
Finished Jan 10 12:32:56 PM PST 24
Peak memory 248340 kb
Host smart-d80f31c9-a1bc-49fe-8524-8a712c0a6391
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3210750848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3210750848
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2823699226
Short name T547
Test name
Test status
Simulation time 108284857496 ps
CPU time 1380.54 seconds
Started Jan 10 12:31:46 PM PST 24
Finished Jan 10 12:55:35 PM PST 24
Peak memory 271304 kb
Host smart-bf2de313-6460-450a-bccf-f3db700472ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823699226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2823699226
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3919603012
Short name T643
Test name
Test status
Simulation time 336386587 ps
CPU time 9.86 seconds
Started Jan 10 12:32:11 PM PST 24
Finished Jan 10 12:33:04 PM PST 24
Peak memory 248100 kb
Host smart-9920e0e4-5b99-4a1e-a710-11d3990e7715
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3919603012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3919603012
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3752645513
Short name T428
Test name
Test status
Simulation time 6837486505 ps
CPU time 131.74 seconds
Started Jan 10 12:32:18 PM PST 24
Finished Jan 10 12:35:10 PM PST 24
Peak memory 255412 kb
Host smart-90ce8a9c-914e-4105-b7e3-7e6e021325db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37526
45513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3752645513
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3814603719
Short name T488
Test name
Test status
Simulation time 545673135 ps
CPU time 15.69 seconds
Started Jan 10 12:32:01 PM PST 24
Finished Jan 10 12:33:03 PM PST 24
Peak memory 253520 kb
Host smart-6819d5dc-4f27-4075-9f88-4d26897396e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38146
03719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3814603719
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.716773606
Short name T633
Test name
Test status
Simulation time 291938972223 ps
CPU time 1226.7 seconds
Started Jan 10 12:32:17 PM PST 24
Finished Jan 10 12:53:24 PM PST 24
Peak memory 282396 kb
Host smart-1bbe30f0-d9b6-4fbd-97e4-fb4858e2f8ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716773606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.716773606
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1187297082
Short name T608
Test name
Test status
Simulation time 23136256089 ps
CPU time 1513.41 seconds
Started Jan 10 12:28:24 PM PST 24
Finished Jan 10 12:53:49 PM PST 24
Peak memory 272736 kb
Host smart-903a3f75-979d-400b-a5bc-5a9107ba552c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187297082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1187297082
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.958000076
Short name T289
Test name
Test status
Simulation time 13479768690 ps
CPU time 104.84 seconds
Started Jan 10 12:32:03 PM PST 24
Finished Jan 10 12:34:33 PM PST 24
Peak memory 247068 kb
Host smart-fd05e686-4ba9-4188-bf5b-cbf997974ccf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958000076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.958000076
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3733101744
Short name T417
Test name
Test status
Simulation time 697939017 ps
CPU time 34.83 seconds
Started Jan 10 12:28:17 PM PST 24
Finished Jan 10 12:29:05 PM PST 24
Peak memory 255092 kb
Host smart-bc6a591e-4057-4263-8c04-25e4ac7c3733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37331
01744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3733101744
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1618901991
Short name T686
Test name
Test status
Simulation time 6326259562 ps
CPU time 45.22 seconds
Started Jan 10 12:32:03 PM PST 24
Finished Jan 10 12:33:34 PM PST 24
Peak memory 254732 kb
Host smart-a5d39f61-6fa8-474f-a05d-c6a6c3551b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16189
01991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1618901991
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3638573811
Short name T430
Test name
Test status
Simulation time 791547371 ps
CPU time 24.4 seconds
Started Jan 10 12:32:03 PM PST 24
Finished Jan 10 12:33:13 PM PST 24
Peak memory 254824 kb
Host smart-aa73192e-4692-4c24-931c-69d7a69fafcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36385
73811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3638573811
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2342738696
Short name T73
Test name
Test status
Simulation time 578584549 ps
CPU time 4.33 seconds
Started Jan 10 12:32:27 PM PST 24
Finished Jan 10 12:33:07 PM PST 24
Peak memory 239868 kb
Host smart-ea54fa51-1cc8-469e-a626-a83299fdc615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23427
38696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2342738696
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3547682691
Short name T245
Test name
Test status
Simulation time 151050118187 ps
CPU time 1290.6 seconds
Started Jan 10 12:31:47 PM PST 24
Finished Jan 10 12:54:06 PM PST 24
Peak memory 285816 kb
Host smart-6c4ca421-3ba4-4fca-a7a3-1a25b7b91c75
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547682691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3547682691
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.3386325297
Short name T89
Test name
Test status
Simulation time 339295570385 ps
CPU time 6836.23 seconds
Started Jan 10 12:32:13 PM PST 24
Finished Jan 10 02:26:52 PM PST 24
Peak memory 354376 kb
Host smart-c183647c-9568-4739-9999-bd406074f193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386325297 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.3386325297
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1295674696
Short name T205
Test name
Test status
Simulation time 356156285 ps
CPU time 2.87 seconds
Started Jan 10 12:28:34 PM PST 24
Finished Jan 10 12:28:49 PM PST 24
Peak memory 248660 kb
Host smart-7b9bd701-6b27-4bf9-a2d1-7f7d59479a5d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1295674696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1295674696
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2923448948
Short name T508
Test name
Test status
Simulation time 133701052034 ps
CPU time 1751.48 seconds
Started Jan 10 12:31:56 PM PST 24
Finished Jan 10 01:01:54 PM PST 24
Peak memory 280860 kb
Host smart-ee96d1e2-0ea4-414d-b58c-00ec43b5f4d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923448948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2923448948
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.746810198
Short name T412
Test name
Test status
Simulation time 2859263581 ps
CPU time 31.36 seconds
Started Jan 10 12:34:42 PM PST 24
Finished Jan 10 12:35:55 PM PST 24
Peak memory 239912 kb
Host smart-9cc60906-626a-40f1-850b-c518174b3a0c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=746810198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.746810198
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2367504054
Short name T625
Test name
Test status
Simulation time 1155822498 ps
CPU time 85.56 seconds
Started Jan 10 12:31:10 PM PST 24
Finished Jan 10 12:33:21 PM PST 24
Peak memory 255680 kb
Host smart-f0cb23d2-f038-4482-a364-802dc70812ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23675
04054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2367504054
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.4090923971
Short name T419
Test name
Test status
Simulation time 452625040 ps
CPU time 7.37 seconds
Started Jan 10 12:32:19 PM PST 24
Finished Jan 10 12:33:06 PM PST 24
Peak memory 239612 kb
Host smart-d2f6deb0-5681-43b8-a5e5-3b4aeca7a295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40909
23971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.4090923971
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.632459154
Short name T21
Test name
Test status
Simulation time 15545897062 ps
CPU time 1100.66 seconds
Started Jan 10 12:31:49 PM PST 24
Finished Jan 10 12:50:57 PM PST 24
Peak memory 272408 kb
Host smart-a7c83b20-4ae6-49df-a39b-a6d38ddd7aea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632459154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.632459154
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1919573746
Short name T116
Test name
Test status
Simulation time 33593460007 ps
CPU time 1274.39 seconds
Started Jan 10 12:34:41 PM PST 24
Finished Jan 10 12:56:37 PM PST 24
Peak memory 288140 kb
Host smart-d958efe1-0793-454c-a8e0-05ca305bd094
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919573746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1919573746
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.977020191
Short name T324
Test name
Test status
Simulation time 8796257920 ps
CPU time 175.89 seconds
Started Jan 10 12:31:56 PM PST 24
Finished Jan 10 12:35:38 PM PST 24
Peak memory 246756 kb
Host smart-2d69aee7-080c-4fe2-bc1b-c694150bd362
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977020191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.977020191
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3494466525
Short name T429
Test name
Test status
Simulation time 282099796 ps
CPU time 16.37 seconds
Started Jan 10 12:32:09 PM PST 24
Finished Jan 10 12:33:10 PM PST 24
Peak memory 248116 kb
Host smart-dd1e7776-fdde-4b61-80f0-aba6caf09752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34944
66525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3494466525
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2557844533
Short name T59
Test name
Test status
Simulation time 1666818947 ps
CPU time 17.85 seconds
Started Jan 10 12:31:47 PM PST 24
Finished Jan 10 12:32:53 PM PST 24
Peak memory 254144 kb
Host smart-bc5331f1-7ff0-4da8-85fd-0228b99e142f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25578
44533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2557844533
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1449144056
Short name T251
Test name
Test status
Simulation time 196315577 ps
CPU time 20.66 seconds
Started Jan 10 12:31:10 PM PST 24
Finished Jan 10 12:32:17 PM PST 24
Peak memory 254284 kb
Host smart-c289fa21-f27a-4937-990b-c600d84a1622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14491
44056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1449144056
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4113413686
Short name T370
Test name
Test status
Simulation time 1028347695 ps
CPU time 25.21 seconds
Started Jan 10 12:32:09 PM PST 24
Finished Jan 10 12:33:18 PM PST 24
Peak memory 254600 kb
Host smart-8bc0defc-9488-4047-bddd-f653b3253d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41134
13686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4113413686
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.4248610330
Short name T400
Test name
Test status
Simulation time 128994049951 ps
CPU time 1902.03 seconds
Started Jan 10 12:31:33 PM PST 24
Finished Jan 10 01:04:06 PM PST 24
Peak memory 280448 kb
Host smart-a11258eb-73b6-49d4-b54f-0c7039379e35
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248610330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.4248610330
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.230621769
Short name T240
Test name
Test status
Simulation time 45314758023 ps
CPU time 2411.82 seconds
Started Jan 10 12:34:39 PM PST 24
Finished Jan 10 01:15:32 PM PST 24
Peak memory 297464 kb
Host smart-f5a937f6-2990-4e90-8de2-4cef68453248
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230621769 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.230621769
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2829398015
Short name T207
Test name
Test status
Simulation time 41273691 ps
CPU time 2.14 seconds
Started Jan 10 12:30:55 PM PST 24
Finished Jan 10 12:31:43 PM PST 24
Peak memory 248312 kb
Host smart-4398f070-97d7-451b-bbfc-86789e98929e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2829398015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2829398015
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.611840593
Short name T677
Test name
Test status
Simulation time 40020239317 ps
CPU time 992.62 seconds
Started Jan 10 12:31:44 PM PST 24
Finished Jan 10 12:49:07 PM PST 24
Peak memory 280968 kb
Host smart-a7704c39-e192-43b9-b98d-e44768d63631
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611840593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.611840593
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1893818438
Short name T434
Test name
Test status
Simulation time 563879021 ps
CPU time 9.49 seconds
Started Jan 10 12:28:28 PM PST 24
Finished Jan 10 12:28:48 PM PST 24
Peak memory 240484 kb
Host smart-cb99a307-8f6c-4a5f-a63f-0cbc512590b7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1893818438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1893818438
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3274955787
Short name T511
Test name
Test status
Simulation time 455775165 ps
CPU time 25.95 seconds
Started Jan 10 12:28:41 PM PST 24
Finished Jan 10 12:29:21 PM PST 24
Peak memory 255220 kb
Host smart-d62ebf9b-3fc8-4d4e-a25d-b32b2d881d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32749
55787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3274955787
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2181617589
Short name T416
Test name
Test status
Simulation time 630070490 ps
CPU time 30.92 seconds
Started Jan 10 12:31:25 PM PST 24
Finished Jan 10 12:32:45 PM PST 24
Peak memory 251256 kb
Host smart-7938944d-2205-4951-ba01-dfdffeb2d06e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21816
17589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2181617589
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3620962045
Short name T317
Test name
Test status
Simulation time 411282502251 ps
CPU time 2247.27 seconds
Started Jan 10 12:31:56 PM PST 24
Finished Jan 10 01:10:10 PM PST 24
Peak memory 288448 kb
Host smart-123fa2c5-b8bc-4247-98cf-8ef82fc2427b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620962045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3620962045
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.118826377
Short name T734
Test name
Test status
Simulation time 23710831870 ps
CPU time 1497.17 seconds
Started Jan 10 12:28:32 PM PST 24
Finished Jan 10 12:53:41 PM PST 24
Peak memory 270832 kb
Host smart-3b4fb877-d1a9-4ef9-8bed-edde8d7accae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118826377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.118826377
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.4159928849
Short name T432
Test name
Test status
Simulation time 225755883 ps
CPU time 13.73 seconds
Started Jan 10 12:28:38 PM PST 24
Finished Jan 10 12:29:04 PM PST 24
Peak memory 253200 kb
Host smart-1c6a1420-45d5-49d6-9bce-5e86f2693f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41599
28849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.4159928849
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2896852644
Short name T562
Test name
Test status
Simulation time 338449810 ps
CPU time 14.07 seconds
Started Jan 10 12:28:24 PM PST 24
Finished Jan 10 12:28:49 PM PST 24
Peak memory 255248 kb
Host smart-5d34aa18-83ce-42c1-b8a1-15dbd9b27b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28968
52644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2896852644
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1787808797
Short name T125
Test name
Test status
Simulation time 3123954586 ps
CPU time 47.22 seconds
Started Jan 10 12:31:51 PM PST 24
Finished Jan 10 12:33:24 PM PST 24
Peak memory 248336 kb
Host smart-01fb6459-c827-458d-a1e9-fe4fee62dd0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17878
08797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1787808797
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2881558178
Short name T596
Test name
Test status
Simulation time 479374188 ps
CPU time 4.18 seconds
Started Jan 10 12:34:39 PM PST 24
Finished Jan 10 12:35:24 PM PST 24
Peak memory 239928 kb
Host smart-abecf23e-17f0-45b5-9646-0b509053aeec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28815
58178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2881558178
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1903239001
Short name T694
Test name
Test status
Simulation time 15636240893 ps
CPU time 1229.87 seconds
Started Jan 10 12:31:25 PM PST 24
Finished Jan 10 12:52:44 PM PST 24
Peak memory 283868 kb
Host smart-040ea288-dd57-495b-91fe-6043be4851b9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903239001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1903239001
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1333295480
Short name T198
Test name
Test status
Simulation time 30921155 ps
CPU time 3.32 seconds
Started Jan 10 12:32:03 PM PST 24
Finished Jan 10 12:32:52 PM PST 24
Peak memory 248416 kb
Host smart-ea2045bb-699f-4fad-b248-cc84daa77095
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1333295480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1333295480
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1479882167
Short name T296
Test name
Test status
Simulation time 33057645429 ps
CPU time 1942.73 seconds
Started Jan 10 12:32:27 PM PST 24
Finished Jan 10 01:05:26 PM PST 24
Peak memory 284000 kb
Host smart-2ef274c8-501c-4015-b22a-5dbb7d6f55a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479882167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1479882167
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3878505814
Short name T673
Test name
Test status
Simulation time 174219334 ps
CPU time 9.56 seconds
Started Jan 10 12:32:14 PM PST 24
Finished Jan 10 12:33:05 PM PST 24
Peak memory 239892 kb
Host smart-a0adbf78-6ee8-4a77-9276-66c89b9c74dd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3878505814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3878505814
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2881975747
Short name T283
Test name
Test status
Simulation time 5213525210 ps
CPU time 128.34 seconds
Started Jan 10 12:30:55 PM PST 24
Finished Jan 10 12:33:50 PM PST 24
Peak memory 255624 kb
Host smart-935d6e1d-8619-4d4a-b1a5-79ad1c5974a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28819
75747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2881975747
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.760337088
Short name T447
Test name
Test status
Simulation time 628308283 ps
CPU time 8.53 seconds
Started Jan 10 12:32:27 PM PST 24
Finished Jan 10 12:33:12 PM PST 24
Peak memory 254572 kb
Host smart-dadf1faa-898b-4816-bb9f-f26761e3c166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76033
7088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.760337088
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.174403221
Short name T649
Test name
Test status
Simulation time 106760159191 ps
CPU time 1150.13 seconds
Started Jan 10 12:32:14 PM PST 24
Finished Jan 10 12:52:06 PM PST 24
Peak memory 288680 kb
Host smart-d01d9ad1-3524-4b28-87a3-1945dc0b3ac2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174403221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.174403221
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2701310141
Short name T722
Test name
Test status
Simulation time 13462235956 ps
CPU time 1252.1 seconds
Started Jan 10 12:31:47 PM PST 24
Finished Jan 10 12:53:28 PM PST 24
Peak memory 287076 kb
Host smart-911fd699-e00e-4ff1-96c4-abaf89f72878
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701310141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2701310141
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.623623633
Short name T339
Test name
Test status
Simulation time 15835234950 ps
CPU time 157.03 seconds
Started Jan 10 12:30:56 PM PST 24
Finished Jan 10 12:34:19 PM PST 24
Peak memory 248168 kb
Host smart-df86ade2-f5fb-4eaa-ae18-9bbdb321e7a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623623633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.623623633
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3341351564
Short name T514
Test name
Test status
Simulation time 677189874 ps
CPU time 12.59 seconds
Started Jan 10 12:30:55 PM PST 24
Finished Jan 10 12:32:00 PM PST 24
Peak memory 248208 kb
Host smart-8d3c27b5-c4e0-4e40-9917-1157dea3abcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33413
51564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3341351564
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1584864829
Short name T94
Test name
Test status
Simulation time 753319973 ps
CPU time 16.94 seconds
Started Jan 10 12:31:46 PM PST 24
Finished Jan 10 12:32:51 PM PST 24
Peak memory 252164 kb
Host smart-d41c699a-7a0b-4152-86d9-3c3ace9aa48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15848
64829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1584864829
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.4180629365
Short name T26
Test name
Test status
Simulation time 1119977448 ps
CPU time 29.85 seconds
Started Jan 10 12:30:55 PM PST 24
Finished Jan 10 12:32:11 PM PST 24
Peak memory 246584 kb
Host smart-3e7a0b13-52d0-4c70-bc8b-b3b4c5dc32f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41806
29365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.4180629365
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1725000668
Short name T223
Test name
Test status
Simulation time 287565366 ps
CPU time 3.79 seconds
Started Jan 10 12:28:10 PM PST 24
Finished Jan 10 12:28:28 PM PST 24
Peak memory 240584 kb
Host smart-bdd409ef-cb82-4724-87e9-d363365dc9d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17250
00668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1725000668
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.959711274
Short name T572
Test name
Test status
Simulation time 47242668365 ps
CPU time 642.8 seconds
Started Jan 10 12:32:23 PM PST 24
Finished Jan 10 12:43:44 PM PST 24
Peak memory 271996 kb
Host smart-d55d7ffa-fddd-4dbe-8ab2-ea8722f993b7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959711274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.959711274
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.301022144
Short name T204
Test name
Test status
Simulation time 66374261 ps
CPU time 3.75 seconds
Started Jan 10 12:31:10 PM PST 24
Finished Jan 10 12:32:00 PM PST 24
Peak memory 247972 kb
Host smart-61a68da7-7f00-47c5-8f11-036461f96eaf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=301022144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.301022144
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2715278744
Short name T606
Test name
Test status
Simulation time 155533949651 ps
CPU time 1907.44 seconds
Started Jan 10 12:31:10 PM PST 24
Finished Jan 10 01:03:44 PM PST 24
Peak memory 280904 kb
Host smart-c4983bee-8e4d-4240-95a7-d6c285fa65d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715278744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2715278744
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3165451475
Short name T708
Test name
Test status
Simulation time 1085795780 ps
CPU time 14.68 seconds
Started Jan 10 12:34:42 PM PST 24
Finished Jan 10 12:35:38 PM PST 24
Peak memory 248120 kb
Host smart-8f5ec5cd-5192-40bc-a758-7f44440a19c9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3165451475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3165451475
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1625944013
Short name T386
Test name
Test status
Simulation time 1906836590 ps
CPU time 112.98 seconds
Started Jan 10 12:31:47 PM PST 24
Finished Jan 10 12:34:29 PM PST 24
Peak memory 254104 kb
Host smart-05179cd1-cad2-4d12-9751-4f3aa95daceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16259
44013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1625944013
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1059485939
Short name T546
Test name
Test status
Simulation time 414916720 ps
CPU time 26.35 seconds
Started Jan 10 12:32:10 PM PST 24
Finished Jan 10 12:33:20 PM PST 24
Peak memory 253868 kb
Host smart-f477c514-bd44-48bb-af63-acb2f6baefb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10594
85939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1059485939
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1475325781
Short name T346
Test name
Test status
Simulation time 55495165244 ps
CPU time 1003.72 seconds
Started Jan 10 12:32:10 PM PST 24
Finished Jan 10 12:49:38 PM PST 24
Peak memory 288460 kb
Host smart-f126ff8d-79f2-47e2-b950-be16d880c1c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475325781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1475325781
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2678180437
Short name T383
Test name
Test status
Simulation time 10619437039 ps
CPU time 1047.61 seconds
Started Jan 10 12:31:09 PM PST 24
Finished Jan 10 12:49:23 PM PST 24
Peak memory 284328 kb
Host smart-991ad366-ac0e-433b-89e1-1324a9431750
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678180437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2678180437
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.719847887
Short name T323
Test name
Test status
Simulation time 43418651129 ps
CPU time 179.86 seconds
Started Jan 10 12:31:10 PM PST 24
Finished Jan 10 12:34:55 PM PST 24
Peak memory 246612 kb
Host smart-543fc302-8042-4117-b6dd-a8ccb660593e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719847887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.719847887
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.623302540
Short name T2
Test name
Test status
Simulation time 1130876551 ps
CPU time 21.18 seconds
Started Jan 10 12:32:11 PM PST 24
Finished Jan 10 12:33:15 PM PST 24
Peak memory 248048 kb
Host smart-189d2d8b-deeb-4c2f-b992-bf9f8fa3e1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62330
2540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.623302540
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.41452411
Short name T658
Test name
Test status
Simulation time 1314544137 ps
CPU time 28.95 seconds
Started Jan 10 12:31:53 PM PST 24
Finished Jan 10 12:33:09 PM PST 24
Peak memory 247252 kb
Host smart-bf69ff30-0a26-4f26-8631-9c007983eeaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41452
411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.41452411
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3313471062
Short name T404
Test name
Test status
Simulation time 843566674 ps
CPU time 43.98 seconds
Started Jan 10 12:32:19 PM PST 24
Finished Jan 10 12:33:42 PM PST 24
Peak memory 255352 kb
Host smart-f805e529-2a61-444f-861a-fb830f1656c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33134
71062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3313471062
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.860913421
Short name T629
Test name
Test status
Simulation time 4366493314 ps
CPU time 63.51 seconds
Started Jan 10 12:32:12 PM PST 24
Finished Jan 10 12:33:58 PM PST 24
Peak memory 248108 kb
Host smart-44b3ff43-15fe-44b9-9009-6a803fa8158a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86091
3421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.860913421
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.598287832
Short name T126
Test name
Test status
Simulation time 96840224926 ps
CPU time 2144.21 seconds
Started Jan 10 12:34:23 PM PST 24
Finished Jan 10 01:10:42 PM PST 24
Peak memory 271996 kb
Host smart-b0c51d77-f4d1-402a-ad84-a8063d7d8f66
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598287832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.598287832
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.646385298
Short name T620
Test name
Test status
Simulation time 64623550278 ps
CPU time 1000.61 seconds
Started Jan 10 12:31:09 PM PST 24
Finished Jan 10 12:48:36 PM PST 24
Peak memory 271084 kb
Host smart-b1d606a4-3a39-4886-bbd8-a8a6df5892fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646385298 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.646385298
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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