Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	104239	1			T1	15		T3	4960		T5	19
class_i[0x1]	85715	1			T3	853		T13	10		T15	1
class_i[0x2]	66712	1			T1	6		T3	1663		T5	1
class_i[0x3]	53823	1			T3	989		T5	6		T13	7

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	75594	1			T1	7		T3	1901		T5	9
alert[0x1]	78566	1			T1	6		T3	2195		T5	1
alert[0x2]	78291	1			T1	6		T3	2557		T5	5
alert[0x3]	78038	1			T1	2		T3	1812		T5	11

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

310199

1

T1

21

T3

8465

T5

18

esc_ping_fail

290

1

T5

8

T7

3

T8

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	75511	1			T1	7		T3	1901		T5	6
esc_integrity_fail	alert[0x1]	78489	1			T1	6		T3	2195		T13	9
esc_integrity_fail	alert[0x2]	78223	1			T1	6		T3	2557		T5	4
esc_integrity_fail	alert[0x3]	77976	1			T1	2		T3	1812		T5	8
esc_ping_fail	alert[0x0]	83	1			T5	3		T126	3		T250	1
esc_ping_fail	alert[0x1]	77	1			T5	1		T8	1		T80	1
esc_ping_fail	alert[0x2]	68	1			T5	1		T7	2		T8	1
esc_ping_fail	alert[0x3]	62	1			T5	3		T7	1		T8	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	104171	1			T1	15		T3	4960		T5	18
esc_integrity_fail	class_i[0x1]	85622	1			T3	853		T13	10		T15	1
esc_integrity_fail	class_i[0x2]	66629	1			T1	6		T3	1663		T32	4
esc_integrity_fail	class_i[0x3]	53777	1			T3	989		T13	7		T47	37
esc_ping_fail	class_i[0x0]	68	1			T5	1		T7	1		T8	1
esc_ping_fail	class_i[0x1]	93	1			T126	3		T250	1		T318	5
esc_ping_fail	class_i[0x2]	83	1			T5	1		T7	1		T8	2
esc_ping_fail	class_i[0x3]	46	1			T5	6		T7	1		T80	1