Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	740771789	0	0	0
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	740771789	0	0	638
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	740771789	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	740771789	740596586	0	0
tb.dut.CheckAccuCntDw	0	0	638	638	0	0
tb.dut.CheckEscCntDw	0	0	638	638	0	0
tb.dut.CheckNAlerts	0	0	638	638	0	0
tb.dut.CheckNClasses	0	0	638	638	0	0
tb.dut.CheckNEscSev	0	0	638	638	0	0
tb.dut.CrashdumpKnownO_A	0	0	740771789	740596586	0	0
tb.dut.EdnKnownO_A	0	0	740771789	740596586	0	0
tb.dut.EscPKnownO_A	0	0	740771789	740596586	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	740771789	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	740771789	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	740771789	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	740771789	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	740771789	80	0	0
tb.dut.IrqAKnownO_A	0	0	740771789	740596586	0	0
tb.dut.IrqBKnownO_A	0	0	740771789	740596586	0	0
tb.dut.IrqCKnownO_A	0	0	740771789	740596586	0	0
tb.dut.IrqDKnownO_A	0	0	740771789	740596586	0	0
tb.dut.TlAReadyKnownO_A	0	0	740771789	740596586	0	0
tb.dut.TlDValidKnownO_A	0	0	740771789	740596586	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	765295846	3986690	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	765295846	17477	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	765295846	18440	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	765295846	16203	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	765295846	17746	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	765295846	14629	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	765295846	16290	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	765295846	15021	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	765295846	17143	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	765295846	17308	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	765295846	16367	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	765295846	16049	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	765295846	16793	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	765295846	17674	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	765295846	16601	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	765295846	16278	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	765295846	16082	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	765295846	16359	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	765295846	17507	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	765295846	16281	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	765295846	17295	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	765295846	15147	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	765295846	17286	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	765295846	16617	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	765295846	17389	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	765295846	14900	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	765295846	17422	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	765295846	17434	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	765295846	16230	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	765295846	17680	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	765295846	18645	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	765295846	16106	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	765295846	16186	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	765295846	15168	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	765295846	17523	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	765295846	16331	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	765295846	16208	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	765295846	16700	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	765295846	15286	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	765295846	15210	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	765295846	17349	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	765295846	18511	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	765295846	17088	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	765295846	16266	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	765295846	14979	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	765295846	17413	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	765295846	14991	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	765295846	17409	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	765295846	17512	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	765295846	15092	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	765295846	16413	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	765295846	16085	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	765295846	17492	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	765295846	16213	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	765295846	17599	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	765295846	16621	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	765295846	16353	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	765295846	17241	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	765295846	15183	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	765295846	16335	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	765295846	14848	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	765295846	17635	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	765295846	14998	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	765295846	15079	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	765295846	16334	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	765295846	17324	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	765295846	17557	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	765295846	16231	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	765295846	16739	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	765295846	18572	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	765295846	29309	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	765295846	16426	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	765295846	15200	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	765295846	16333	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	765295846	16155	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	765295846	15102	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	765295846	16338	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	765295846	17340	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	765295846	17297	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	740771789	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	740771789	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	740771789	80	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	740771789	275390	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	740771789	375044378	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	740771789	329	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	740771789	989	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	740771789	63	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	740771789	504	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	740599923	244433318	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	740771789	1115	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	740771789	1098	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	740771789	1068	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	740771789	1046	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	740771789	770	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	740771789	87163	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	740771789	634	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	740771789	73	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	740771789	1468	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	740771789	1228	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	638	638	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	740771789	740596586	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	740771789	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	740771789	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	740771789	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	740771789	5727	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	740771789	217398	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	740771789	385649675	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	740771789	308	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	740771789	565	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	740771789	26	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	740771789	255	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	740599923	297893954	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	740771789	661	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	740771789	655	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	740771789	641	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	740771789	627	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	740771789	1084	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	740771789	130674	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	740771789	985	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	740771789	73	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	740771789	1465	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	740771789	1225	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	638	638	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	740771789	740596586	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	740771789	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	740771789	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	740771789	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	740771789	1573	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	740771789	176783	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	740771789	426217991	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	740771789	257	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	740771789	545	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	740771789	17	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	740771789	248	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	740599923	324745225	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	740771789	623	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	740771789	610	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	740771789	601	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	740771789	590	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	740771789	909	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	740771789	125215	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	740771789	824	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	740771789	68	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	740771789	1421	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	740771789	1181	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	638	638	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	740771789	740596586	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	740771789	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	740771789	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	740771789	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	740771789	6493	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	740771789	157769	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	740771789	422139953	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	740771789	277	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	740771789	525	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	740771789	23	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	740771789	216	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	740599923	332656060	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	740771789	619	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	740771789	609	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	740771789	601	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	740771789	591	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	740771789	840	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	740771789	105137	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	740771789	740	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	740771789	77	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	740771789	1442	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	740771789	1202	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	638	638	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	740771789	740596586	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	765295846	144621852	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	765295846	764646755	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	765295846	764646755	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	765295846	201568800	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	765295846	764646755	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	765295846	764646755	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	843	843	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	843	843	0	0
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tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	843	843	0	0

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