Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	73	1			T3	1		T89	1		T92	1
class_index[0x1]	73	1			T32	1		T81	2		T82	1
class_index[0x2]	68	1			T2	1		T81	1		T87	1
class_index[0x3]	77	1			T13	1		T81	2		T124	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	110	1			T87	1		T55	1		T43	1
intr_timeout_cnt[1]	58	1			T32	1		T81	1		T91	1
intr_timeout_cnt[2]	38	1			T13	1		T81	3		T53	1
intr_timeout_cnt[3]	17	1			T2	1		T66	1		T68	1
intr_timeout_cnt[4]	16	1			T124	1		T50	1		T96	1
intr_timeout_cnt[5]	11	1			T3	1		T82	1		T215	1
intr_timeout_cnt[6]	9	1			T261	1		T262	1		T107	1
intr_timeout_cnt[7]	14	1			T81	1		T53	1		T94	1
intr_timeout_cnt[8]	8	1			T53	1		T142	1		T143	1
intr_timeout_cnt[9]	10	1			T53	1		T97	1		T263	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	37	1			T89	1		T50	1		T94	1
class_index[0x0]	intr_timeout_cnt[1]	10	1			T92	1		T93	1		T264	1
class_index[0x0]	intr_timeout_cnt[2]	12	1			T133	2		T265	1		T105	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T266	1		T267	1		T268	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T96	1		T133	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	2	1			T3	1		T269	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T242	2		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T270	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	4	1			T97	1		T271	3		-	-
class_index[0x1]	intr_timeout_cnt[0]	24	1			T55	1		T56	1		T89	2
class_index[0x1]	intr_timeout_cnt[1]	16	1			T32	1		T81	1		T64	1
class_index[0x1]	intr_timeout_cnt[2]	12	1			T86	3		T91	1		T66	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T133	1		T129	1		T272	1
class_index[0x1]	intr_timeout_cnt[4]	5	1			T66	2		T97	1		T273	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T82	1		T274	1		T121	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T107	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	3	1			T81	1		T275	2		-	-
class_index[0x1]	intr_timeout_cnt[9]	5	1			T53	1		T263	1		T276	2
class_index[0x2]	intr_timeout_cnt[0]	27	1			T87	1		T123	1		T93	1
class_index[0x2]	intr_timeout_cnt[1]	15	1			T91	1		T122	1		T37	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T81	1		T277	1		T267	1
class_index[0x2]	intr_timeout_cnt[3]	6	1			T2	1		T66	1		T68	1
class_index[0x2]	intr_timeout_cnt[4]	4	1			T50	1		T265	1		T120	1
class_index[0x2]	intr_timeout_cnt[5]	4	1			T278	1		T279	1		T280	1
class_index[0x2]	intr_timeout_cnt[6]	3	1			T261	1		T281	1		T282	1
class_index[0x2]	intr_timeout_cnt[7]	5	1			T94	1		T262	1		T283	1
class_index[0x2]	intr_timeout_cnt[8]	1	1			T53	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	22	1			T43	1		T141	3		T144	1
class_index[0x3]	intr_timeout_cnt[1]	17	1			T56	1		T95	1		T34	8
class_index[0x3]	intr_timeout_cnt[2]	11	1			T13	1		T81	2		T53	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T133	1		T105	1		T273	1
class_index[0x3]	intr_timeout_cnt[4]	5	1			T124	1		T97	1		T277	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T215	1		T284	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	5	1			T262	1		T285	1		T271	1
class_index[0x3]	intr_timeout_cnt[7]	4	1			T53	1		T34	1		T278	2
class_index[0x3]	intr_timeout_cnt[8]	6	1			T142	1		T143	1		T37	1
class_index[0x3]	intr_timeout_cnt[9]	1	1			T121	1		-	-		-	-