Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	362949	1			T24	5		T28	5		T30	5
all_values[1]	362949	1			T24	5		T28	5		T30	5
all_values[2]	362949	1			T24	5		T28	5		T30	5
all_values[3]	362949	1			T24	5		T28	5		T30	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

722038

1

T24

6

T28

15

T30

10

auto[1]

729758

1

T24

14

T28

5

T30

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

859323

1

T24

16

T28

12

T30

14

auto[1]

592473

1

T24

4

T28

8

T30

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102769	1			T28	3		T30	4		T213	1
all_values[0]	auto[0]	auto[1]	77247	1			T24	1		T214	2		T254	1
all_values[0]	auto[1]	auto[0]	105047	1			T24	4		T28	1		T30	1
all_values[0]	auto[1]	auto[1]	77886	1			T28	1		T213	1		T254	4
all_values[1]	auto[0]	auto[0]	108053	1			T24	1		T28	2		T30	1
all_values[1]	auto[0]	auto[1]	72437	1			T28	3		T30	1		T214	3
all_values[1]	auto[1]	auto[0]	110038	1			T24	3		T30	1		T213	1
all_values[1]	auto[1]	auto[1]	72421	1			T24	1		T30	2		T214	2
all_values[2]	auto[0]	auto[0]	107717	1			T28	1		T30	4		T213	1
all_values[2]	auto[0]	auto[1]	73248	1			T28	2		T213	3		T214	1
all_values[2]	auto[1]	auto[0]	108696	1			T24	5		T28	2		T30	1
all_values[2]	auto[1]	auto[1]	73288	1			T213	1		T214	2		T1	1
all_values[3]	auto[0]	auto[0]	107696	1			T24	2		T28	2		T213	1
all_values[3]	auto[0]	auto[1]	72871	1			T24	2		T28	2		T214	1
all_values[3]	auto[1]	auto[0]	109307	1			T24	1		T28	1		T30	2
all_values[3]	auto[1]	auto[1]	73075	1			T30	3		T214	4		T1	2