Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	362949	1			T24	5		T28	5		T30	5
all_pins[1]	362949	1			T24	5		T28	5		T30	5
all_pins[2]	362949	1			T24	5		T28	5		T30	5
all_pins[3]	362949	1			T24	5		T28	5		T30	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1155126	1			T24	19		T28	19		T30	15
values[0x1]	296670	1			T24	1		T28	1		T30	5
transitions[0x0=>0x1]	196992	1			T24	1		T30	5		T213	1
transitions[0x1=>0x0]	197252	1			T24	1		T28	1		T30	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	285063	1			T24	5		T28	4		T30	5
all_pins[0]	values[0x1]	77886	1			T28	1		T213	1		T254	4
all_pins[0]	transitions[0x0=>0x1]	77164	1			T254	3		T1	2		T2	2
all_pins[0]	transitions[0x1=>0x0]	72613	1			T30	3		T214	4		T1	2
all_pins[1]	values[0x0]	290528	1			T24	4		T28	5		T30	3
all_pins[1]	values[0x1]	72421	1			T24	1		T30	2		T214	2
all_pins[1]	transitions[0x0=>0x1]	39060	1			T24	1		T30	2		T214	2
all_pins[1]	transitions[0x1=>0x0]	44525	1			T28	1		T213	1		T254	3
all_pins[2]	values[0x0]	289661	1			T24	5		T28	5		T30	5
all_pins[2]	values[0x1]	73288	1			T213	1		T214	2		T1	1
all_pins[2]	transitions[0x0=>0x1]	40520	1			T213	1		T214	2		T1	1
all_pins[2]	transitions[0x1=>0x0]	39653	1			T24	1		T30	2		T214	2
all_pins[3]	values[0x0]	289874	1			T24	5		T28	5		T30	2
all_pins[3]	values[0x1]	73075	1			T30	3		T214	4		T1	2
all_pins[3]	transitions[0x0=>0x1]	40248	1			T30	3		T214	3		T1	2
all_pins[3]	transitions[0x1=>0x0]	40461	1			T213	1		T214	1		T1	1