Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1			T24	4		T28	4		T30	4
all_values[1]	263	1			T24	4		T28	4		T30	4
all_values[2]	263	1			T24	4		T28	4		T30	4
all_values[3]	263	1			T24	4		T28	4		T30	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

522

1

T24

5

T28

9

T30

10

auto[1]

530

1

T24

11

T28

7

T30

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

473

1

T24

7

T28

7

T30

10

auto[1]

579

1

T24

9

T28

9

T30

6

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

654

1

T24

9

T28

10

T30

12

auto[1]

398

1

T24

7

T28

6

T30

4

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

51

1

T28

1

T30

2

T213

1

all_values[0]

auto[0]

auto[0]

auto[1]

20

1

T214

1

T254

1

T372

1

all_values[0]

auto[0]

auto[1]

auto[0]

71

1

T24

1

T28

1

T30

2

all_values[0]

auto[0]

auto[1]

auto[1]

23

1

T254

1

T373

1

T374

1

all_values[0]

auto[1]

auto[0]

auto[1]

38

1

T24

1

T213

1

T214

1

all_values[0]

auto[1]

auto[1]

auto[1]

60

1

T24

2

T28

2

T213

1

all_values[1]

auto[0]

auto[0]

auto[0]

61

1

T24

1

T28

1

T30

1

all_values[1]

auto[0]

auto[0]

auto[1]

21

1

T28

1

T214

1

T209

2

all_values[1]

auto[0]

auto[1]

auto[0]

53

1

T24

1

T214

2

T254

2

all_values[1]

auto[0]

auto[1]

auto[1]

24

1

T24

1

T30

1

T374

1

all_values[1]

auto[1]

auto[0]

auto[1]

49

1

T28

2

T30

2

T214

2

all_values[1]

auto[1]

auto[1]

auto[1]

55

1

T24

1

T213

1

T214

2

all_values[2]

auto[0]

auto[0]

auto[0]

69

1

T30

4

T214

1

T375

3

all_values[2]

auto[0]

auto[0]

auto[1]

23

1

T28

1

T213

1

T209

1

all_values[2]

auto[0]

auto[1]

auto[0]

60

1

T24

3

T28

2

T214

2

all_values[2]

auto[0]

auto[1]

auto[1]

16

1

T214

1

T373

1

T376

1

all_values[2]

auto[1]

auto[0]

auto[1]

60

1

T213

2

T214

1

T375

1

all_values[2]

auto[1]

auto[1]

auto[1]

35

1

T24

1

T28

1

T213

1

all_values[3]

auto[0]

auto[0]

auto[0]

52

1

T28

2

T30

1

T375

4

all_values[3]

auto[0]

auto[0]

auto[1]

25

1

T24

1

T28

1

T214

1

all_values[3]

auto[0]

auto[1]

auto[0]

56

1

T24

1

T213

2

T214

2

all_values[3]

auto[0]

auto[1]

auto[1]

29

1

T30

1

T214

2

T373

2

all_values[3]

auto[1]

auto[0]

auto[1]

53

1

T24

2

T213

2

T254

1

all_values[3]

auto[1]

auto[1]

auto[1]

48

1

T28

1

T30

2

T214

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal