Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	97461	1			T3	572		T6	477		T13	891
accum_cnt_1000	237708	1			T3	2924		T6	434		T13	1087
accum_cnt_100	32588	1			T3	551		T6	24		T13	54
accum_cnt_50	83562	1			T2	4		T3	771		T6	18
accum_cnt_10	203796	1			T1	30		T2	52		T3	930
accum_cnt_0	374550	1			T1	2		T2	64		T3	4882

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	267797	1			T1	8		T2	30		T3	2758
class_index[0x1]	267795	1			T1	8		T2	30		T3	2758
class_index[0x2]	267795	1			T1	8		T2	30		T3	2758
class_index[0x3]	267794	1			T1	8		T2	30		T3	2758

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	27892	1			T3	452		T41	380		T54	598
class_index[0x0]	accum_cnt_1000	58905	1			T3	715		T74	606		T53	121
class_index[0x0]	accum_cnt_100	7735	1			T3	154		T32	12		T81	16
class_index[0x0]	accum_cnt_50	24942	1			T2	3		T3	138		T19	9
class_index[0x0]	accum_cnt_10	55058	1			T1	6		T2	26		T3	524
class_index[0x0]	accum_cnt_0	77845	1			T1	2		T2	1		T3	621
class_index[0x1]	accum_cnt_2000	26052	1			T13	457		T15	442		T51	339
class_index[0x1]	accum_cnt_1000	64758	1			T3	1047		T13	535		T15	411
class_index[0x1]	accum_cnt_100	8901	1			T3	208		T13	28		T15	30
class_index[0x1]	accum_cnt_50	15282	1			T3	405		T13	29		T15	20
class_index[0x1]	accum_cnt_10	48593	1			T1	8		T3	51		T5	22
class_index[0x1]	accum_cnt_0	91432	1			T2	30		T3	1047		T5	9
class_index[0x2]	accum_cnt_2000	21306	1			T3	120		T51	476		T317	82
class_index[0x2]	accum_cnt_1000	54136	1			T3	268		T51	407		T52	733
class_index[0x2]	accum_cnt_100	6304	1			T3	83		T51	24		T52	94
class_index[0x2]	accum_cnt_50	19470	1			T2	1		T3	84		T21	8
class_index[0x2]	accum_cnt_10	51042	1			T1	8		T2	26		T3	28
class_index[0x2]	accum_cnt_0	108078	1			T2	3		T3	1927		T5	31
class_index[0x3]	accum_cnt_2000	22211	1			T6	477		T13	434		T14	379
class_index[0x3]	accum_cnt_1000	59909	1			T3	894		T6	434		T13	552
class_index[0x3]	accum_cnt_100	9648	1			T3	106		T6	24		T13	26
class_index[0x3]	accum_cnt_50	23868	1			T3	144		T6	18		T20	4
class_index[0x3]	accum_cnt_10	49103	1			T1	8		T3	327		T5	21
class_index[0x3]	accum_cnt_0	97195	1			T2	30		T3	1287		T5	10