Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	7902	1			T3	180		T126	1		T74	17
alert[0x1]	3954	1			T15	25		T74	26		T53	10
alert[0x2]	5614	1			T74	65		T43	4		T318	1
alert[0x3]	3124	1			T126	1		T255	82		T319	300
alert[0x4]	8367	1			T3	49		T15	153		T74	15
alert[0x5]	9568	1			T5	1		T126	1		T81	9
alert[0x6]	9493	1			T15	71		T74	56		T54	96
alert[0x7]	6062	1			T3	7		T8	1		T74	130
alert[0x8]	4712	1			T3	58		T15	21		T126	1
alert[0x9]	3755	1			T15	149		T250	1		T53	4
alert[0xa]	3397	1			T15	1334		T126	1		T54	78
alert[0xb]	3769	1			T3	186		T32	3		T15	16
alert[0xc]	4221	1			T15	496		T53	53		T318	1
alert[0xd]	2659	1			T3	31		T5	1		T15	193
alert[0xe]	7786	1			T8	1		T43	41		T142	5
alert[0xf]	5254	1			T3	13		T32	3		T53	2
alert[0x10]	8246	1			T43	7		T255	223		T89	277
alert[0x11]	9744	1			T3	996		T15	2925		T47	1
alert[0x12]	6190	1			T3	9		T5	1		T15	61
alert[0x13]	3895	1			T3	146		T53	2		T54	20
alert[0x14]	4949	1			T3	134		T5	1		T7	1
alert[0x15]	7605	1			T15	108		T74	254		T53	16
alert[0x16]	6219	1			T3	217		T5	1		T7	1
alert[0x17]	4769	1			T1	9		T3	28		T7	1
alert[0x18]	4415	1			T3	119		T5	1		T255	1423
alert[0x19]	9618	1			T32	2		T15	11		T81	21
alert[0x1a]	4346	1			T3	17		T8	1		T15	58
alert[0x1b]	4864	1			T5	1		T15	305		T47	6
alert[0x1c]	8604	1			T3	55		T8	1		T32	1
alert[0x1d]	6313	1			T3	329		T56	4		T89	44
alert[0x1e]	7373	1			T3	211		T7	1		T53	44
alert[0x1f]	5643	1			T32	4		T15	180		T80	1
alert[0x20]	7663	1			T3	340		T32	2		T15	208
alert[0x21]	5802	1			T53	409		T54	26		T43	17
alert[0x22]	2100	1			T74	246		T43	6		T255	99
alert[0x23]	4393	1			T15	21		T126	1		T74	36
alert[0x24]	11339	1			T5	1		T7	1		T32	1
alert[0x25]	3468	1			T3	5		T15	834		T74	356
alert[0x26]	13893	1			T74	40		T53	284		T54	69
alert[0x27]	4347	1			T8	1		T15	49		T74	6
alert[0x28]	7736	1			T7	1		T43	15		T86	16
alert[0x29]	6285	1			T3	36		T5	1		T15	21
alert[0x2a]	6171	1			T15	5		T250	1		T320	1
alert[0x2b]	4914	1			T15	18		T74	10		T53	6
alert[0x2c]	7834	1			T3	70		T5	1		T321	1
alert[0x2d]	4347	1			T3	296		T250	2		T255	70
alert[0x2e]	5152	1			T8	1		T32	2		T15	226
alert[0x2f]	6944	1			T15	325		T126	1		T250	2
alert[0x30]	6055	1			T3	42		T74	9		T250	1
alert[0x31]	3370	1			T15	55		T53	7		T55	2
alert[0x32]	8211	1			T32	22		T15	503		T250	1
alert[0x33]	9239	1			T3	49		T74	9		T318	1
alert[0x34]	8315	1			T3	90		T15	166		T126	1
alert[0x35]	11754	1			T3	23		T13	9		T15	4239
alert[0x36]	5121	1			T7	1		T32	10		T74	313
alert[0x37]	5189	1			T3	163		T5	1		T47	1
alert[0x38]	8717	1			T74	20		T53	54		T54	44
alert[0x39]	6252	1			T8	1		T15	9		T74	86
alert[0x3a]	11346	1			T3	449		T15	124		T126	2
alert[0x3b]	10066	1			T3	12		T7	1		T32	3
alert[0x3c]	3584	1			T3	18		T32	80		T126	1
alert[0x3d]	8169	1			T5	1		T321	1		T53	4
alert[0x3e]	10541	1			T15	49		T74	8		T124	3
alert[0x3f]	2804	1			T47	1		T81	12		T74	49
alert[0x40]	7174	1			T3	7		T7	1		T32	18

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	141423	1			T3	958		T5	1		T13	9
class_i[0x1]	92506	1			T3	9		T5	9		T7	4
class_i[0x2]	97390	1			T1	9		T3	3408		T5	1
class_i[0x3]	89406	1			T3	10		T5	1		T7	3

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

420022

1

T1

9

T3

4385

T13

9

alert_ping_fail

703

1

T5

12

T7

9

T8

7

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	7895	1			T3	180		T74	17		T53	51
alert_integrity_fail	alert[0x1]	3946	1			T15	25		T74	26		T53	10
alert_integrity_fail	alert[0x2]	5601	1			T74	65		T43	4		T255	26
alert_integrity_fail	alert[0x3]	3118	1			T255	82		T319	300		T37	232
alert_integrity_fail	alert[0x4]	8360	1			T3	49		T15	153		T74	15
alert_integrity_fail	alert[0x5]	9553	1			T81	9		T53	13		T54	10
alert_integrity_fail	alert[0x6]	9479	1			T15	71		T74	56		T54	96
alert_integrity_fail	alert[0x7]	6042	1			T3	7		T74	130		T53	1
alert_integrity_fail	alert[0x8]	4701	1			T3	58		T15	21		T74	3
alert_integrity_fail	alert[0x9]	3748	1			T15	149		T53	4		T54	158
alert_integrity_fail	alert[0xa]	3387	1			T15	1334		T54	78		T55	18
alert_integrity_fail	alert[0xb]	3758	1			T3	186		T32	3		T15	16
alert_integrity_fail	alert[0xc]	4213	1			T15	496		T53	53		T89	5
alert_integrity_fail	alert[0xd]	2647	1			T3	31		T15	193		T53	3
alert_integrity_fail	alert[0xe]	7778	1			T43	41		T142	5		T37	4
alert_integrity_fail	alert[0xf]	5247	1			T3	13		T32	3		T53	2
alert_integrity_fail	alert[0x10]	8238	1			T43	7		T255	223		T89	277
alert_integrity_fail	alert[0x11]	9735	1			T3	996		T15	2925		T47	1
alert_integrity_fail	alert[0x12]	6178	1			T3	9		T15	61		T55	10
alert_integrity_fail	alert[0x13]	3888	1			T3	146		T53	2		T54	20
alert_integrity_fail	alert[0x14]	4933	1			T3	134		T43	292		T86	22
alert_integrity_fail	alert[0x15]	7592	1			T15	108		T74	254		T53	16
alert_integrity_fail	alert[0x16]	6201	1			T3	217		T15	1		T54	17
alert_integrity_fail	alert[0x17]	4758	1			T1	9		T3	28		T32	2
alert_integrity_fail	alert[0x18]	4402	1			T3	119		T255	1423		T319	45
alert_integrity_fail	alert[0x19]	9608	1			T32	2		T15	11		T81	21
alert_integrity_fail	alert[0x1a]	4337	1			T3	17		T15	58		T74	48
alert_integrity_fail	alert[0x1b]	4853	1			T15	305		T47	6		T74	28
alert_integrity_fail	alert[0x1c]	8586	1			T3	55		T32	1		T15	76
alert_integrity_fail	alert[0x1d]	6302	1			T3	329		T56	4		T89	44
alert_integrity_fail	alert[0x1e]	7361	1			T3	211		T53	44		T54	74
alert_integrity_fail	alert[0x1f]	5623	1			T32	4		T15	180		T54	746
alert_integrity_fail	alert[0x20]	7650	1			T3	340		T32	2		T15	208
alert_integrity_fail	alert[0x21]	5798	1			T53	409		T54	26		T43	17
alert_integrity_fail	alert[0x22]	2087	1			T74	246		T43	6		T255	99
alert_integrity_fail	alert[0x23]	4387	1			T15	21		T74	36		T54	1002
alert_integrity_fail	alert[0x24]	11331	1			T32	1		T74	108		T54	559
alert_integrity_fail	alert[0x25]	3456	1			T3	5		T15	834		T74	356
alert_integrity_fail	alert[0x26]	13883	1			T74	40		T53	284		T54	69
alert_integrity_fail	alert[0x27]	4342	1			T15	49		T74	6		T55	3
alert_integrity_fail	alert[0x28]	7720	1			T43	15		T86	16		T319	176
alert_integrity_fail	alert[0x29]	6272	1			T3	36		T15	21		T74	31
alert_integrity_fail	alert[0x2a]	6156	1			T15	5		T61	702		T94	63
alert_integrity_fail	alert[0x2b]	4908	1			T15	18		T74	10		T53	6
alert_integrity_fail	alert[0x2c]	7817	1			T3	70		T53	325		T54	2183
alert_integrity_fail	alert[0x2d]	4336	1			T3	296		T255	70		T319	373
alert_integrity_fail	alert[0x2e]	5142	1			T32	2		T15	226		T54	272
alert_integrity_fail	alert[0x2f]	6931	1			T15	325		T53	10		T54	1706
alert_integrity_fail	alert[0x30]	6045	1			T3	42		T74	9		T255	58
alert_integrity_fail	alert[0x31]	3364	1			T15	55		T53	7		T55	2
alert_integrity_fail	alert[0x32]	8199	1			T32	22		T15	503		T53	13
alert_integrity_fail	alert[0x33]	9223	1			T3	49		T74	9		T319	609
alert_integrity_fail	alert[0x34]	8305	1			T3	90		T15	166		T74	10
alert_integrity_fail	alert[0x35]	11744	1			T3	23		T13	9		T15	4239
alert_integrity_fail	alert[0x36]	5106	1			T32	10		T74	313		T53	3
alert_integrity_fail	alert[0x37]	5182	1			T3	163		T47	1		T53	294
alert_integrity_fail	alert[0x38]	8708	1			T74	20		T53	54		T54	44
alert_integrity_fail	alert[0x39]	6245	1			T15	9		T74	86		T53	8
alert_integrity_fail	alert[0x3a]	11336	1			T3	449		T15	124		T74	298
alert_integrity_fail	alert[0x3b]	10053	1			T3	12		T32	3		T53	2
alert_integrity_fail	alert[0x3c]	3575	1			T3	18		T32	80		T54	127
alert_integrity_fail	alert[0x3d]	8161	1			T53	4		T54	202		T255	150
alert_integrity_fail	alert[0x3e]	10531	1			T15	49		T74	8		T124	3
alert_integrity_fail	alert[0x3f]	2796	1			T47	1		T81	12		T74	49
alert_integrity_fail	alert[0x40]	7165	1			T3	7		T32	18		T15	20
alert_ping_fail	alert[0x0]	7	1			T126	1		T250	2		T322	1
alert_ping_fail	alert[0x1]	8	1			T323	1		T324	2		T325	1
alert_ping_fail	alert[0x2]	13	1			T318	1		T326	1		T327	1
alert_ping_fail	alert[0x3]	6	1			T126	1		T323	1		T328	1
alert_ping_fail	alert[0x4]	7	1			T329	1		T330	1		T328	1
alert_ping_fail	alert[0x5]	15	1			T5	1		T126	1		T329	1
alert_ping_fail	alert[0x6]	14	1			T139	1		T49	1		T331	1
alert_ping_fail	alert[0x7]	20	1			T8	1		T69	1		T318	2
alert_ping_fail	alert[0x8]	11	1			T126	1		T323	1		T332	1
alert_ping_fail	alert[0x9]	7	1			T250	1		T333	1		T334	1
alert_ping_fail	alert[0xa]	10	1			T126	1		T327	1		T335	1
alert_ping_fail	alert[0xb]	11	1			T327	1		T336	1		T334	1
alert_ping_fail	alert[0xc]	8	1			T318	1		T337	1		T330	1
alert_ping_fail	alert[0xd]	12	1			T5	1		T80	1		T337	1
alert_ping_fail	alert[0xe]	8	1			T8	1		T333	1		T338	1
alert_ping_fail	alert[0xf]	7	1			T329	1		T49	1		T333	1
alert_ping_fail	alert[0x10]	8	1			T333	1		T339	1		T340	1
alert_ping_fail	alert[0x11]	9	1			T80	1		T250	1		T337	1
alert_ping_fail	alert[0x12]	12	1			T5	1		T329	2		T49	1
alert_ping_fail	alert[0x13]	7	1			T341	2		T336	1		T342	1
alert_ping_fail	alert[0x14]	16	1			T5	1		T7	1		T318	1
alert_ping_fail	alert[0x15]	13	1			T320	1		T329	1		T343	2
alert_ping_fail	alert[0x16]	18	1			T5	1		T7	1		T313	1
alert_ping_fail	alert[0x17]	11	1			T7	1		T126	1		T336	1
alert_ping_fail	alert[0x18]	13	1			T5	1		T326	1		T323	1
alert_ping_fail	alert[0x19]	10	1			T250	1		T49	1		T336	1
alert_ping_fail	alert[0x1a]	9	1			T8	1		T126	1		T321	1
alert_ping_fail	alert[0x1b]	11	1			T5	1		T52	1		T126	1
alert_ping_fail	alert[0x1c]	18	1			T8	1		T139	1		T344	1
alert_ping_fail	alert[0x1d]	11	1			T320	1		T337	1		T329	1
alert_ping_fail	alert[0x1e]	12	1			T7	1		T329	1		T336	2
alert_ping_fail	alert[0x1f]	20	1			T80	1		T320	1		T337	1
alert_ping_fail	alert[0x20]	13	1			T126	1		T250	2		T333	1
alert_ping_fail	alert[0x21]	4	1			T330	1		T345	1		T328	1
alert_ping_fail	alert[0x22]	13	1			T333	1		T341	1		T336	1
alert_ping_fail	alert[0x23]	6	1			T126	1		T250	1		T330	1
alert_ping_fail	alert[0x24]	8	1			T5	1		T7	1		T327	1
alert_ping_fail	alert[0x25]	12	1			T329	1		T323	1		T336	2
alert_ping_fail	alert[0x26]	10	1			T318	1		T327	3		T322	1
alert_ping_fail	alert[0x27]	5	1			T8	1		T326	1		T322	1
alert_ping_fail	alert[0x28]	16	1			T7	1		T326	1		T333	1
alert_ping_fail	alert[0x29]	13	1			T5	1		T337	1		T329	1
alert_ping_fail	alert[0x2a]	15	1			T250	1		T320	1		T329	1
alert_ping_fail	alert[0x2b]	6	1			T336	1		T346	1		T347	1
alert_ping_fail	alert[0x2c]	17	1			T5	1		T321	1		T315	2
alert_ping_fail	alert[0x2d]	11	1			T250	2		T320	1		T323	1
alert_ping_fail	alert[0x2e]	10	1			T8	1		T126	1		T250	1
alert_ping_fail	alert[0x2f]	13	1			T126	1		T250	2		T337	1
alert_ping_fail	alert[0x30]	10	1			T250	1		T323	1		T327	1
alert_ping_fail	alert[0x31]	6	1			T318	1		T329	1		T348	1
alert_ping_fail	alert[0x32]	12	1			T250	1		T337	1		T323	1
alert_ping_fail	alert[0x33]	16	1			T318	1		T326	1		T49	1
alert_ping_fail	alert[0x34]	10	1			T126	1		T326	1		T323	1
alert_ping_fail	alert[0x35]	10	1			T250	1		T337	1		T323	1
alert_ping_fail	alert[0x36]	15	1			T7	1		T250	1		T326	2
alert_ping_fail	alert[0x37]	7	1			T5	1		T322	1		T339	1
alert_ping_fail	alert[0x38]	9	1			T318	1		T327	1		T324	1
alert_ping_fail	alert[0x39]	7	1			T8	1		T49	1		T322	1
alert_ping_fail	alert[0x3a]	10	1			T126	2		T326	1		T327	1
alert_ping_fail	alert[0x3b]	13	1			T7	1		T80	1		T329	1
alert_ping_fail	alert[0x3c]	9	1			T126	1		T326	1		T349	1
alert_ping_fail	alert[0x3d]	8	1			T5	1		T321	1		T329	1
alert_ping_fail	alert[0x3e]	10	1			T326	1		T338	1		T325	1
alert_ping_fail	alert[0x3f]	8	1			T329	1		T323	1		T328	1
alert_ping_fail	alert[0x40]	9	1			T7	1		T250	2		T334	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	141290	1			T3	958		T13	9		T32	148
alert_integrity_fail	class_i[0x1]	92285	1			T3	9		T47	1		T53	1661
alert_integrity_fail	class_i[0x2]	97231	1			T1	9		T3	3408		T32	5
alert_integrity_fail	class_i[0x3]	89216	1			T3	10		T81	14		T124	3
alert_ping_fail	class_i[0x0]	133	1			T5	1		T8	2		T126	1
alert_ping_fail	class_i[0x1]	221	1			T5	9		T7	4		T8	2
alert_ping_fail	class_i[0x2]	159	1			T5	1		T7	2		T126	15
alert_ping_fail	class_i[0x3]	190	1			T5	1		T7	3		T8	3