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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.71 100.00 100.00 100.00 99.30 99.60


Total test records in report: 843
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T207 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1436615389 Jan 14 02:53:20 PM PST 24 Jan 14 02:53:23 PM PST 24 57141183 ps
T183 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1124726690 Jan 14 02:53:20 PM PST 24 Jan 14 03:02:45 PM PST 24 14989832823 ps
T780 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3986105123 Jan 14 02:52:49 PM PST 24 Jan 14 02:53:26 PM PST 24 1052255993 ps
T781 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1949832000 Jan 14 02:53:15 PM PST 24 Jan 14 02:53:42 PM PST 24 371294387 ps
T782 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1044869509 Jan 14 02:53:21 PM PST 24 Jan 14 02:53:23 PM PST 24 12038622 ps
T180 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4070971885 Jan 14 02:53:31 PM PST 24 Jan 14 03:02:19 PM PST 24 6504447714 ps
T783 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.160684220 Jan 14 02:52:33 PM PST 24 Jan 14 02:52:39 PM PST 24 175924854 ps
T784 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.991081373 Jan 14 02:53:15 PM PST 24 Jan 14 02:53:20 PM PST 24 62258097 ps
T169 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3425312874 Jan 14 02:52:16 PM PST 24 Jan 14 02:56:16 PM PST 24 2243503270 ps
T179 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.403466158 Jan 14 02:52:40 PM PST 24 Jan 14 03:03:32 PM PST 24 4601251924 ps
T785 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.390676187 Jan 14 02:52:58 PM PST 24 Jan 14 02:53:25 PM PST 24 315261008 ps
T786 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.452302894 Jan 14 02:52:50 PM PST 24 Jan 14 02:54:05 PM PST 24 547578596 ps
T201 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2844848704 Jan 14 02:52:47 PM PST 24 Jan 14 02:52:50 PM PST 24 58480571 ps
T161 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.4048890437 Jan 14 02:53:23 PM PST 24 Jan 14 02:58:18 PM PST 24 13799625572 ps
T787 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3064213465 Jan 14 02:53:49 PM PST 24 Jan 14 02:53:51 PM PST 24 19477824 ps
T788 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1513995451 Jan 14 02:53:35 PM PST 24 Jan 14 02:54:19 PM PST 24 4541062822 ps
T789 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.196936805 Jan 14 02:53:34 PM PST 24 Jan 14 02:53:40 PM PST 24 46646523 ps
T790 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2573654171 Jan 14 02:52:36 PM PST 24 Jan 14 02:52:44 PM PST 24 122144845 ps
T791 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2863808945 Jan 14 02:53:36 PM PST 24 Jan 14 02:53:38 PM PST 24 14408119 ps
T792 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1332692356 Jan 14 02:53:19 PM PST 24 Jan 14 02:53:29 PM PST 24 289709330 ps
T793 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1691850925 Jan 14 02:53:11 PM PST 24 Jan 14 02:53:24 PM PST 24 161661888 ps
T794 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1755562057 Jan 14 02:53:19 PM PST 24 Jan 14 02:53:33 PM PST 24 301122003 ps
T795 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2230200577 Jan 14 02:53:37 PM PST 24 Jan 14 02:53:40 PM PST 24 7484676 ps
T796 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.553042011 Jan 14 02:53:35 PM PST 24 Jan 14 02:53:37 PM PST 24 7696353 ps
T797 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1975268318 Jan 14 02:52:40 PM PST 24 Jan 14 02:52:42 PM PST 24 52202215 ps
T798 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2745012576 Jan 14 02:52:52 PM PST 24 Jan 14 02:52:54 PM PST 24 44191754 ps
T799 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1096734122 Jan 14 02:53:26 PM PST 24 Jan 14 02:53:28 PM PST 24 11979586 ps
T800 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.640180460 Jan 14 02:53:48 PM PST 24 Jan 14 02:53:51 PM PST 24 17229484 ps
T801 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3807014479 Jan 14 02:52:59 PM PST 24 Jan 14 02:53:27 PM PST 24 679498468 ps
T802 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2449842988 Jan 14 02:52:59 PM PST 24 Jan 14 02:53:21 PM PST 24 130779718 ps
T205 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3331389408 Jan 14 02:52:56 PM PST 24 Jan 14 02:53:36 PM PST 24 1168049997 ps
T175 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3734281936 Jan 14 02:52:50 PM PST 24 Jan 14 03:01:21 PM PST 24 6034555102 ps
T176 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3874499792 Jan 14 02:53:13 PM PST 24 Jan 14 02:56:27 PM PST 24 2713546467 ps
T187 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1288475146 Jan 14 02:53:12 PM PST 24 Jan 14 03:03:20 PM PST 24 34364125090 ps
T194 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1770267362 Jan 14 02:52:52 PM PST 24 Jan 14 02:52:56 PM PST 24 59971208 ps
T181 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2332673897 Jan 14 02:53:19 PM PST 24 Jan 14 02:56:41 PM PST 24 2731004613 ps
T189 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.321747012 Jan 14 02:52:25 PM PST 24 Jan 14 03:03:37 PM PST 24 8872772235 ps
T196 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.456067618 Jan 14 02:52:42 PM PST 24 Jan 14 02:52:46 PM PST 24 201755779 ps
T803 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3474654059 Jan 14 02:52:38 PM PST 24 Jan 14 02:53:06 PM PST 24 1477239429 ps
T804 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3248055673 Jan 14 02:52:22 PM PST 24 Jan 14 02:52:26 PM PST 24 9765852 ps
T805 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2359672807 Jan 14 02:53:40 PM PST 24 Jan 14 02:53:42 PM PST 24 6815111 ps
T377 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3558860310 Jan 14 02:53:35 PM PST 24 Jan 14 03:04:35 PM PST 24 6658841134 ps
T806 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.776478011 Jan 14 02:53:36 PM PST 24 Jan 14 02:53:38 PM PST 24 7545681 ps
T807 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1225504870 Jan 14 02:52:51 PM PST 24 Jan 14 02:52:58 PM PST 24 112149238 ps
T197 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2250791036 Jan 14 02:53:30 PM PST 24 Jan 14 02:53:34 PM PST 24 126629007 ps
T808 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.4035975098 Jan 14 02:53:43 PM PST 24 Jan 14 02:53:45 PM PST 24 12055529 ps
T195 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.488422159 Jan 14 02:52:49 PM PST 24 Jan 14 02:53:30 PM PST 24 314028572 ps
T166 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.658786647 Jan 14 02:52:56 PM PST 24 Jan 14 03:08:20 PM PST 24 50951975885 ps
T809 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2113210827 Jan 14 02:52:17 PM PST 24 Jan 14 02:52:26 PM PST 24 341601874 ps
T810 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1223516881 Jan 14 02:52:34 PM PST 24 Jan 14 02:52:36 PM PST 24 10949527 ps
T186 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.850286013 Jan 14 02:53:04 PM PST 24 Jan 14 03:17:27 PM PST 24 95387076013 ps
T811 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2781412769 Jan 14 02:52:56 PM PST 24 Jan 14 02:52:59 PM PST 24 12921280 ps
T812 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.890115020 Jan 14 02:53:33 PM PST 24 Jan 14 02:53:57 PM PST 24 5247971510 ps
T203 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.481249196 Jan 14 02:53:26 PM PST 24 Jan 14 02:53:30 PM PST 24 153019020 ps
T813 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2692649079 Jan 14 02:52:15 PM PST 24 Jan 14 03:00:33 PM PST 24 17451889088 ps
T814 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2652379826 Jan 14 02:53:46 PM PST 24 Jan 14 02:53:48 PM PST 24 25104064 ps
T815 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.977560958 Jan 14 02:53:47 PM PST 24 Jan 14 02:53:49 PM PST 24 22048912 ps
T816 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2195768910 Jan 14 02:53:32 PM PST 24 Jan 14 02:53:34 PM PST 24 8577876 ps
T198 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.4226058301 Jan 14 02:53:34 PM PST 24 Jan 14 02:53:40 PM PST 24 205021794 ps
T817 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1566875574 Jan 14 02:52:23 PM PST 24 Jan 14 02:52:37 PM PST 24 103578610 ps
T818 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1555749734 Jan 14 02:53:01 PM PST 24 Jan 14 02:53:14 PM PST 24 775913530 ps
T819 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.859356953 Jan 14 02:53:09 PM PST 24 Jan 14 02:53:54 PM PST 24 2774303353 ps
T173 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3734327949 Jan 14 02:52:17 PM PST 24 Jan 14 02:55:20 PM PST 24 9819122587 ps
T820 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.914946983 Jan 14 02:52:15 PM PST 24 Jan 14 02:52:26 PM PST 24 454332376 ps
T821 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2993247967 Jan 14 02:52:17 PM PST 24 Jan 14 02:52:26 PM PST 24 38622141 ps
T822 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1259447694 Jan 14 02:53:48 PM PST 24 Jan 14 02:53:50 PM PST 24 11974806 ps
T823 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.995837815 Jan 14 02:52:14 PM PST 24 Jan 14 02:52:38 PM PST 24 175275910 ps
T824 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2443455443 Jan 14 02:53:10 PM PST 24 Jan 14 02:53:15 PM PST 24 19261073 ps
T825 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3597163650 Jan 14 02:53:29 PM PST 24 Jan 14 02:53:33 PM PST 24 75994339 ps
T826 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2805736409 Jan 14 02:53:00 PM PST 24 Jan 14 02:53:02 PM PST 24 9885206 ps
T827 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2797399211 Jan 14 02:53:49 PM PST 24 Jan 14 02:53:52 PM PST 24 8341729 ps
T828 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.686486921 Jan 14 02:53:11 PM PST 24 Jan 14 02:53:29 PM PST 24 1022048203 ps
T829 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4201379864 Jan 14 02:52:53 PM PST 24 Jan 14 02:52:55 PM PST 24 10356276 ps
T174 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3788782399 Jan 14 02:52:53 PM PST 24 Jan 14 02:55:25 PM PST 24 2169363956 ps
T830 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1380931063 Jan 14 02:53:12 PM PST 24 Jan 14 02:53:17 PM PST 24 325032803 ps
T831 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2528842896 Jan 14 02:53:24 PM PST 24 Jan 14 02:53:26 PM PST 24 15174768 ps
T832 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.687692507 Jan 14 02:53:40 PM PST 24 Jan 14 02:53:49 PM PST 24 201697798 ps
T199 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1975252781 Jan 14 02:52:36 PM PST 24 Jan 14 02:53:16 PM PST 24 339471367 ps
T178 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.957738900 Jan 14 02:53:10 PM PST 24 Jan 14 02:54:47 PM PST 24 4872767103 ps
T182 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.874140729 Jan 14 02:53:28 PM PST 24 Jan 14 02:57:18 PM PST 24 2172414937 ps
T833 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2839565703 Jan 14 02:53:19 PM PST 24 Jan 14 02:53:25 PM PST 24 43422968 ps
T188 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3249961084 Jan 14 02:53:23 PM PST 24 Jan 14 03:01:52 PM PST 24 28826648123 ps
T834 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.4273538093 Jan 14 02:53:09 PM PST 24 Jan 14 02:53:15 PM PST 24 60611177 ps
T835 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.972687322 Jan 14 02:52:35 PM PST 24 Jan 14 02:53:59 PM PST 24 3030875923 ps
T192 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.415809041 Jan 14 02:52:57 PM PST 24 Jan 14 02:53:36 PM PST 24 1159237085 ps
T836 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1411240381 Jan 14 02:53:39 PM PST 24 Jan 14 02:53:41 PM PST 24 8667424 ps
T837 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4216376139 Jan 14 02:52:35 PM PST 24 Jan 14 02:52:44 PM PST 24 94905634 ps
T838 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2716694226 Jan 14 02:53:20 PM PST 24 Jan 14 02:53:29 PM PST 24 177803161 ps
T839 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.453618356 Jan 14 02:53:09 PM PST 24 Jan 14 02:53:11 PM PST 24 11453359 ps
T840 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.239578775 Jan 14 02:53:36 PM PST 24 Jan 14 02:54:14 PM PST 24 519885992 ps
T841 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3007904544 Jan 14 02:53:02 PM PST 24 Jan 14 02:53:31 PM PST 24 181818095 ps
T842 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1655401222 Jan 14 02:52:57 PM PST 24 Jan 14 02:53:03 PM PST 24 105559931 ps
T843 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.316338422 Jan 14 02:52:39 PM PST 24 Jan 14 02:53:02 PM PST 24 1113584183 ps

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2156120781
Short name T12
Test name
Test status
Simulation time 2313250672 ps
CPU time 39.08 seconds
Started Jan 14 02:52:40 PM PST 24
Finished Jan 14 02:53:20 PM PST 24
Peak memory 240444 kb
Host smart-0439e34d-55e5-4c56-b59d-9f87303c0384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2156120781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2156120781
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3240659842
Short name T3
Test name
Test status
Simulation time 41433688666 ps
CPU time 4549.7 seconds
Started Jan 14 02:59:11 PM PST 24
Finished Jan 14 04:15:02 PM PST 24
Peak memory 338572 kb
Host smart-61e1e8e1-9e00-4c15-8e22-e298bc0d973b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240659842 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3240659842
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1422585360
Short name T9
Test name
Test status
Simulation time 1030874134 ps
CPU time 13.36 seconds
Started Jan 14 02:59:02 PM PST 24
Finished Jan 14 02:59:16 PM PST 24
Peak memory 277556 kb
Host smart-1918a185-8974-4795-83f3-8cc7ff5a62d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1422585360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1422585360
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1714511530
Short name T15
Test name
Test status
Simulation time 52809335242 ps
CPU time 3094.21 seconds
Started Jan 14 03:01:10 PM PST 24
Finished Jan 14 03:52:49 PM PST 24
Peak memory 289064 kb
Host smart-e96e96e0-2f59-4bbb-a889-6b07c6e40863
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714511530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1714511530
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.453367917
Short name T23
Test name
Test status
Simulation time 30353490486 ps
CPU time 1007.07 seconds
Started Jan 14 02:52:14 PM PST 24
Finished Jan 14 03:09:04 PM PST 24
Peak memory 272416 kb
Host smart-c35b3186-84e1-4a93-9dce-4e0c01044ec2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453367917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.453367917
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1049744097
Short name T165
Test name
Test status
Simulation time 3842999124 ps
CPU time 304.16 seconds
Started Jan 14 02:53:02 PM PST 24
Finished Jan 14 02:58:07 PM PST 24
Peak memory 272708 kb
Host smart-17bc8d87-cb2a-4e4c-bf00-aba960bf4f18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1049744097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1049744097
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3443722433
Short name T314
Test name
Test status
Simulation time 26739380773 ps
CPU time 1437.06 seconds
Started Jan 14 03:01:00 PM PST 24
Finished Jan 14 03:24:58 PM PST 24
Peak memory 272668 kb
Host smart-9b8f911b-a04d-4ce5-8265-289615b81024
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443722433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3443722433
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2502318957
Short name T74
Test name
Test status
Simulation time 72079340600 ps
CPU time 4973.2 seconds
Started Jan 14 03:00:44 PM PST 24
Finished Jan 14 04:23:39 PM PST 24
Peak memory 305876 kb
Host smart-32c452ec-3f8c-4b41-bde6-2ff4db653064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502318957 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2502318957
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2562745534
Short name T214
Test name
Test status
Simulation time 8926659 ps
CPU time 1.62 seconds
Started Jan 14 02:53:00 PM PST 24
Finished Jan 14 02:53:03 PM PST 24
Peak memory 235684 kb
Host smart-b92387d3-1660-41a3-8dcb-702ee2a67bd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2562745534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2562745534
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1556917257
Short name T177
Test name
Test status
Simulation time 33811956601 ps
CPU time 1195.27 seconds
Started Jan 14 02:53:26 PM PST 24
Finished Jan 14 03:13:23 PM PST 24
Peak memory 265448 kb
Host smart-bc7394fe-60af-49e4-8c84-4e334a21b636
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556917257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1556917257
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2514806176
Short name T248
Test name
Test status
Simulation time 1464269387 ps
CPU time 35.17 seconds
Started Jan 14 02:59:37 PM PST 24
Finished Jan 14 03:00:13 PM PST 24
Peak memory 248588 kb
Host smart-017fa2a6-d257-404a-ae6f-da714d5bc859
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2514806176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2514806176
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.4048890437
Short name T161
Test name
Test status
Simulation time 13799625572 ps
CPU time 294.85 seconds
Started Jan 14 02:53:23 PM PST 24
Finished Jan 14 02:58:18 PM PST 24
Peak memory 272728 kb
Host smart-96e94517-093d-4ce1-a552-6f89220897a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4048890437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.4048890437
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2724430547
Short name T81
Test name
Test status
Simulation time 103459990143 ps
CPU time 4261.64 seconds
Started Jan 14 03:00:27 PM PST 24
Finished Jan 14 04:11:30 PM PST 24
Peak memory 305444 kb
Host smart-c7e6a27d-fa4b-4887-a311-061eafd8cfb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724430547 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2724430547
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.143006413
Short name T52
Test name
Test status
Simulation time 36537755653 ps
CPU time 2146.85 seconds
Started Jan 14 03:01:07 PM PST 24
Finished Jan 14 03:36:58 PM PST 24
Peak memory 272724 kb
Host smart-3f4cfee8-b6fb-41ac-934e-ff638b5c6657
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143006413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.143006413
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.900314483
Short name T155
Test name
Test status
Simulation time 43512066350 ps
CPU time 955.61 seconds
Started Jan 14 02:52:17 PM PST 24
Finished Jan 14 03:08:19 PM PST 24
Peak memory 265456 kb
Host smart-2bac3a99-1317-4c72-8ca3-dcf637ab7fce
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900314483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.900314483
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.271247232
Short name T126
Test name
Test status
Simulation time 22592503510 ps
CPU time 471.62 seconds
Started Jan 14 03:01:33 PM PST 24
Finished Jan 14 03:09:26 PM PST 24
Peak memory 248700 kb
Host smart-fc5ba960-cffb-4e1d-a3ed-342fe0ad4670
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271247232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.271247232
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2804451827
Short name T164
Test name
Test status
Simulation time 1877298971 ps
CPU time 194.21 seconds
Started Jan 14 02:53:39 PM PST 24
Finished Jan 14 02:56:54 PM PST 24
Peak memory 272192 kb
Host smart-a17d5797-5852-4511-9db6-b8e15058dc32
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2804451827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2804451827
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3282930061
Short name T329
Test name
Test status
Simulation time 26604755685 ps
CPU time 595.19 seconds
Started Jan 14 02:59:47 PM PST 24
Finished Jan 14 03:09:43 PM PST 24
Peak memory 248648 kb
Host smart-050928af-42cd-4ff6-8fed-248b41443185
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282930061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3282930061
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3254207539
Short name T43
Test name
Test status
Simulation time 91418120731 ps
CPU time 1537.68 seconds
Started Jan 14 02:59:19 PM PST 24
Finished Jan 14 03:24:58 PM PST 24
Peak memory 289096 kb
Host smart-9173747a-e60a-47b5-b8ef-e02e77dc754b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254207539 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3254207539
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3000577301
Short name T350
Test name
Test status
Simulation time 33459768454 ps
CPU time 2041.73 seconds
Started Jan 14 02:59:35 PM PST 24
Finished Jan 14 03:33:38 PM PST 24
Peak memory 272896 kb
Host smart-2dc0b6a8-696c-494c-96ba-e7b083b66d38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000577301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3000577301
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3593229620
Short name T153
Test name
Test status
Simulation time 6214049632 ps
CPU time 500.07 seconds
Started Jan 14 02:52:35 PM PST 24
Finished Jan 14 03:00:56 PM PST 24
Peak memory 265392 kb
Host smart-07f25c76-6806-43fa-a591-e65239333fd4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593229620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3593229620
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.173576374
Short name T133
Test name
Test status
Simulation time 33812948110 ps
CPU time 2161.27 seconds
Started Jan 14 03:01:34 PM PST 24
Finished Jan 14 03:37:37 PM PST 24
Peak memory 288868 kb
Host smart-044c239b-4577-4e1c-b85d-59ec6e77c49a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173576374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.173576374
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.550918879
Short name T139
Test name
Test status
Simulation time 149823310248 ps
CPU time 1292.77 seconds
Started Jan 14 03:00:44 PM PST 24
Finished Jan 14 03:22:18 PM PST 24
Peak memory 272420 kb
Host smart-e06b6942-d5c3-482b-ac57-85ee9e264645
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550918879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.550918879
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1005796766
Short name T157
Test name
Test status
Simulation time 29823799445 ps
CPU time 1067.36 seconds
Started Jan 14 02:52:59 PM PST 24
Finished Jan 14 03:10:48 PM PST 24
Peak memory 265396 kb
Host smart-3235d84d-b433-409b-8dea-4ce54a1a9b9d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005796766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1005796766
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3271926833
Short name T338
Test name
Test status
Simulation time 11662666224 ps
CPU time 470.78 seconds
Started Jan 14 03:02:41 PM PST 24
Finished Jan 14 03:10:33 PM PST 24
Peak memory 247288 kb
Host smart-b2a20ded-765e-4246-a3ed-090df0f1fe82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271926833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3271926833
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2583460402
Short name T117
Test name
Test status
Simulation time 31754085485 ps
CPU time 2049.9 seconds
Started Jan 14 02:59:35 PM PST 24
Finished Jan 14 03:33:46 PM PST 24
Peak memory 285976 kb
Host smart-eca9c1ee-fcb8-4da8-8f82-3001a722b9f8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583460402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2583460402
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2076068928
Short name T341
Test name
Test status
Simulation time 174316189021 ps
CPU time 2889.82 seconds
Started Jan 14 03:01:20 PM PST 24
Finished Jan 14 03:49:31 PM PST 24
Peak memory 288800 kb
Host smart-d98f59a9-9a34-4d58-a779-77e153c1127c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076068928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2076068928
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2401585317
Short name T53
Test name
Test status
Simulation time 44152665864 ps
CPU time 3482 seconds
Started Jan 14 03:00:11 PM PST 24
Finished Jan 14 03:58:15 PM PST 24
Peak memory 304836 kb
Host smart-1421c793-6f26-4aec-8197-591ceb4ea337
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401585317 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2401585317
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3425312874
Short name T169
Test name
Test status
Simulation time 2243503270 ps
CPU time 238 seconds
Started Jan 14 02:52:16 PM PST 24
Finished Jan 14 02:56:16 PM PST 24
Peak memory 265408 kb
Host smart-454048c7-c23c-4489-aeff-f26cd24c96c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3425312874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3425312874
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3574908492
Short name T250
Test name
Test status
Simulation time 55995408260 ps
CPU time 574.23 seconds
Started Jan 14 02:59:24 PM PST 24
Finished Jan 14 03:09:00 PM PST 24
Peak memory 248724 kb
Host smart-eff9119a-a232-4e67-ac22-0ea6222e7ae3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574908492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3574908492
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3793887935
Short name T86
Test name
Test status
Simulation time 127362716726 ps
CPU time 2730.22 seconds
Started Jan 14 03:01:14 PM PST 24
Finished Jan 14 03:46:46 PM PST 24
Peak memory 322444 kb
Host smart-7c8508f9-59ed-4a65-bd47-2008c23536e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793887935 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3793887935
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1810410719
Short name T254
Test name
Test status
Simulation time 13322771 ps
CPU time 1.7 seconds
Started Jan 14 02:53:39 PM PST 24
Finished Jan 14 02:53:42 PM PST 24
Peak memory 236456 kb
Host smart-a5ffe743-f1ed-44f8-8d95-7e0b5eeb9a99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1810410719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1810410719
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.4262998617
Short name T285
Test name
Test status
Simulation time 33531907952 ps
CPU time 509.81 seconds
Started Jan 14 03:03:33 PM PST 24
Finished Jan 14 03:12:05 PM PST 24
Peak memory 255208 kb
Host smart-adbec60b-3b32-41af-a785-38943c381fcf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262998617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.4262998617
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2845432432
Short name T38
Test name
Test status
Simulation time 124919323027 ps
CPU time 1542.74 seconds
Started Jan 14 03:00:47 PM PST 24
Finished Jan 14 03:26:35 PM PST 24
Peak memory 288976 kb
Host smart-d5fd1382-59fc-46d3-9b42-c6b4634325af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845432432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2845432432
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.403466158
Short name T179
Test name
Test status
Simulation time 4601251924 ps
CPU time 650.86 seconds
Started Jan 14 02:52:40 PM PST 24
Finished Jan 14 03:03:32 PM PST 24
Peak memory 272620 kb
Host smart-349406ca-473a-4a31-a4f6-6c42364334c5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403466158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.403466158
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.578845391
Short name T148
Test name
Test status
Simulation time 4738101689 ps
CPU time 82.08 seconds
Started Jan 14 02:53:02 PM PST 24
Finished Jan 14 02:54:25 PM PST 24
Peak memory 248732 kb
Host smart-d647ad83-d782-48b6-b1b8-d8c05c8f8771
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=578845391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.578845391
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.906026154
Short name T66
Test name
Test status
Simulation time 45460859828 ps
CPU time 3382.89 seconds
Started Jan 14 03:00:33 PM PST 24
Finished Jan 14 03:56:58 PM PST 24
Peak memory 299232 kb
Host smart-52103069-fbc0-4dfa-9f98-561d74e889b9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906026154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.906026154
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1293336612
Short name T316
Test name
Test status
Simulation time 33725900212 ps
CPU time 1732.34 seconds
Started Jan 14 02:58:50 PM PST 24
Finished Jan 14 03:27:44 PM PST 24
Peak memory 289228 kb
Host smart-66957bd2-8b8d-4ea9-b71f-8e02a9cd907b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293336612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1293336612
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1668441363
Short name T322
Test name
Test status
Simulation time 22458937579 ps
CPU time 478.22 seconds
Started Jan 14 02:59:52 PM PST 24
Finished Jan 14 03:07:51 PM PST 24
Peak memory 246904 kb
Host smart-2386b873-39da-4785-b845-78a54a362df4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668441363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1668441363
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1514199182
Short name T367
Test name
Test status
Simulation time 54139118221 ps
CPU time 3263.08 seconds
Started Jan 14 03:01:20 PM PST 24
Finished Jan 14 03:55:45 PM PST 24
Peak memory 288812 kb
Host smart-7576f2de-3c1e-48a9-b404-ae1f6e82a466
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514199182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1514199182
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1861792150
Short name T293
Test name
Test status
Simulation time 53897011657 ps
CPU time 3914.74 seconds
Started Jan 14 03:04:20 PM PST 24
Finished Jan 14 04:09:36 PM PST 24
Peak memory 280152 kb
Host smart-e8880cbe-67c8-4ca7-b9f8-73952ca07093
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861792150 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1861792150
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1179934397
Short name T7
Test name
Test status
Simulation time 8459098302 ps
CPU time 187.33 seconds
Started Jan 14 02:58:47 PM PST 24
Finished Jan 14 03:01:56 PM PST 24
Peak memory 247592 kb
Host smart-73c4d986-b20e-4877-97cb-a016f46f7461
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179934397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1179934397
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2522367306
Short name T242
Test name
Test status
Simulation time 51742151259 ps
CPU time 3629.94 seconds
Started Jan 14 02:59:49 PM PST 24
Finished Jan 14 04:00:20 PM PST 24
Peak memory 303156 kb
Host smart-67a72fc6-116f-463d-a263-49fa50cd8f75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522367306 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2522367306
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2976054924
Short name T675
Test name
Test status
Simulation time 63265837302 ps
CPU time 679.96 seconds
Started Jan 14 03:00:16 PM PST 24
Finished Jan 14 03:11:37 PM PST 24
Peak memory 247596 kb
Host smart-d281f298-fc3a-4a24-9216-2ff4e5886b91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976054924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2976054924
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.688024263
Short name T97
Test name
Test status
Simulation time 102930983778 ps
CPU time 6878.56 seconds
Started Jan 14 03:03:07 PM PST 24
Finished Jan 14 04:57:47 PM PST 24
Peak memory 338464 kb
Host smart-06e2c2ca-b2f3-413f-951e-ead5985eff8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688024263 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.688024263
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.4081463184
Short name T584
Test name
Test status
Simulation time 30833574534 ps
CPU time 1783.13 seconds
Started Jan 14 02:59:56 PM PST 24
Finished Jan 14 03:29:41 PM PST 24
Peak memory 273296 kb
Host smart-ae9f4475-0f8e-4cb7-a5e7-c3598ea220d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081463184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.4081463184
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.809210698
Short name T280
Test name
Test status
Simulation time 153877050449 ps
CPU time 7966.79 seconds
Started Jan 14 03:04:02 PM PST 24
Finished Jan 14 05:16:51 PM PST 24
Peak memory 338960 kb
Host smart-5d1fa60d-6428-42da-99c7-3742abc6cfed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809210698 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.809210698
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1514064674
Short name T107
Test name
Test status
Simulation time 189778029832 ps
CPU time 2403.27 seconds
Started Jan 14 02:59:40 PM PST 24
Finished Jan 14 03:39:44 PM PST 24
Peak memory 285872 kb
Host smart-e6d36d20-0863-4e10-b663-253865424802
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514064674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1514064674
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2590756709
Short name T162
Test name
Test status
Simulation time 24973735168 ps
CPU time 532.91 seconds
Started Jan 14 02:52:55 PM PST 24
Finished Jan 14 03:01:48 PM PST 24
Peak memory 265376 kb
Host smart-602f4a04-3e70-42bd-a1bd-6b36a125b7b9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590756709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2590756709
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2763549844
Short name T208
Test name
Test status
Simulation time 115973588 ps
CPU time 4.04 seconds
Started Jan 14 02:53:12 PM PST 24
Finished Jan 14 02:53:17 PM PST 24
Peak memory 236472 kb
Host smart-707da215-9423-4804-9716-47e50fb7318c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2763549844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2763549844
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3295693692
Short name T125
Test name
Test status
Simulation time 206611192 ps
CPU time 12 seconds
Started Jan 14 02:59:08 PM PST 24
Finished Jan 14 02:59:21 PM PST 24
Peak memory 248172 kb
Host smart-e9d1a682-e9d7-463e-9042-a9bfd7b3e1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32956
93692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3295693692
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.4084709849
Short name T228
Test name
Test status
Simulation time 43452601 ps
CPU time 3.48 seconds
Started Jan 14 02:58:51 PM PST 24
Finished Jan 14 02:58:56 PM PST 24
Peak memory 248904 kb
Host smart-ce0950b0-8b34-4045-ac36-49c7da5ec548
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4084709849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.4084709849
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.4019836935
Short name T236
Test name
Test status
Simulation time 34547285 ps
CPU time 3.25 seconds
Started Jan 14 02:59:35 PM PST 24
Finished Jan 14 02:59:39 PM PST 24
Peak memory 248884 kb
Host smart-53b965b8-7cf6-40a9-8353-3d92506fab4e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4019836935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.4019836935
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1112049989
Short name T233
Test name
Test status
Simulation time 46898178 ps
CPU time 2.58 seconds
Started Jan 14 02:59:48 PM PST 24
Finished Jan 14 02:59:51 PM PST 24
Peak memory 248900 kb
Host smart-c47912dd-4b4e-44c6-9c2e-833aedbcead2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1112049989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1112049989
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.957738900
Short name T178
Test name
Test status
Simulation time 4872767103 ps
CPU time 96.12 seconds
Started Jan 14 02:53:10 PM PST 24
Finished Jan 14 02:54:47 PM PST 24
Peak memory 256264 kb
Host smart-d0bfe0da-aba2-4c5f-be8c-e9e65e0ff648
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=957738900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.957738900
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.751959281
Short name T121
Test name
Test status
Simulation time 137315205472 ps
CPU time 2136.29 seconds
Started Jan 14 02:59:25 PM PST 24
Finished Jan 14 03:35:03 PM PST 24
Peak memory 281680 kb
Host smart-234128bf-4c57-45b5-8005-02d7e81b7e1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751959281 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.751959281
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1653639732
Short name T266
Test name
Test status
Simulation time 1047068327 ps
CPU time 57.58 seconds
Started Jan 14 03:00:32 PM PST 24
Finished Jan 14 03:01:31 PM PST 24
Peak memory 254604 kb
Host smart-38cec8af-9d05-48c3-94d4-42b47203a2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16536
39732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1653639732
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3749007326
Short name T284
Test name
Test status
Simulation time 50713091130 ps
CPU time 3716.45 seconds
Started Jan 14 03:01:17 PM PST 24
Finished Jan 14 04:03:14 PM PST 24
Peak memory 300920 kb
Host smart-13bc72dc-527c-44a5-9dbd-f35e81552429
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749007326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3749007326
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.440925481
Short name T346
Test name
Test status
Simulation time 39729657442 ps
CPU time 508.99 seconds
Started Jan 14 02:59:00 PM PST 24
Finished Jan 14 03:07:30 PM PST 24
Peak memory 248744 kb
Host smart-c45fc9f5-5df9-4391-ad0f-23f89e9be2ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440925481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.440925481
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4137438913
Short name T27
Test name
Test status
Simulation time 4055531012 ps
CPU time 99.68 seconds
Started Jan 14 02:52:52 PM PST 24
Finished Jan 14 02:54:33 PM PST 24
Peak memory 257212 kb
Host smart-f660474f-ea43-4620-b5d6-abfd9746df55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4137438913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.4137438913
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3316634145
Short name T200
Test name
Test status
Simulation time 13827384693 ps
CPU time 88.58 seconds
Started Jan 14 02:52:23 PM PST 24
Finished Jan 14 02:53:54 PM PST 24
Peak memory 237808 kb
Host smart-1755c41d-d7c1-4968-b0b3-03bafbf24888
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3316634145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3316634145
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.757487165
Short name T158
Test name
Test status
Simulation time 5971237167 ps
CPU time 181.49 seconds
Started Jan 14 02:53:25 PM PST 24
Finished Jan 14 02:56:28 PM PST 24
Peak memory 273380 kb
Host smart-5c878f6b-6acb-4c3f-9400-8e5834f8ac8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=757487165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.757487165
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3429669090
Short name T770
Test name
Test status
Simulation time 26292144 ps
CPU time 1.42 seconds
Started Jan 14 02:52:18 PM PST 24
Finished Jan 14 02:52:25 PM PST 24
Peak memory 235712 kb
Host smart-e584d7ae-f2d9-4811-851e-340bde9bdb3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3429669090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3429669090
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3734281936
Short name T175
Test name
Test status
Simulation time 6034555102 ps
CPU time 509.34 seconds
Started Jan 14 02:52:50 PM PST 24
Finished Jan 14 03:01:21 PM PST 24
Peak memory 269080 kb
Host smart-9bce72bb-a32f-4ed1-9b55-7ef0ef2c9c6b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734281936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3734281936
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3918961119
Short name T22
Test name
Test status
Simulation time 925342685 ps
CPU time 51.68 seconds
Started Jan 14 02:59:27 PM PST 24
Finished Jan 14 03:00:20 PM PST 24
Peak memory 254372 kb
Host smart-350e9112-f6b8-4b2d-8003-bbb77770502e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39189
61119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3918961119
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2132552521
Short name T70
Test name
Test status
Simulation time 1174430419 ps
CPU time 36.37 seconds
Started Jan 14 02:59:39 PM PST 24
Finished Jan 14 03:00:16 PM PST 24
Peak memory 248676 kb
Host smart-41ce03d7-f034-4bc5-afb1-d74db7595153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21325
52521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2132552521
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3620556249
Short name T303
Test name
Test status
Simulation time 171319794809 ps
CPU time 2162.61 seconds
Started Jan 14 02:59:43 PM PST 24
Finished Jan 14 03:35:46 PM PST 24
Peak memory 283184 kb
Host smart-228a9548-3b75-4e4f-be95-b739cf0978bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620556249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3620556249
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2660055681
Short name T301
Test name
Test status
Simulation time 19766333650 ps
CPU time 277.22 seconds
Started Jan 14 02:59:26 PM PST 24
Finished Jan 14 03:04:05 PM PST 24
Peak memory 256400 kb
Host smart-007eacc2-42cb-40a0-8c39-82a6854e0630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26600
55681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2660055681
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.4017176405
Short name T270
Test name
Test status
Simulation time 16033882213 ps
CPU time 1095.45 seconds
Started Jan 14 02:59:40 PM PST 24
Finished Jan 14 03:17:56 PM PST 24
Peak memory 273308 kb
Host smart-d1a4e675-9a30-4767-887e-bb8fa9f22108
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017176405 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.4017176405
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2489881234
Short name T48
Test name
Test status
Simulation time 40575109635 ps
CPU time 2440.7 seconds
Started Jan 14 02:59:39 PM PST 24
Finished Jan 14 03:40:21 PM PST 24
Peak memory 285492 kb
Host smart-debe6b68-cae6-441a-8cfe-6c6ec0617356
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489881234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2489881234
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.970625350
Short name T261
Test name
Test status
Simulation time 393531496 ps
CPU time 20.72 seconds
Started Jan 14 02:59:53 PM PST 24
Finished Jan 14 03:00:14 PM PST 24
Peak memory 254296 kb
Host smart-6574ea1b-b570-41f8-ab65-4cd20d70ddcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97062
5350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.970625350
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.318217621
Short name T359
Test name
Test status
Simulation time 40283093513 ps
CPU time 2474.67 seconds
Started Jan 14 03:00:23 PM PST 24
Finished Jan 14 03:41:39 PM PST 24
Peak memory 284944 kb
Host smart-0aba0910-8983-4be5-a7f7-41bd2ae161c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318217621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.318217621
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3331015049
Short name T345
Test name
Test status
Simulation time 16303560359 ps
CPU time 360.72 seconds
Started Jan 14 03:00:26 PM PST 24
Finished Jan 14 03:06:27 PM PST 24
Peak memory 247600 kb
Host smart-4906a2dc-45f2-48b8-bff8-59eef5f47194
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331015049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3331015049
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2284521625
Short name T290
Test name
Test status
Simulation time 375608898 ps
CPU time 27.62 seconds
Started Jan 14 03:00:33 PM PST 24
Finished Jan 14 03:01:02 PM PST 24
Peak memory 246932 kb
Host smart-d78dbc33-5df6-4555-ae91-8d8954b90a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22845
21625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2284521625
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.291797537
Short name T596
Test name
Test status
Simulation time 491141767 ps
CPU time 33.96 seconds
Started Jan 14 03:00:46 PM PST 24
Finished Jan 14 03:01:21 PM PST 24
Peak memory 255040 kb
Host smart-4e9ca9a6-edf7-419d-a23e-996ebf22c644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29179
7537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.291797537
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1546940316
Short name T362
Test name
Test status
Simulation time 346345919818 ps
CPU time 3166.95 seconds
Started Jan 14 03:01:22 PM PST 24
Finished Jan 14 03:54:10 PM PST 24
Peak memory 289036 kb
Host smart-d740643c-8527-4328-adc8-e47d042a24d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546940316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1546940316
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3892623151
Short name T41
Test name
Test status
Simulation time 21230720104 ps
CPU time 1381.24 seconds
Started Jan 14 02:59:48 PM PST 24
Finished Jan 14 03:22:50 PM PST 24
Peak memory 272232 kb
Host smart-13171492-a114-4188-b773-c4bbc3bb63ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892623151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3892623151
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3168123543
Short name T106
Test name
Test status
Simulation time 49464855612 ps
CPU time 3376.33 seconds
Started Jan 14 03:00:03 PM PST 24
Finished Jan 14 03:56:21 PM PST 24
Peak memory 289044 kb
Host smart-e4acf8c7-5b05-467b-a510-e0c7d802eca5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168123543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3168123543
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3874499792
Short name T176
Test name
Test status
Simulation time 2713546467 ps
CPU time 192.66 seconds
Started Jan 14 02:53:13 PM PST 24
Finished Jan 14 02:56:27 PM PST 24
Peak memory 257296 kb
Host smart-337550e8-0f43-4395-9ba7-d3a19328fb5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3874499792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3874499792
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.321747012
Short name T189
Test name
Test status
Simulation time 8872772235 ps
CPU time 668.3 seconds
Started Jan 14 02:52:25 PM PST 24
Finished Jan 14 03:03:37 PM PST 24
Peak memory 265408 kb
Host smart-4aab418c-d17f-43e7-a9d8-17131de5004f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321747012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.321747012
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2250791036
Short name T197
Test name
Test status
Simulation time 126629007 ps
CPU time 3.18 seconds
Started Jan 14 02:53:30 PM PST 24
Finished Jan 14 02:53:34 PM PST 24
Peak memory 236372 kb
Host smart-c74ba154-c2c6-4105-af77-ee237e3b2bff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2250791036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2250791036
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.461362755
Short name T14
Test name
Test status
Simulation time 39657598098 ps
CPU time 1050.9 seconds
Started Jan 14 02:58:49 PM PST 24
Finished Jan 14 03:16:22 PM PST 24
Peak memory 283012 kb
Host smart-c1b4ed77-cd68-4100-852b-ef50062448af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461362755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.461362755
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.4226058301
Short name T198
Test name
Test status
Simulation time 205021794 ps
CPU time 4.89 seconds
Started Jan 14 02:53:34 PM PST 24
Finished Jan 14 02:53:40 PM PST 24
Peak memory 236952 kb
Host smart-f43a3515-1ba7-45d8-8c5f-ccf819525c20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4226058301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.4226058301
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1975252781
Short name T199
Test name
Test status
Simulation time 339471367 ps
CPU time 38.54 seconds
Started Jan 14 02:52:36 PM PST 24
Finished Jan 14 02:53:16 PM PST 24
Peak memory 240420 kb
Host smart-3ce1e5dc-06b6-464d-ac0a-9afcb6d0d81c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1975252781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1975252781
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.415809041
Short name T192
Test name
Test status
Simulation time 1159237085 ps
CPU time 38.32 seconds
Started Jan 14 02:52:57 PM PST 24
Finished Jan 14 02:53:36 PM PST 24
Peak memory 240444 kb
Host smart-6c2e084f-fcaf-4ed7-b95a-a0f0763556ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=415809041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.415809041
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3375623513
Short name T193
Test name
Test status
Simulation time 133742196 ps
CPU time 3.06 seconds
Started Jan 14 02:53:02 PM PST 24
Finished Jan 14 02:53:06 PM PST 24
Peak memory 236508 kb
Host smart-aee8aed6-59e2-49a6-b69c-03d552e8a056
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3375623513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3375623513
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2844848704
Short name T201
Test name
Test status
Simulation time 58480571 ps
CPU time 2.15 seconds
Started Jan 14 02:52:47 PM PST 24
Finished Jan 14 02:52:50 PM PST 24
Peak memory 235624 kb
Host smart-fedd02b1-bc95-430e-9fa8-380ee9b26baa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2844848704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2844848704
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.488422159
Short name T195
Test name
Test status
Simulation time 314028572 ps
CPU time 40.65 seconds
Started Jan 14 02:52:49 PM PST 24
Finished Jan 14 02:53:30 PM PST 24
Peak memory 236620 kb
Host smart-b67fdb5e-63e3-4e62-ab51-f11d604b6150
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=488422159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.488422159
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.545733305
Short name T204
Test name
Test status
Simulation time 468662476 ps
CPU time 33.01 seconds
Started Jan 14 02:52:17 PM PST 24
Finished Jan 14 02:52:56 PM PST 24
Peak memory 248604 kb
Host smart-c2b71397-2d2c-424f-9407-248a7c0f9ed8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=545733305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.545733305
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1436615389
Short name T207
Test name
Test status
Simulation time 57141183 ps
CPU time 2.18 seconds
Started Jan 14 02:53:20 PM PST 24
Finished Jan 14 02:53:23 PM PST 24
Peak memory 236744 kb
Host smart-4b9380a1-e840-4080-973a-6deb5ec0d6e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1436615389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1436615389
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2350516490
Short name T206
Test name
Test status
Simulation time 22035709 ps
CPU time 2.58 seconds
Started Jan 14 02:53:26 PM PST 24
Finished Jan 14 02:53:29 PM PST 24
Peak memory 236500 kb
Host smart-ba7cdc00-104c-4ec7-a67b-6db92fa6c8ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2350516490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2350516490
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.481249196
Short name T203
Test name
Test status
Simulation time 153019020 ps
CPU time 2.99 seconds
Started Jan 14 02:53:26 PM PST 24
Finished Jan 14 02:53:30 PM PST 24
Peak memory 237032 kb
Host smart-b08186a0-204b-4fc3-b62f-e0d7a95c204f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=481249196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.481249196
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1770267362
Short name T194
Test name
Test status
Simulation time 59971208 ps
CPU time 2.85 seconds
Started Jan 14 02:52:52 PM PST 24
Finished Jan 14 02:52:56 PM PST 24
Peak memory 236492 kb
Host smart-3b45a557-f041-4eba-896c-ba1d302d887d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1770267362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1770267362
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1144226226
Short name T36
Test name
Test status
Simulation time 551793516 ps
CPU time 15.95 seconds
Started Jan 14 03:03:19 PM PST 24
Finished Jan 14 03:03:37 PM PST 24
Peak memory 248676 kb
Host smart-1f83c2ea-1650-4223-8b8d-a8683c505e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11442
26226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1144226226
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1290024178
Short name T184
Test name
Test status
Simulation time 568871703 ps
CPU time 59.74 seconds
Started Jan 14 02:52:17 PM PST 24
Finished Jan 14 02:53:23 PM PST 24
Peak memory 240312 kb
Host smart-b21c42d7-340c-4433-a7d5-b7b5d6c041c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1290024178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1290024178
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2692649079
Short name T813
Test name
Test status
Simulation time 17451889088 ps
CPU time 495.31 seconds
Started Jan 14 02:52:15 PM PST 24
Finished Jan 14 03:00:33 PM PST 24
Peak memory 236428 kb
Host smart-7ed00f89-48fc-4cd2-aec3-c968b41594b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2692649079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2692649079
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2113210827
Short name T809
Test name
Test status
Simulation time 341601874 ps
CPU time 3.77 seconds
Started Jan 14 02:52:17 PM PST 24
Finished Jan 14 02:52:26 PM PST 24
Peak memory 240332 kb
Host smart-12dbd2c7-39b1-4092-82c2-78b787f9b4b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2113210827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2113210827
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2993247967
Short name T821
Test name
Test status
Simulation time 38622141 ps
CPU time 3.03 seconds
Started Jan 14 02:52:17 PM PST 24
Finished Jan 14 02:52:26 PM PST 24
Peak memory 240496 kb
Host smart-7bf363b6-fa55-4fe8-9de5-7c77d0583ab7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993247967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2993247967
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.914946983
Short name T820
Test name
Test status
Simulation time 454332376 ps
CPU time 8.5 seconds
Started Jan 14 02:52:15 PM PST 24
Finished Jan 14 02:52:26 PM PST 24
Peak memory 235492 kb
Host smart-f28db958-4b78-4719-b410-953d0d69d58d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=914946983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.914946983
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.995837815
Short name T823
Test name
Test status
Simulation time 175275910 ps
CPU time 20.89 seconds
Started Jan 14 02:52:14 PM PST 24
Finished Jan 14 02:52:38 PM PST 24
Peak memory 240264 kb
Host smart-932450c7-1d65-4d54-8e21-758003ca97b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=995837815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.995837815
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3734327949
Short name T173
Test name
Test status
Simulation time 9819122587 ps
CPU time 177.33 seconds
Started Jan 14 02:52:17 PM PST 24
Finished Jan 14 02:55:20 PM PST 24
Peak memory 257180 kb
Host smart-8657f53f-14f3-40a5-a97b-00a97a3197a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3734327949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3734327949
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2258578892
Short name T760
Test name
Test status
Simulation time 43606675 ps
CPU time 6.17 seconds
Started Jan 14 02:52:16 PM PST 24
Finished Jan 14 02:52:28 PM PST 24
Peak memory 248732 kb
Host smart-b7b9bafd-c7ec-474f-829b-744a8ad097c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2258578892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2258578892
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.51143101
Short name T761
Test name
Test status
Simulation time 15867861309 ps
CPU time 295.01 seconds
Started Jan 14 02:52:27 PM PST 24
Finished Jan 14 02:57:24 PM PST 24
Peak memory 240504 kb
Host smart-a296ff25-e089-4198-8ef0-73304d4cc14d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=51143101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.51143101
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3767897174
Short name T29
Test name
Test status
Simulation time 3027307211 ps
CPU time 200.86 seconds
Started Jan 14 02:52:24 PM PST 24
Finished Jan 14 02:55:49 PM PST 24
Peak memory 236564 kb
Host smart-adb97fbc-6628-4680-a1b5-ce8d864646af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3767897174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3767897174
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1566875574
Short name T817
Test name
Test status
Simulation time 103578610 ps
CPU time 9.26 seconds
Started Jan 14 02:52:23 PM PST 24
Finished Jan 14 02:52:37 PM PST 24
Peak memory 240444 kb
Host smart-165cf3e6-de6a-4968-ad78-a6f74c679a81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1566875574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1566875574
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1383737210
Short name T147
Test name
Test status
Simulation time 61793621 ps
CPU time 7.32 seconds
Started Jan 14 02:52:24 PM PST 24
Finished Jan 14 02:52:36 PM PST 24
Peak memory 251520 kb
Host smart-e871dad4-599b-4d0d-b02b-a5fff6736a77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383737210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1383737210
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3603223229
Short name T212
Test name
Test status
Simulation time 197276442 ps
CPU time 4.99 seconds
Started Jan 14 02:52:23 PM PST 24
Finished Jan 14 02:52:32 PM PST 24
Peak memory 235476 kb
Host smart-42c9ca75-e2a1-4508-a90f-99cf074fc35c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3603223229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3603223229
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3248055673
Short name T804
Test name
Test status
Simulation time 9765852 ps
CPU time 1.58 seconds
Started Jan 14 02:52:22 PM PST 24
Finished Jan 14 02:52:26 PM PST 24
Peak memory 236500 kb
Host smart-10225e9f-7f02-4b2c-8f65-3351a1855cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3248055673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3248055673
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2023386271
Short name T218
Test name
Test status
Simulation time 266315451 ps
CPU time 21.86 seconds
Started Jan 14 02:52:25 PM PST 24
Finished Jan 14 02:52:51 PM PST 24
Peak memory 245736 kb
Host smart-e78164a6-e4ce-4428-835e-881e45bc2944
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2023386271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2023386271
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3220594188
Short name T754
Test name
Test status
Simulation time 729744354 ps
CPU time 12.84 seconds
Started Jan 14 02:52:23 PM PST 24
Finished Jan 14 02:52:40 PM PST 24
Peak memory 251928 kb
Host smart-969785e3-b2b4-4a2d-b61d-18fb95498446
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3220594188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3220594188
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3764083635
Short name T149
Test name
Test status
Simulation time 203148851 ps
CPU time 7.28 seconds
Started Jan 14 02:53:01 PM PST 24
Finished Jan 14 02:53:10 PM PST 24
Peak memory 243080 kb
Host smart-89a0f0d9-1ba1-4deb-b0ac-b3eb715bdc66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764083635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3764083635
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3511248098
Short name T219
Test name
Test status
Simulation time 109830932 ps
CPU time 5.91 seconds
Started Jan 14 02:53:02 PM PST 24
Finished Jan 14 02:53:09 PM PST 24
Peak memory 236500 kb
Host smart-a62c5437-ad0c-4bf8-b7a6-04bd1b3e62b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3511248098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3511248098
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3206136953
Short name T764
Test name
Test status
Simulation time 9114503 ps
CPU time 1.53 seconds
Started Jan 14 02:53:03 PM PST 24
Finished Jan 14 02:53:05 PM PST 24
Peak memory 235616 kb
Host smart-2234adad-31a8-408e-8b30-2e645e25cced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3206136953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3206136953
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.28062850
Short name T735
Test name
Test status
Simulation time 348980847 ps
CPU time 20.37 seconds
Started Jan 14 02:53:03 PM PST 24
Finished Jan 14 02:53:25 PM PST 24
Peak memory 243812 kb
Host smart-b8583f74-5ed4-4cce-b851-e9e0ec4eb394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=28062850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outs
tanding.28062850
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.658786647
Short name T166
Test name
Test status
Simulation time 50951975885 ps
CPU time 922.91 seconds
Started Jan 14 02:52:56 PM PST 24
Finished Jan 14 03:08:20 PM PST 24
Peak memory 265528 kb
Host smart-253d98ad-633a-4298-87f0-20faedce0f25
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658786647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.658786647
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2298434767
Short name T752
Test name
Test status
Simulation time 116843242 ps
CPU time 7.31 seconds
Started Jan 14 02:53:04 PM PST 24
Finished Jan 14 02:53:12 PM PST 24
Peak memory 248580 kb
Host smart-bfdd319f-bb76-4c33-9180-53843505f534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2298434767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2298434767
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2443455443
Short name T824
Test name
Test status
Simulation time 19261073 ps
CPU time 4.01 seconds
Started Jan 14 02:53:10 PM PST 24
Finished Jan 14 02:53:15 PM PST 24
Peak memory 248584 kb
Host smart-58a25f46-8830-42a6-928e-be65e7b3305f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443455443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2443455443
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.4273538093
Short name T834
Test name
Test status
Simulation time 60611177 ps
CPU time 5.24 seconds
Started Jan 14 02:53:09 PM PST 24
Finished Jan 14 02:53:15 PM PST 24
Peak memory 235336 kb
Host smart-23868a27-37a9-4251-bcde-7b81a7b5aa19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4273538093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.4273538093
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3007904544
Short name T841
Test name
Test status
Simulation time 181818095 ps
CPU time 27.62 seconds
Started Jan 14 02:53:02 PM PST 24
Finished Jan 14 02:53:31 PM PST 24
Peak memory 244692 kb
Host smart-feba69d8-6cbe-438b-b339-f7109e837f98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3007904544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3007904544
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.4247161276
Short name T156
Test name
Test status
Simulation time 8477624300 ps
CPU time 159.91 seconds
Started Jan 14 02:53:09 PM PST 24
Finished Jan 14 02:55:50 PM PST 24
Peak memory 265216 kb
Host smart-0880e911-1900-474f-9afc-f95f4089b6c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4247161276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.4247161276
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.850286013
Short name T186
Test name
Test status
Simulation time 95387076013 ps
CPU time 1461.56 seconds
Started Jan 14 02:53:04 PM PST 24
Finished Jan 14 03:17:27 PM PST 24
Peak memory 265264 kb
Host smart-6f2c5631-532f-48b8-8109-4324e360f84f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850286013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.850286013
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1555749734
Short name T818
Test name
Test status
Simulation time 775913530 ps
CPU time 12.38 seconds
Started Jan 14 02:53:01 PM PST 24
Finished Jan 14 02:53:14 PM PST 24
Peak memory 250940 kb
Host smart-971bc99c-92a6-4eeb-b208-467484fd6e88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1555749734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1555749734
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1937739925
Short name T151
Test name
Test status
Simulation time 36249381 ps
CPU time 4.33 seconds
Started Jan 14 02:53:12 PM PST 24
Finished Jan 14 02:53:18 PM PST 24
Peak memory 240492 kb
Host smart-89380ea0-aa3a-41f9-b1c5-fd1f1b0696c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937739925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1937739925
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2483904108
Short name T748
Test name
Test status
Simulation time 255892084 ps
CPU time 5.41 seconds
Started Jan 14 02:53:09 PM PST 24
Finished Jan 14 02:53:16 PM PST 24
Peak memory 238388 kb
Host smart-e1e638da-7593-423e-ad33-215f5be6f8d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2483904108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2483904108
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.453618356
Short name T839
Test name
Test status
Simulation time 11453359 ps
CPU time 1.23 seconds
Started Jan 14 02:53:09 PM PST 24
Finished Jan 14 02:53:11 PM PST 24
Peak memory 236500 kb
Host smart-3a0c4f65-cbc4-4c79-95fd-70eca998b452
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=453618356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.453618356
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2081154803
Short name T747
Test name
Test status
Simulation time 583543136 ps
CPU time 38.44 seconds
Started Jan 14 02:53:10 PM PST 24
Finished Jan 14 02:53:49 PM PST 24
Peak memory 243752 kb
Host smart-58f7f155-f2c7-4152-9ee2-872944e0d20a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2081154803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2081154803
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1288475146
Short name T187
Test name
Test status
Simulation time 34364125090 ps
CPU time 607.34 seconds
Started Jan 14 02:53:12 PM PST 24
Finished Jan 14 03:03:20 PM PST 24
Peak memory 265340 kb
Host smart-644558df-0307-45bc-b013-aeff6395189a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288475146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1288475146
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1691850925
Short name T793
Test name
Test status
Simulation time 161661888 ps
CPU time 11.37 seconds
Started Jan 14 02:53:11 PM PST 24
Finished Jan 14 02:53:24 PM PST 24
Peak memory 248696 kb
Host smart-7a5684ae-d96c-4bb1-9a5d-8622ebf5c2fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1691850925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1691850925
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1380931063
Short name T830
Test name
Test status
Simulation time 325032803 ps
CPU time 4.16 seconds
Started Jan 14 02:53:12 PM PST 24
Finished Jan 14 02:53:17 PM PST 24
Peak memory 237568 kb
Host smart-798370a2-282c-4dd3-a3b2-2d02044992b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380931063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1380931063
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.659633875
Short name T773
Test name
Test status
Simulation time 44741049 ps
CPU time 3.64 seconds
Started Jan 14 02:53:15 PM PST 24
Finished Jan 14 02:53:20 PM PST 24
Peak memory 236448 kb
Host smart-4a046f04-ee7e-4e6b-ae1a-b8199f02a74f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=659633875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.659633875
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2472047466
Short name T771
Test name
Test status
Simulation time 9999393 ps
CPU time 1.39 seconds
Started Jan 14 02:53:11 PM PST 24
Finished Jan 14 02:53:13 PM PST 24
Peak memory 235628 kb
Host smart-a993a2cc-7360-4521-ab85-0468dbfde76b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2472047466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2472047466
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.859356953
Short name T819
Test name
Test status
Simulation time 2774303353 ps
CPU time 43.41 seconds
Started Jan 14 02:53:09 PM PST 24
Finished Jan 14 02:53:54 PM PST 24
Peak memory 248712 kb
Host smart-6e7ebd86-17ad-4e72-9416-b9241d5e33cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=859356953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.859356953
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2005176828
Short name T170
Test name
Test status
Simulation time 6917872735 ps
CPU time 494.84 seconds
Started Jan 14 02:53:16 PM PST 24
Finished Jan 14 03:01:32 PM PST 24
Peak memory 265540 kb
Host smart-5b20d5ba-f488-4f6e-af33-73ed97f12f03
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005176828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2005176828
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.686486921
Short name T828
Test name
Test status
Simulation time 1022048203 ps
CPU time 17.3 seconds
Started Jan 14 02:53:11 PM PST 24
Finished Jan 14 02:53:29 PM PST 24
Peak memory 248732 kb
Host smart-9ade4d4b-c050-40f7-a46a-8ee95920a814
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=686486921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.686486921
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.985281766
Short name T146
Test name
Test status
Simulation time 562667011 ps
CPU time 21 seconds
Started Jan 14 02:53:15 PM PST 24
Finished Jan 14 02:53:37 PM PST 24
Peak memory 239436 kb
Host smart-52a4e599-54d7-4974-a8a7-33d31e181a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=985281766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.985281766
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1720004934
Short name T737
Test name
Test status
Simulation time 80225156 ps
CPU time 4.33 seconds
Started Jan 14 02:53:19 PM PST 24
Finished Jan 14 02:53:24 PM PST 24
Peak memory 256836 kb
Host smart-bc4f3e85-bc8f-4454-bcdb-a5604eee2829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720004934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1720004934
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.991081373
Short name T784
Test name
Test status
Simulation time 62258097 ps
CPU time 3.5 seconds
Started Jan 14 02:53:15 PM PST 24
Finished Jan 14 02:53:20 PM PST 24
Peak memory 236492 kb
Host smart-c77b056c-17af-4cc4-b798-50377f54f887
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=991081373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.991081373
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.727179771
Short name T763
Test name
Test status
Simulation time 7666054 ps
CPU time 1.43 seconds
Started Jan 14 02:53:17 PM PST 24
Finished Jan 14 02:53:19 PM PST 24
Peak memory 234708 kb
Host smart-c4ade65d-fb07-4fd8-94cf-0f54a7525199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=727179771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.727179771
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1949832000
Short name T781
Test name
Test status
Simulation time 371294387 ps
CPU time 25.96 seconds
Started Jan 14 02:53:15 PM PST 24
Finished Jan 14 02:53:42 PM PST 24
Peak memory 240372 kb
Host smart-b8cddbbc-72ef-481d-903d-c3a576eea096
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1949832000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1949832000
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3120519389
Short name T159
Test name
Test status
Simulation time 18517734737 ps
CPU time 161.5 seconds
Started Jan 14 02:53:11 PM PST 24
Finished Jan 14 02:55:53 PM PST 24
Peak memory 266300 kb
Host smart-e369e7d0-a09c-4eee-8c81-97fc0326a9d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3120519389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3120519389
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1637489851
Short name T163
Test name
Test status
Simulation time 2216023588 ps
CPU time 333.31 seconds
Started Jan 14 02:53:17 PM PST 24
Finished Jan 14 02:58:51 PM PST 24
Peak memory 265432 kb
Host smart-fedb1100-1197-4986-a388-dfebd35be7a2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637489851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1637489851
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3765432190
Short name T150
Test name
Test status
Simulation time 104176881 ps
CPU time 13.59 seconds
Started Jan 14 02:53:13 PM PST 24
Finished Jan 14 02:53:27 PM PST 24
Peak memory 248668 kb
Host smart-71d546b1-ea4a-4f13-864f-c4f5539ed7c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3765432190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3765432190
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2946117916
Short name T202
Test name
Test status
Simulation time 93938797 ps
CPU time 4.08 seconds
Started Jan 14 02:53:17 PM PST 24
Finished Jan 14 02:53:22 PM PST 24
Peak memory 235620 kb
Host smart-f5a6d975-3539-4ab6-8865-fb5a82b83f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2946117916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2946117916
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2839565703
Short name T833
Test name
Test status
Simulation time 43422968 ps
CPU time 4.73 seconds
Started Jan 14 02:53:19 PM PST 24
Finished Jan 14 02:53:25 PM PST 24
Peak memory 240508 kb
Host smart-fcd0e555-dc2c-48b7-aefd-7d3a2d4ae9b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839565703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2839565703
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1332692356
Short name T792
Test name
Test status
Simulation time 289709330 ps
CPU time 8.92 seconds
Started Jan 14 02:53:19 PM PST 24
Finished Jan 14 02:53:29 PM PST 24
Peak memory 236472 kb
Host smart-2448a3e6-7d79-4b0f-874c-63e818122e62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1332692356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1332692356
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1044869509
Short name T782
Test name
Test status
Simulation time 12038622 ps
CPU time 1.46 seconds
Started Jan 14 02:53:21 PM PST 24
Finished Jan 14 02:53:23 PM PST 24
Peak memory 236528 kb
Host smart-6680c41f-8d7a-448b-8b18-ee8d2f2d9bdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1044869509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1044869509
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1755562057
Short name T794
Test name
Test status
Simulation time 301122003 ps
CPU time 13.24 seconds
Started Jan 14 02:53:19 PM PST 24
Finished Jan 14 02:53:33 PM PST 24
Peak memory 244676 kb
Host smart-b872fee2-fa0a-4e25-bd7b-5ce34ff6e172
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1755562057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1755562057
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1124726690
Short name T183
Test name
Test status
Simulation time 14989832823 ps
CPU time 564.2 seconds
Started Jan 14 02:53:20 PM PST 24
Finished Jan 14 03:02:45 PM PST 24
Peak memory 268868 kb
Host smart-c8417ded-61c0-47cf-b9f2-dc6058af1591
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124726690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1124726690
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1157720626
Short name T734
Test name
Test status
Simulation time 310116691 ps
CPU time 9.22 seconds
Started Jan 14 02:53:20 PM PST 24
Finished Jan 14 02:53:30 PM PST 24
Peak memory 248048 kb
Host smart-45046196-86ad-44e2-8fb1-492a3f3e9d83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1157720626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1157720626
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1944418126
Short name T251
Test name
Test status
Simulation time 33753420 ps
CPU time 4.11 seconds
Started Jan 14 02:53:26 PM PST 24
Finished Jan 14 02:53:30 PM PST 24
Peak memory 240400 kb
Host smart-6aaac338-4cf6-4ce9-b7c4-3905df8d9428
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944418126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1944418126
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2716694226
Short name T838
Test name
Test status
Simulation time 177803161 ps
CPU time 7.95 seconds
Started Jan 14 02:53:20 PM PST 24
Finished Jan 14 02:53:29 PM PST 24
Peak memory 240372 kb
Host smart-9e690d80-2099-42d1-9b81-e664ff3954fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2716694226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2716694226
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1096734122
Short name T799
Test name
Test status
Simulation time 11979586 ps
CPU time 1.31 seconds
Started Jan 14 02:53:26 PM PST 24
Finished Jan 14 02:53:28 PM PST 24
Peak memory 235732 kb
Host smart-5c5ec8fb-b946-4efc-823e-97a1d7bd51fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1096734122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1096734122
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1219032186
Short name T31
Test name
Test status
Simulation time 453755626 ps
CPU time 11.68 seconds
Started Jan 14 02:53:25 PM PST 24
Finished Jan 14 02:53:37 PM PST 24
Peak memory 243752 kb
Host smart-d75d28ef-49e9-4449-b6c8-8ba6e1698b2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1219032186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1219032186
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2332673897
Short name T181
Test name
Test status
Simulation time 2731004613 ps
CPU time 200.54 seconds
Started Jan 14 02:53:19 PM PST 24
Finished Jan 14 02:56:41 PM PST 24
Peak memory 265580 kb
Host smart-5221e486-341a-497a-a60c-9598bd90b53c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2332673897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2332673897
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.96462102
Short name T191
Test name
Test status
Simulation time 337200258 ps
CPU time 9.57 seconds
Started Jan 14 02:53:19 PM PST 24
Finished Jan 14 02:53:30 PM PST 24
Peak memory 253672 kb
Host smart-7550eab9-6cec-4504-b357-2ce55f9fad79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=96462102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.96462102
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.192300864
Short name T776
Test name
Test status
Simulation time 70862075 ps
CPU time 6.55 seconds
Started Jan 14 02:53:30 PM PST 24
Finished Jan 14 02:53:37 PM PST 24
Peak memory 250736 kb
Host smart-1012bd34-fc41-4a41-8584-5528a2c60a85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192300864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.192300864
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3794074229
Short name T743
Test name
Test status
Simulation time 108589163 ps
CPU time 8.66 seconds
Started Jan 14 02:53:35 PM PST 24
Finished Jan 14 02:53:44 PM PST 24
Peak memory 235612 kb
Host smart-721c135b-7e3f-40fe-b9f2-815d80191be9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3794074229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3794074229
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2528842896
Short name T831
Test name
Test status
Simulation time 15174768 ps
CPU time 1.22 seconds
Started Jan 14 02:53:24 PM PST 24
Finished Jan 14 02:53:26 PM PST 24
Peak memory 236524 kb
Host smart-8ba1cd66-62aa-4eb5-a59d-b9ef9d5eb934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2528842896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2528842896
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.890115020
Short name T812
Test name
Test status
Simulation time 5247971510 ps
CPU time 22.71 seconds
Started Jan 14 02:53:33 PM PST 24
Finished Jan 14 02:53:57 PM PST 24
Peak memory 244516 kb
Host smart-09134ea8-8b0e-49b1-a66c-228d61fbc11f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=890115020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.890115020
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3249961084
Short name T188
Test name
Test status
Simulation time 28826648123 ps
CPU time 507.89 seconds
Started Jan 14 02:53:23 PM PST 24
Finished Jan 14 03:01:52 PM PST 24
Peak memory 268224 kb
Host smart-78028796-c147-4f07-83e3-949c5cdafbb4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249961084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3249961084
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2361406494
Short name T775
Test name
Test status
Simulation time 524043603 ps
CPU time 10.74 seconds
Started Jan 14 02:53:28 PM PST 24
Finished Jan 14 02:53:39 PM PST 24
Peak memory 248680 kb
Host smart-931f6270-4707-40a8-9035-e46e36888593
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2361406494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2361406494
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3597163650
Short name T825
Test name
Test status
Simulation time 75994339 ps
CPU time 4.06 seconds
Started Jan 14 02:53:29 PM PST 24
Finished Jan 14 02:53:33 PM PST 24
Peak memory 241152 kb
Host smart-8a52f2b2-a066-44a6-b140-ac52af5eaef3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597163650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3597163650
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1227559416
Short name T185
Test name
Test status
Simulation time 82757279 ps
CPU time 3.39 seconds
Started Jan 14 02:53:34 PM PST 24
Finished Jan 14 02:53:38 PM PST 24
Peak memory 236496 kb
Host smart-94a14255-7e8a-4ef3-87f0-f4bd91023f87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1227559416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1227559416
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2863808945
Short name T791
Test name
Test status
Simulation time 14408119 ps
CPU time 1.37 seconds
Started Jan 14 02:53:36 PM PST 24
Finished Jan 14 02:53:38 PM PST 24
Peak memory 235688 kb
Host smart-3cd1947f-3c43-4e8f-ba1a-ea1a4fe6eca1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2863808945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2863808945
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.239578775
Short name T840
Test name
Test status
Simulation time 519885992 ps
CPU time 36.89 seconds
Started Jan 14 02:53:36 PM PST 24
Finished Jan 14 02:54:14 PM PST 24
Peak memory 243856 kb
Host smart-37a7501e-8964-4105-aae2-11f70f1d794a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=239578775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.239578775
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4070971885
Short name T180
Test name
Test status
Simulation time 6504447714 ps
CPU time 527.91 seconds
Started Jan 14 02:53:31 PM PST 24
Finished Jan 14 03:02:19 PM PST 24
Peak memory 265472 kb
Host smart-c732d8d4-d7b7-4796-bc03-0b1f1cc5051d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070971885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.4070971885
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2122465638
Short name T756
Test name
Test status
Simulation time 450634973 ps
CPU time 18.62 seconds
Started Jan 14 02:53:35 PM PST 24
Finished Jan 14 02:53:54 PM PST 24
Peak memory 253880 kb
Host smart-14ba56e2-553e-42b8-8bd4-6d2f7e7a2ff1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2122465638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2122465638
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.196936805
Short name T789
Test name
Test status
Simulation time 46646523 ps
CPU time 5.34 seconds
Started Jan 14 02:53:34 PM PST 24
Finished Jan 14 02:53:40 PM PST 24
Peak memory 248700 kb
Host smart-29f2437e-6c51-4a50-8640-efa193ffdef3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196936805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.196936805
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1342063168
Short name T216
Test name
Test status
Simulation time 270704502 ps
CPU time 4.92 seconds
Started Jan 14 02:53:36 PM PST 24
Finished Jan 14 02:53:42 PM PST 24
Peak memory 236412 kb
Host smart-847f60db-0c7e-4f8d-9f3a-1f0e5f62710d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1342063168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1342063168
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2103863038
Short name T749
Test name
Test status
Simulation time 24881805 ps
CPU time 1.27 seconds
Started Jan 14 02:53:37 PM PST 24
Finished Jan 14 02:53:40 PM PST 24
Peak memory 235748 kb
Host smart-1d481778-9018-4f18-a677-3622674b7f51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2103863038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2103863038
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1513995451
Short name T788
Test name
Test status
Simulation time 4541062822 ps
CPU time 42.3 seconds
Started Jan 14 02:53:35 PM PST 24
Finished Jan 14 02:54:19 PM PST 24
Peak memory 243816 kb
Host smart-d57f9963-317f-4a7f-98d8-e0ed36043152
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1513995451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1513995451
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.874140729
Short name T182
Test name
Test status
Simulation time 2172414937 ps
CPU time 228.87 seconds
Started Jan 14 02:53:28 PM PST 24
Finished Jan 14 02:57:18 PM PST 24
Peak memory 265400 kb
Host smart-2f52ae7f-a681-4cd9-906d-d9e2b2e95c49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=874140729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.874140729
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3558860310
Short name T377
Test name
Test status
Simulation time 6658841134 ps
CPU time 659.57 seconds
Started Jan 14 02:53:35 PM PST 24
Finished Jan 14 03:04:35 PM PST 24
Peak memory 265340 kb
Host smart-96a57a06-a9f3-405b-9487-76508449396c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558860310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3558860310
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.687692507
Short name T832
Test name
Test status
Simulation time 201697798 ps
CPU time 8.17 seconds
Started Jan 14 02:53:40 PM PST 24
Finished Jan 14 02:53:49 PM PST 24
Peak memory 248708 kb
Host smart-d52b7a79-8570-4d2a-8f93-11dde9319b72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=687692507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.687692507
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4055183250
Short name T766
Test name
Test status
Simulation time 4555881877 ps
CPU time 148.17 seconds
Started Jan 14 02:52:38 PM PST 24
Finished Jan 14 02:55:08 PM PST 24
Peak memory 240468 kb
Host smart-7b50f839-7d83-4194-bb5b-aa132aa311b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4055183250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.4055183250
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.210492040
Short name T733
Test name
Test status
Simulation time 3336671356 ps
CPU time 213.95 seconds
Started Jan 14 02:52:34 PM PST 24
Finished Jan 14 02:56:09 PM PST 24
Peak memory 236564 kb
Host smart-b60527e0-76b1-4374-a973-76339be03c2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=210492040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.210492040
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.160684220
Short name T783
Test name
Test status
Simulation time 175924854 ps
CPU time 4.79 seconds
Started Jan 14 02:52:33 PM PST 24
Finished Jan 14 02:52:39 PM PST 24
Peak memory 240448 kb
Host smart-f55a842c-9ad0-451b-a686-58e13b48fc15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=160684220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.160684220
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2573654171
Short name T790
Test name
Test status
Simulation time 122144845 ps
CPU time 7 seconds
Started Jan 14 02:52:36 PM PST 24
Finished Jan 14 02:52:44 PM PST 24
Peak memory 256396 kb
Host smart-69a8affe-c358-4989-b6cf-51fb08e17dbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573654171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2573654171
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4216376139
Short name T837
Test name
Test status
Simulation time 94905634 ps
CPU time 7.92 seconds
Started Jan 14 02:52:35 PM PST 24
Finished Jan 14 02:52:44 PM PST 24
Peak memory 236356 kb
Host smart-10032aaa-4858-4e61-996c-b0768d5a2154
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4216376139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.4216376139
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1223516881
Short name T810
Test name
Test status
Simulation time 10949527 ps
CPU time 1.37 seconds
Started Jan 14 02:52:34 PM PST 24
Finished Jan 14 02:52:36 PM PST 24
Peak memory 236508 kb
Host smart-30b76a4e-f839-4e1e-8eec-fd8e8f380dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1223516881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1223516881
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3668633074
Short name T738
Test name
Test status
Simulation time 511805378 ps
CPU time 20.07 seconds
Started Jan 14 02:52:39 PM PST 24
Finished Jan 14 02:53:00 PM PST 24
Peak memory 239556 kb
Host smart-a969b44a-1290-47be-9d7c-279a25c25da2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3668633074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3668633074
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1376288087
Short name T167
Test name
Test status
Simulation time 7640366342 ps
CPU time 157.45 seconds
Started Jan 14 02:52:23 PM PST 24
Finished Jan 14 02:55:05 PM PST 24
Peak memory 265368 kb
Host smart-1213b4b5-772c-4ead-8a90-5f4d73b0bf31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1376288087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1376288087
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.101093256
Short name T758
Test name
Test status
Simulation time 69167058 ps
CPU time 9.65 seconds
Started Jan 14 02:52:25 PM PST 24
Finished Jan 14 02:52:38 PM PST 24
Peak memory 248688 kb
Host smart-c5de1b89-fc35-4b11-ae58-648f35eec2ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=101093256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.101093256
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2195768910
Short name T816
Test name
Test status
Simulation time 8577876 ps
CPU time 1.35 seconds
Started Jan 14 02:53:32 PM PST 24
Finished Jan 14 02:53:34 PM PST 24
Peak memory 236532 kb
Host smart-da59c235-7c60-4591-9da1-282dce149124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2195768910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2195768910
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3500855764
Short name T755
Test name
Test status
Simulation time 10164129 ps
CPU time 1.38 seconds
Started Jan 14 02:53:35 PM PST 24
Finished Jan 14 02:53:37 PM PST 24
Peak memory 236580 kb
Host smart-edb1755a-bae3-45cf-901c-182ba7a7ad77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3500855764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3500855764
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2230200577
Short name T795
Test name
Test status
Simulation time 7484676 ps
CPU time 1.33 seconds
Started Jan 14 02:53:37 PM PST 24
Finished Jan 14 02:53:40 PM PST 24
Peak memory 235684 kb
Host smart-c0a750ff-c4fc-46aa-9d65-40881ab96243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2230200577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2230200577
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1644511526
Short name T739
Test name
Test status
Simulation time 7138676 ps
CPU time 1.47 seconds
Started Jan 14 02:53:36 PM PST 24
Finished Jan 14 02:53:39 PM PST 24
Peak memory 234700 kb
Host smart-cd110afd-57d1-49c7-be93-e7728047beff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1644511526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1644511526
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.979302320
Short name T374
Test name
Test status
Simulation time 14783532 ps
CPU time 1.28 seconds
Started Jan 14 02:53:39 PM PST 24
Finished Jan 14 02:53:41 PM PST 24
Peak memory 236492 kb
Host smart-c3c2c7fd-9053-42bf-b0e3-ca7b35dca605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=979302320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.979302320
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2760704629
Short name T28
Test name
Test status
Simulation time 9597672 ps
CPU time 1.46 seconds
Started Jan 14 02:53:42 PM PST 24
Finished Jan 14 02:53:44 PM PST 24
Peak memory 235708 kb
Host smart-d4fe0f61-3706-4463-ae9a-293d1b874962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2760704629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2760704629
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3733046697
Short name T742
Test name
Test status
Simulation time 52301602 ps
CPU time 1.23 seconds
Started Jan 14 02:53:42 PM PST 24
Finished Jan 14 02:53:44 PM PST 24
Peak memory 234380 kb
Host smart-5c06ee50-aac3-4bbe-a44d-0fac9b994f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3733046697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3733046697
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.840527067
Short name T376
Test name
Test status
Simulation time 9878236 ps
CPU time 1.34 seconds
Started Jan 14 02:53:36 PM PST 24
Finished Jan 14 02:53:38 PM PST 24
Peak memory 236516 kb
Host smart-05b8fcab-fcb6-459d-befd-c167946b4147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=840527067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.840527067
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1411240381
Short name T836
Test name
Test status
Simulation time 8667424 ps
CPU time 1.47 seconds
Started Jan 14 02:53:39 PM PST 24
Finished Jan 14 02:53:41 PM PST 24
Peak memory 235636 kb
Host smart-82c7c70e-e838-44db-9c90-17ba337fc6e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1411240381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1411240381
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.553042011
Short name T796
Test name
Test status
Simulation time 7696353 ps
CPU time 1.4 seconds
Started Jan 14 02:53:35 PM PST 24
Finished Jan 14 02:53:37 PM PST 24
Peak memory 234660 kb
Host smart-43521a6f-8a8a-441a-8a60-345748f4d36d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=553042011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.553042011
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1399124251
Short name T741
Test name
Test status
Simulation time 4497921541 ps
CPU time 324.17 seconds
Started Jan 14 02:52:37 PM PST 24
Finished Jan 14 02:58:03 PM PST 24
Peak memory 238404 kb
Host smart-68750f22-049c-477b-837e-9129aa2ed7aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1399124251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1399124251
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4057282288
Short name T378
Test name
Test status
Simulation time 1575475556 ps
CPU time 118.76 seconds
Started Jan 14 02:52:42 PM PST 24
Finished Jan 14 02:54:41 PM PST 24
Peak memory 236492 kb
Host smart-2a5bd05d-3f78-4a0f-aacf-75683b3e79ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4057282288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.4057282288
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1487751725
Short name T25
Test name
Test status
Simulation time 23324768 ps
CPU time 3.64 seconds
Started Jan 14 02:52:39 PM PST 24
Finished Jan 14 02:52:44 PM PST 24
Peak memory 240424 kb
Host smart-b47de670-469e-4d55-95ed-ef35115c2f7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1487751725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1487751725
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.473825798
Short name T777
Test name
Test status
Simulation time 57893214 ps
CPU time 6.5 seconds
Started Jan 14 02:52:39 PM PST 24
Finished Jan 14 02:52:46 PM PST 24
Peak memory 248660 kb
Host smart-3b246ea0-aebe-4ffd-a137-e60963b24cb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473825798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.473825798
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.4120321728
Short name T26
Test name
Test status
Simulation time 113218983 ps
CPU time 7.57 seconds
Started Jan 14 02:52:44 PM PST 24
Finished Jan 14 02:52:53 PM PST 24
Peak memory 235628 kb
Host smart-9acdc722-8844-48fe-bf3f-fafcd334c6aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4120321728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.4120321728
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1975268318
Short name T797
Test name
Test status
Simulation time 52202215 ps
CPU time 1.38 seconds
Started Jan 14 02:52:40 PM PST 24
Finished Jan 14 02:52:42 PM PST 24
Peak memory 236452 kb
Host smart-07a34e14-9816-40a6-b15a-8fae18aba831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1975268318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1975268318
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.507942047
Short name T217
Test name
Test status
Simulation time 2077022793 ps
CPU time 39.06 seconds
Started Jan 14 02:52:38 PM PST 24
Finished Jan 14 02:53:18 PM PST 24
Peak memory 244656 kb
Host smart-3cf17fc5-ca27-4d8d-ab37-96526c82b2d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=507942047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.507942047
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.972687322
Short name T835
Test name
Test status
Simulation time 3030875923 ps
CPU time 82.52 seconds
Started Jan 14 02:52:35 PM PST 24
Finished Jan 14 02:53:59 PM PST 24
Peak memory 257204 kb
Host smart-19f81e38-ed91-49fc-92b2-aeaf80fb42be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=972687322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.972687322
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1961676267
Short name T190
Test name
Test status
Simulation time 194903229 ps
CPU time 6.46 seconds
Started Jan 14 02:52:34 PM PST 24
Finished Jan 14 02:52:42 PM PST 24
Peak memory 251592 kb
Host smart-be2d32c4-b106-42c1-bf03-33dc8f329a8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1961676267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1961676267
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.776478011
Short name T806
Test name
Test status
Simulation time 7545681 ps
CPU time 1.51 seconds
Started Jan 14 02:53:36 PM PST 24
Finished Jan 14 02:53:38 PM PST 24
Peak memory 236468 kb
Host smart-68afe0ee-519f-4cde-9db0-99b0e26cf3c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=776478011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.776478011
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4034850222
Short name T373
Test name
Test status
Simulation time 12054804 ps
CPU time 1.48 seconds
Started Jan 14 02:53:37 PM PST 24
Finished Jan 14 02:53:39 PM PST 24
Peak memory 235616 kb
Host smart-98c1b0ff-9d46-4e07-99aa-fc58b9a7c345
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4034850222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.4034850222
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.4035975098
Short name T808
Test name
Test status
Simulation time 12055529 ps
CPU time 1.45 seconds
Started Jan 14 02:53:43 PM PST 24
Finished Jan 14 02:53:45 PM PST 24
Peak memory 235664 kb
Host smart-3a0b56a8-f04f-4ae8-a906-d645f72772ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4035975098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.4035975098
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2193718429
Short name T372
Test name
Test status
Simulation time 8183044 ps
CPU time 1.47 seconds
Started Jan 14 02:53:42 PM PST 24
Finished Jan 14 02:53:44 PM PST 24
Peak memory 236484 kb
Host smart-fcd5daaa-2189-4a04-ba3e-b3ed2f90e5ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2193718429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2193718429
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2359672807
Short name T805
Test name
Test status
Simulation time 6815111 ps
CPU time 1.49 seconds
Started Jan 14 02:53:40 PM PST 24
Finished Jan 14 02:53:42 PM PST 24
Peak memory 235660 kb
Host smart-0798fe55-a1f2-4ae5-bb7c-2f45dd6690c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2359672807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2359672807
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.999140189
Short name T209
Test name
Test status
Simulation time 13058167 ps
CPU time 1.31 seconds
Started Jan 14 02:53:40 PM PST 24
Finished Jan 14 02:53:42 PM PST 24
Peak memory 236508 kb
Host smart-d0a04e53-ed33-40a1-b8d2-897a7f17f478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=999140189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.999140189
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2797399211
Short name T827
Test name
Test status
Simulation time 8341729 ps
CPU time 1.36 seconds
Started Jan 14 02:53:49 PM PST 24
Finished Jan 14 02:53:52 PM PST 24
Peak memory 235764 kb
Host smart-d17b76c3-65d0-492b-9984-8b8d41ce6bf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2797399211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2797399211
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.640180460
Short name T800
Test name
Test status
Simulation time 17229484 ps
CPU time 1.37 seconds
Started Jan 14 02:53:48 PM PST 24
Finished Jan 14 02:53:51 PM PST 24
Peak memory 236508 kb
Host smart-9dd5045a-86ed-4ef2-8533-881901a1de76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=640180460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.640180460
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.74976621
Short name T375
Test name
Test status
Simulation time 13567288 ps
CPU time 1.22 seconds
Started Jan 14 02:53:49 PM PST 24
Finished Jan 14 02:53:51 PM PST 24
Peak memory 235624 kb
Host smart-204db3f6-8c28-450e-85a6-d42e8f1040e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=74976621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.74976621
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.452302894
Short name T786
Test name
Test status
Simulation time 547578596 ps
CPU time 73.23 seconds
Started Jan 14 02:52:50 PM PST 24
Finished Jan 14 02:54:05 PM PST 24
Peak memory 240452 kb
Host smart-d8cae594-a87b-4f6e-a7ba-16cfcc88a963
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=452302894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.452302894
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2624565048
Short name T740
Test name
Test status
Simulation time 8170367881 ps
CPU time 101.67 seconds
Started Jan 14 02:52:51 PM PST 24
Finished Jan 14 02:54:34 PM PST 24
Peak memory 236552 kb
Host smart-5fd474e8-5433-4603-8c48-58848c75132a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2624565048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2624565048
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2734731724
Short name T772
Test name
Test status
Simulation time 203843659 ps
CPU time 4.83 seconds
Started Jan 14 02:52:51 PM PST 24
Finished Jan 14 02:52:57 PM PST 24
Peak memory 240452 kb
Host smart-56d8b7df-8356-489d-b8af-e66cda72131f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2734731724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2734731724
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1366304562
Short name T750
Test name
Test status
Simulation time 55765820 ps
CPU time 7.37 seconds
Started Jan 14 02:52:51 PM PST 24
Finished Jan 14 02:53:00 PM PST 24
Peak memory 256128 kb
Host smart-06d285ba-d79b-490e-8998-9935e42d2367
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366304562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1366304562
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3027881315
Short name T210
Test name
Test status
Simulation time 181613927 ps
CPU time 7.25 seconds
Started Jan 14 02:52:45 PM PST 24
Finished Jan 14 02:52:53 PM PST 24
Peak memory 235620 kb
Host smart-cbe05bcf-c7b6-49b7-8a02-4c325414131f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3027881315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3027881315
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2965745956
Short name T768
Test name
Test status
Simulation time 21478410 ps
CPU time 1.35 seconds
Started Jan 14 02:52:47 PM PST 24
Finished Jan 14 02:52:49 PM PST 24
Peak memory 236516 kb
Host smart-45ea2686-589b-453d-95ae-df23a3a6e193
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2965745956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2965745956
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3474654059
Short name T803
Test name
Test status
Simulation time 1477239429 ps
CPU time 27.22 seconds
Started Jan 14 02:52:38 PM PST 24
Finished Jan 14 02:53:06 PM PST 24
Peak memory 244696 kb
Host smart-e7b41f5d-a21f-49bf-af2e-06ea4689c032
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3474654059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3474654059
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.75624108
Short name T172
Test name
Test status
Simulation time 5583684897 ps
CPU time 387.17 seconds
Started Jan 14 02:52:43 PM PST 24
Finished Jan 14 02:59:11 PM PST 24
Peak memory 273552 kb
Host smart-95e5a545-35d1-41a7-b773-f20e5bd3e785
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=75624108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors
.75624108
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.861166644
Short name T152
Test name
Test status
Simulation time 4803188212 ps
CPU time 358.86 seconds
Started Jan 14 02:52:41 PM PST 24
Finished Jan 14 02:58:41 PM PST 24
Peak memory 265468 kb
Host smart-2b5dfc14-7a98-4783-a530-c3c34893f5fe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861166644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.861166644
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3060038003
Short name T736
Test name
Test status
Simulation time 66432381 ps
CPU time 9.39 seconds
Started Jan 14 02:52:41 PM PST 24
Finished Jan 14 02:52:52 PM PST 24
Peak memory 252948 kb
Host smart-e9b8dd39-2aec-44cb-b341-5c3b9a0dbdc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3060038003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3060038003
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2652379826
Short name T814
Test name
Test status
Simulation time 25104064 ps
CPU time 1.38 seconds
Started Jan 14 02:53:46 PM PST 24
Finished Jan 14 02:53:48 PM PST 24
Peak memory 235616 kb
Host smart-f8ff44af-015f-4d8b-a25b-3cf71bb14417
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2652379826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2652379826
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3064213465
Short name T787
Test name
Test status
Simulation time 19477824 ps
CPU time 1.44 seconds
Started Jan 14 02:53:49 PM PST 24
Finished Jan 14 02:53:51 PM PST 24
Peak memory 236480 kb
Host smart-86f474ab-6c5a-492d-b9eb-983675568883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3064213465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3064213465
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.4273871796
Short name T769
Test name
Test status
Simulation time 25053530 ps
CPU time 1.45 seconds
Started Jan 14 02:53:51 PM PST 24
Finished Jan 14 02:53:54 PM PST 24
Peak memory 236496 kb
Host smart-86913265-06b8-4b5d-b60a-eec3169e69f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4273871796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.4273871796
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2564942482
Short name T213
Test name
Test status
Simulation time 10999454 ps
CPU time 1.31 seconds
Started Jan 14 02:53:46 PM PST 24
Finished Jan 14 02:53:49 PM PST 24
Peak memory 234728 kb
Host smart-663cd1b4-7226-45c8-be99-b3c4ad888090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2564942482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2564942482
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1259447694
Short name T822
Test name
Test status
Simulation time 11974806 ps
CPU time 1.3 seconds
Started Jan 14 02:53:48 PM PST 24
Finished Jan 14 02:53:50 PM PST 24
Peak memory 236380 kb
Host smart-8a6d5f72-396e-4dbd-a6c5-b35125956292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1259447694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1259447694
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.977560958
Short name T815
Test name
Test status
Simulation time 22048912 ps
CPU time 1.43 seconds
Started Jan 14 02:53:47 PM PST 24
Finished Jan 14 02:53:49 PM PST 24
Peak memory 235768 kb
Host smart-35bd311b-b854-4daf-bd3f-6a23288c1a76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=977560958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.977560958
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2063954639
Short name T24
Test name
Test status
Simulation time 8149846 ps
CPU time 1.51 seconds
Started Jan 14 02:53:47 PM PST 24
Finished Jan 14 02:53:49 PM PST 24
Peak memory 235640 kb
Host smart-491be8da-99e3-4efb-a5eb-eac98f4d6446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2063954639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2063954639
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2692667282
Short name T762
Test name
Test status
Simulation time 10906826 ps
CPU time 1.28 seconds
Started Jan 14 02:53:48 PM PST 24
Finished Jan 14 02:53:51 PM PST 24
Peak memory 236580 kb
Host smart-f9922353-4f91-4d4b-97c7-850522380dc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2692667282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2692667282
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3107106926
Short name T774
Test name
Test status
Simulation time 9179438 ps
CPU time 1.49 seconds
Started Jan 14 02:53:42 PM PST 24
Finished Jan 14 02:53:44 PM PST 24
Peak memory 235668 kb
Host smart-556d7d90-fa3c-41ec-871d-62e01ae625c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3107106926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3107106926
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.786974909
Short name T751
Test name
Test status
Simulation time 12273351 ps
CPU time 1.64 seconds
Started Jan 14 02:53:41 PM PST 24
Finished Jan 14 02:53:43 PM PST 24
Peak memory 236516 kb
Host smart-92628b0a-a757-4710-a6db-157eee1e1d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=786974909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.786974909
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2970961646
Short name T767
Test name
Test status
Simulation time 276276674 ps
CPU time 7.46 seconds
Started Jan 14 02:52:51 PM PST 24
Finished Jan 14 02:52:59 PM PST 24
Peak memory 243668 kb
Host smart-a1a1a605-0b56-464f-b900-7f2338e5a43d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970961646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2970961646
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3044968174
Short name T759
Test name
Test status
Simulation time 398325974 ps
CPU time 4.08 seconds
Started Jan 14 02:52:52 PM PST 24
Finished Jan 14 02:52:58 PM PST 24
Peak memory 239288 kb
Host smart-9422b30c-7f66-4ec5-b0a3-f6502992e3f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3044968174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3044968174
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4201379864
Short name T829
Test name
Test status
Simulation time 10356276 ps
CPU time 1.37 seconds
Started Jan 14 02:52:53 PM PST 24
Finished Jan 14 02:52:55 PM PST 24
Peak memory 234664 kb
Host smart-a50772e1-9c6f-4dae-bd79-36b49e3c1513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4201379864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.4201379864
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3986105123
Short name T780
Test name
Test status
Simulation time 1052255993 ps
CPU time 35.44 seconds
Started Jan 14 02:52:49 PM PST 24
Finished Jan 14 02:53:26 PM PST 24
Peak memory 248664 kb
Host smart-2caa430f-824c-4a7c-86cc-0a758bdb4c80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3986105123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3986105123
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3308683060
Short name T154
Test name
Test status
Simulation time 2082890638 ps
CPU time 172.58 seconds
Started Jan 14 02:52:41 PM PST 24
Finished Jan 14 02:55:35 PM PST 24
Peak memory 265324 kb
Host smart-5dcf3950-2ee4-4ebe-8511-12d7add73bc9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3308683060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3308683060
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.316338422
Short name T843
Test name
Test status
Simulation time 1113584183 ps
CPU time 21.54 seconds
Started Jan 14 02:52:39 PM PST 24
Finished Jan 14 02:53:02 PM PST 24
Peak memory 248220 kb
Host smart-9d7dc145-fc91-401d-9485-3e4af726132e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=316338422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.316338422
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.456067618
Short name T196
Test name
Test status
Simulation time 201755779 ps
CPU time 2.93 seconds
Started Jan 14 02:52:42 PM PST 24
Finished Jan 14 02:52:46 PM PST 24
Peak memory 236484 kb
Host smart-4d025ee6-79a3-4b24-9315-1613f2572ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=456067618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.456067618
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.26993541
Short name T211
Test name
Test status
Simulation time 102840718 ps
CPU time 6.35 seconds
Started Jan 14 02:52:50 PM PST 24
Finished Jan 14 02:52:57 PM PST 24
Peak memory 250480 kb
Host smart-369bffdb-47ec-4c56-aee7-a7796c1f9d42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26993541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.alert_handler_csr_mem_rw_with_rand_reset.26993541
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.629649131
Short name T221
Test name
Test status
Simulation time 61294748 ps
CPU time 4.77 seconds
Started Jan 14 02:52:52 PM PST 24
Finished Jan 14 02:52:58 PM PST 24
Peak memory 235612 kb
Host smart-5baf98c5-17ea-4c0c-b36f-6ddf6c7d9c88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=629649131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.629649131
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2745012576
Short name T798
Test name
Test status
Simulation time 44191754 ps
CPU time 1.35 seconds
Started Jan 14 02:52:52 PM PST 24
Finished Jan 14 02:52:54 PM PST 24
Peak memory 236484 kb
Host smart-91794329-5e75-4275-a86b-ca2c6381cef1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2745012576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2745012576
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3358876461
Short name T753
Test name
Test status
Simulation time 167217916 ps
CPU time 26.15 seconds
Started Jan 14 02:52:50 PM PST 24
Finished Jan 14 02:53:17 PM PST 24
Peak memory 244684 kb
Host smart-6093c3ef-77db-4e98-a9b7-ee1444952807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3358876461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3358876461
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3788782399
Short name T174
Test name
Test status
Simulation time 2169363956 ps
CPU time 150.83 seconds
Started Jan 14 02:52:53 PM PST 24
Finished Jan 14 02:55:25 PM PST 24
Peak memory 257196 kb
Host smart-34ef53a2-ad4e-420e-b9be-9a004d51d1ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3788782399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3788782399
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.638057111
Short name T160
Test name
Test status
Simulation time 8594623858 ps
CPU time 641.5 seconds
Started Jan 14 02:52:53 PM PST 24
Finished Jan 14 03:03:35 PM PST 24
Peak memory 273148 kb
Host smart-442bc24c-b359-4903-a883-4ca0aeffdc53
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638057111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.638057111
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.809435860
Short name T778
Test name
Test status
Simulation time 389069771 ps
CPU time 13.97 seconds
Started Jan 14 02:52:55 PM PST 24
Finished Jan 14 02:53:10 PM PST 24
Peak memory 248724 kb
Host smart-5280c49b-aa81-4c15-b5f9-2ebb7701c80d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=809435860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.809435860
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2608516071
Short name T744
Test name
Test status
Simulation time 114169936 ps
CPU time 6.7 seconds
Started Jan 14 02:52:59 PM PST 24
Finished Jan 14 02:53:07 PM PST 24
Peak memory 243616 kb
Host smart-d8da27a1-ddcf-45ef-9ac1-c39d9c2efaa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608516071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2608516071
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1225504870
Short name T807
Test name
Test status
Simulation time 112149238 ps
CPU time 5.32 seconds
Started Jan 14 02:52:51 PM PST 24
Finished Jan 14 02:52:58 PM PST 24
Peak memory 236484 kb
Host smart-fae12a4c-b695-4f36-9a68-f5d5d4fd9944
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1225504870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1225504870
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3596917202
Short name T30
Test name
Test status
Simulation time 15631492 ps
CPU time 1.32 seconds
Started Jan 14 02:52:53 PM PST 24
Finished Jan 14 02:52:55 PM PST 24
Peak memory 234476 kb
Host smart-e2f2b935-7628-4fcf-8595-b98ef4fd7112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3596917202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3596917202
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3807014479
Short name T801
Test name
Test status
Simulation time 679498468 ps
CPU time 27.1 seconds
Started Jan 14 02:52:59 PM PST 24
Finished Jan 14 02:53:27 PM PST 24
Peak memory 239892 kb
Host smart-23919b5e-6029-4b81-8b8c-55b407ff27b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3807014479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3807014479
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3133941730
Short name T779
Test name
Test status
Simulation time 50696995 ps
CPU time 7.19 seconds
Started Jan 14 02:52:50 PM PST 24
Finished Jan 14 02:52:58 PM PST 24
Peak memory 248312 kb
Host smart-e8d59618-6e07-4666-bd53-38ce067980fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3133941730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3133941730
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3201420745
Short name T757
Test name
Test status
Simulation time 656329518 ps
CPU time 6.74 seconds
Started Jan 14 02:52:56 PM PST 24
Finished Jan 14 02:53:04 PM PST 24
Peak memory 251512 kb
Host smart-33a41112-5227-4e09-a750-1e6ac2293142
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201420745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3201420745
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1655401222
Short name T842
Test name
Test status
Simulation time 105559931 ps
CPU time 5.06 seconds
Started Jan 14 02:52:57 PM PST 24
Finished Jan 14 02:53:03 PM PST 24
Peak memory 235612 kb
Host smart-7f0b5095-aac9-4e8e-95f6-2706b6d35fbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1655401222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1655401222
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2781412769
Short name T811
Test name
Test status
Simulation time 12921280 ps
CPU time 1.34 seconds
Started Jan 14 02:52:56 PM PST 24
Finished Jan 14 02:52:59 PM PST 24
Peak memory 236480 kb
Host smart-f19e4ca2-2cf4-44a6-b7b1-8f878fd2428b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2781412769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2781412769
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.390676187
Short name T785
Test name
Test status
Simulation time 315261008 ps
CPU time 26.04 seconds
Started Jan 14 02:52:58 PM PST 24
Finished Jan 14 02:53:25 PM PST 24
Peak memory 244684 kb
Host smart-981eb534-d6ec-4a0d-870f-020a8b73ce70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=390676187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.390676187
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1443084917
Short name T168
Test name
Test status
Simulation time 1984018064 ps
CPU time 155.16 seconds
Started Jan 14 02:52:54 PM PST 24
Finished Jan 14 02:55:30 PM PST 24
Peak memory 257088 kb
Host smart-7e2c3cfc-d4b5-45d6-abb0-af7c250d12bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1443084917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1443084917
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2449842988
Short name T802
Test name
Test status
Simulation time 130779718 ps
CPU time 20.93 seconds
Started Jan 14 02:52:59 PM PST 24
Finished Jan 14 02:53:21 PM PST 24
Peak memory 247960 kb
Host smart-9d7d72b6-83bb-468d-b064-b4b9e1557f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2449842988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2449842988
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3331389408
Short name T205
Test name
Test status
Simulation time 1168049997 ps
CPU time 39.39 seconds
Started Jan 14 02:52:56 PM PST 24
Finished Jan 14 02:53:36 PM PST 24
Peak memory 240472 kb
Host smart-876cece9-fad1-4fcb-bb8c-06c28dc8ea41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3331389408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3331389408
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3107701651
Short name T746
Test name
Test status
Simulation time 80207920 ps
CPU time 5.38 seconds
Started Jan 14 02:52:56 PM PST 24
Finished Jan 14 02:53:02 PM PST 24
Peak memory 252532 kb
Host smart-73dd4c81-c44c-4c84-8506-4844f80d311f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107701651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3107701651
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2309714164
Short name T220
Test name
Test status
Simulation time 182652677 ps
CPU time 5.13 seconds
Started Jan 14 02:52:56 PM PST 24
Finished Jan 14 02:53:02 PM PST 24
Peak memory 236484 kb
Host smart-94350f8c-df92-4556-a32e-ab8dfcb60366
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2309714164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2309714164
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2805736409
Short name T826
Test name
Test status
Simulation time 9885206 ps
CPU time 1.26 seconds
Started Jan 14 02:53:00 PM PST 24
Finished Jan 14 02:53:02 PM PST 24
Peak memory 234708 kb
Host smart-aec953ff-4a71-4ace-9128-fdf73dc9d629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2805736409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2805736409
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2745114532
Short name T745
Test name
Test status
Simulation time 522637365 ps
CPU time 17.06 seconds
Started Jan 14 02:52:56 PM PST 24
Finished Jan 14 02:53:14 PM PST 24
Peak memory 243708 kb
Host smart-73665960-fcb3-425a-bc5b-4e60cd923ab8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2745114532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2745114532
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1465325723
Short name T171
Test name
Test status
Simulation time 1502419587 ps
CPU time 86.6 seconds
Started Jan 14 02:52:58 PM PST 24
Finished Jan 14 02:54:26 PM PST 24
Peak memory 257128 kb
Host smart-50ed5f51-e2d8-43d8-9539-1c670406e7cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1465325723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1465325723
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.275688517
Short name T765
Test name
Test status
Simulation time 81081278 ps
CPU time 9.48 seconds
Started Jan 14 02:52:56 PM PST 24
Finished Jan 14 02:53:07 PM PST 24
Peak memory 248692 kb
Host smart-8c79887f-f04e-4a0c-904c-b2293acf052d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=275688517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.275688517
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3182390558
Short name T110
Test name
Test status
Simulation time 45612356676 ps
CPU time 2803.49 seconds
Started Jan 14 02:58:42 PM PST 24
Finished Jan 14 03:45:27 PM PST 24
Peak memory 286740 kb
Host smart-ccf5f418-6054-4e0e-b303-48851cdb2440
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182390558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3182390558
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3082588867
Short name T392
Test name
Test status
Simulation time 453995886 ps
CPU time 7.51 seconds
Started Jan 14 02:58:45 PM PST 24
Finished Jan 14 02:58:55 PM PST 24
Peak memory 240380 kb
Host smart-b0774043-dcdd-439d-b949-b8d50d3d01de
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3082588867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3082588867
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3674642637
Short name T615
Test name
Test status
Simulation time 5852166861 ps
CPU time 188.53 seconds
Started Jan 14 02:58:45 PM PST 24
Finished Jan 14 03:01:56 PM PST 24
Peak memory 256404 kb
Host smart-e7f68382-1441-4d38-a95d-893fc2d9842c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36746
42637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3674642637
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.698462131
Short name T673
Test name
Test status
Simulation time 2291853714 ps
CPU time 24.9 seconds
Started Jan 14 02:58:46 PM PST 24
Finished Jan 14 02:59:13 PM PST 24
Peak memory 254316 kb
Host smart-22941f5a-ad1d-48ac-96d4-051b8d07f78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69846
2131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.698462131
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.4011010960
Short name T726
Test name
Test status
Simulation time 11785258594 ps
CPU time 1224.56 seconds
Started Jan 14 02:58:47 PM PST 24
Finished Jan 14 03:19:13 PM PST 24
Peak memory 289116 kb
Host smart-14632237-fc57-4e9c-9da9-08379b655bec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011010960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.4011010960
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1815260174
Short name T665
Test name
Test status
Simulation time 204706276 ps
CPU time 22.43 seconds
Started Jan 14 02:58:45 PM PST 24
Finished Jan 14 02:59:10 PM PST 24
Peak memory 255448 kb
Host smart-896ebf91-dbd6-4cd7-a17f-91c405141ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18152
60174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1815260174
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.750877721
Short name T603
Test name
Test status
Simulation time 1303197651 ps
CPU time 67.56 seconds
Started Jan 14 02:58:45 PM PST 24
Finished Jan 14 02:59:54 PM PST 24
Peak memory 248004 kb
Host smart-b3ac97ec-f9ff-494e-b3c4-d9f4cb80171d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75087
7721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.750877721
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2899181541
Short name T10
Test name
Test status
Simulation time 465172588 ps
CPU time 27.64 seconds
Started Jan 14 02:58:46 PM PST 24
Finished Jan 14 02:59:15 PM PST 24
Peak memory 264344 kb
Host smart-0217e595-481e-4daf-b588-8ce631c543a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2899181541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2899181541
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.643874115
Short name T505
Test name
Test status
Simulation time 539661987 ps
CPU time 17.28 seconds
Started Jan 14 02:58:41 PM PST 24
Finished Jan 14 02:59:00 PM PST 24
Peak memory 253544 kb
Host smart-d65dd1a8-58a6-4393-8792-9af03c5362fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64387
4115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.643874115
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.743678574
Short name T715
Test name
Test status
Simulation time 2807689977 ps
CPU time 46.51 seconds
Started Jan 14 02:58:46 PM PST 24
Finished Jan 14 02:59:34 PM PST 24
Peak memory 248884 kb
Host smart-4f3c2d94-f5f5-4b51-9a55-d429493f1861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74367
8574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.743678574
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2376714597
Short name T63
Test name
Test status
Simulation time 372683710473 ps
CPU time 3723.69 seconds
Started Jan 14 02:58:43 PM PST 24
Finished Jan 14 04:00:49 PM PST 24
Peak memory 305808 kb
Host smart-c6a97620-8508-43f1-bf2a-2c80d9974112
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376714597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2376714597
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1918039026
Short name T215
Test name
Test status
Simulation time 39567080601 ps
CPU time 3406.87 seconds
Started Jan 14 02:58:47 PM PST 24
Finished Jan 14 03:55:36 PM PST 24
Peak memory 322656 kb
Host smart-41f06f00-14de-45f0-a79b-f3aec3068751
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918039026 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1918039026
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.406208283
Short name T223
Test name
Test status
Simulation time 258858627 ps
CPU time 3.02 seconds
Started Jan 14 02:58:46 PM PST 24
Finished Jan 14 02:58:51 PM PST 24
Peak memory 248816 kb
Host smart-400e48c6-0a30-4733-9f74-c6764220ee5f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=406208283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.406208283
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.402227034
Short name T319
Test name
Test status
Simulation time 14086734158 ps
CPU time 1410.22 seconds
Started Jan 14 02:58:50 PM PST 24
Finished Jan 14 03:22:22 PM PST 24
Peak memory 289088 kb
Host smart-8b26c6f4-2216-4a04-81fb-1eea9513ffb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402227034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.402227034
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2160974038
Short name T633
Test name
Test status
Simulation time 164808754 ps
CPU time 10.2 seconds
Started Jan 14 02:58:47 PM PST 24
Finished Jan 14 02:58:59 PM PST 24
Peak memory 240428 kb
Host smart-acf08c53-8d49-4937-9832-56fef33f028b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2160974038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2160974038
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.25788544
Short name T541
Test name
Test status
Simulation time 1379085976 ps
CPU time 26.01 seconds
Started Jan 14 02:58:42 PM PST 24
Finished Jan 14 02:59:10 PM PST 24
Peak memory 248652 kb
Host smart-339b3f78-71c1-461f-bf12-9dacd42e3af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25788
544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.25788544
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3953768104
Short name T90
Test name
Test status
Simulation time 1112255690 ps
CPU time 22.15 seconds
Started Jan 14 02:58:40 PM PST 24
Finished Jan 14 02:59:03 PM PST 24
Peak memory 255188 kb
Host smart-8fe16018-7dc9-4dfa-8077-934721f527d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39537
68104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3953768104
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.4188659924
Short name T342
Test name
Test status
Simulation time 238317445678 ps
CPU time 2578.09 seconds
Started Jan 14 02:58:45 PM PST 24
Finished Jan 14 03:41:45 PM PST 24
Peak memory 288984 kb
Host smart-f62abf88-6237-43e2-86e5-2f3476c9e68e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188659924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.4188659924
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2336242303
Short name T80
Test name
Test status
Simulation time 1964517719 ps
CPU time 84.45 seconds
Started Jan 14 02:58:41 PM PST 24
Finished Jan 14 03:00:07 PM PST 24
Peak memory 247240 kb
Host smart-b5d1c8f7-ed8c-4d3b-bc1c-054d7b134f3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336242303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2336242303
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.3975483191
Short name T475
Test name
Test status
Simulation time 1361041759 ps
CPU time 44.08 seconds
Started Jan 14 02:58:45 PM PST 24
Finished Jan 14 02:59:31 PM PST 24
Peak memory 248716 kb
Host smart-70c40512-16d9-4aef-90d6-b600bb697465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39754
83191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3975483191
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2143784380
Short name T724
Test name
Test status
Simulation time 1102974131 ps
CPU time 18.57 seconds
Started Jan 14 02:58:36 PM PST 24
Finished Jan 14 02:58:57 PM PST 24
Peak memory 254532 kb
Host smart-d75b3f56-a380-422c-8106-051bc183eb0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21437
84380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2143784380
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1565914103
Short name T46
Test name
Test status
Simulation time 486932442 ps
CPU time 27.84 seconds
Started Jan 14 02:58:52 PM PST 24
Finished Jan 14 02:59:21 PM PST 24
Peak memory 271132 kb
Host smart-843acac4-02bb-4280-9788-95fc09938641
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1565914103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1565914103
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.741856098
Short name T32
Test name
Test status
Simulation time 772579681 ps
CPU time 32.47 seconds
Started Jan 14 02:58:41 PM PST 24
Finished Jan 14 02:59:15 PM PST 24
Peak memory 255780 kb
Host smart-5650cdf2-a900-454a-9940-d459b508da9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74185
6098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.741856098
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2582042342
Short name T482
Test name
Test status
Simulation time 378638701 ps
CPU time 32.27 seconds
Started Jan 14 02:58:53 PM PST 24
Finished Jan 14 02:59:26 PM PST 24
Peak memory 255500 kb
Host smart-d223136c-40df-4a30-8670-950f7a34f63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25820
42342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2582042342
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.999734520
Short name T241
Test name
Test status
Simulation time 1479071953 ps
CPU time 36.5 seconds
Started Jan 14 02:58:44 PM PST 24
Finished Jan 14 02:59:22 PM PST 24
Peak memory 248720 kb
Host smart-6f88a8b5-85c3-4b28-9f0a-a9f252bd2bf2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999734520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.999734520
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2669417781
Short name T661
Test name
Test status
Simulation time 41885149354 ps
CPU time 1409.5 seconds
Started Jan 14 02:58:49 PM PST 24
Finished Jan 14 03:22:20 PM PST 24
Peak memory 284264 kb
Host smart-a6a37420-90af-4c6f-b61f-9f10118e86f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669417781 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2669417781
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1033439762
Short name T232
Test name
Test status
Simulation time 45673845 ps
CPU time 3.78 seconds
Started Jan 14 02:59:23 PM PST 24
Finished Jan 14 02:59:28 PM PST 24
Peak memory 248796 kb
Host smart-e5eb4f43-ce47-406b-9eeb-a52b87ccac47
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1033439762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1033439762
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.67073086
Short name T127
Test name
Test status
Simulation time 23593175120 ps
CPU time 649.51 seconds
Started Jan 14 02:59:23 PM PST 24
Finished Jan 14 03:10:14 PM PST 24
Peak memory 265092 kb
Host smart-a3fc98be-cec1-4b31-8f96-270a15a9064b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67073086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.67073086
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3754051062
Short name T418
Test name
Test status
Simulation time 147911902 ps
CPU time 8.54 seconds
Started Jan 14 02:59:34 PM PST 24
Finished Jan 14 02:59:44 PM PST 24
Peak memory 240396 kb
Host smart-7e1750df-5de8-4963-a8da-0995a50e1e3e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3754051062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3754051062
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3546306379
Short name T621
Test name
Test status
Simulation time 4427537785 ps
CPU time 265.4 seconds
Started Jan 14 02:59:20 PM PST 24
Finished Jan 14 03:03:46 PM PST 24
Peak memory 256200 kb
Host smart-15ca9b43-8bb6-4fba-97a6-3f0aa8c1e39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35463
06379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3546306379
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.4033911234
Short name T399
Test name
Test status
Simulation time 332653070 ps
CPU time 21.25 seconds
Started Jan 14 02:59:20 PM PST 24
Finished Jan 14 02:59:42 PM PST 24
Peak memory 255196 kb
Host smart-354b05dc-01fb-4e1f-8e9b-0537ac7d4ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40339
11234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.4033911234
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2216754913
Short name T360
Test name
Test status
Simulation time 26271226267 ps
CPU time 1380.77 seconds
Started Jan 14 02:59:21 PM PST 24
Finished Jan 14 03:22:23 PM PST 24
Peak memory 272844 kb
Host smart-b708049c-6b16-48b2-8564-bc8bca862f3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216754913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2216754913
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3421020649
Short name T426
Test name
Test status
Simulation time 67460353522 ps
CPU time 2156.15 seconds
Started Jan 14 02:59:27 PM PST 24
Finished Jan 14 03:35:25 PM PST 24
Peak memory 272344 kb
Host smart-f61cdf54-d0ba-4311-b5b5-909f7a506bc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421020649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3421020649
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2497891083
Short name T334
Test name
Test status
Simulation time 64049452774 ps
CPU time 517.44 seconds
Started Jan 14 02:59:23 PM PST 24
Finished Jan 14 03:08:02 PM PST 24
Peak memory 247188 kb
Host smart-0686aea5-586c-4154-8481-bc66916ae5ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497891083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2497891083
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1493162166
Short name T543
Test name
Test status
Simulation time 1112134822 ps
CPU time 65.1 seconds
Started Jan 14 02:59:24 PM PST 24
Finished Jan 14 03:00:31 PM PST 24
Peak memory 248684 kb
Host smart-4f7d4e69-a3d4-4106-a7ba-cb9719c6a178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14931
62166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1493162166
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.909869995
Short name T296
Test name
Test status
Simulation time 5149620058 ps
CPU time 29.74 seconds
Started Jan 14 02:59:21 PM PST 24
Finished Jan 14 02:59:52 PM PST 24
Peak memory 254960 kb
Host smart-cd600197-5347-409d-ae5b-c574a5d7febe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90986
9995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.909869995
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.4235089104
Short name T668
Test name
Test status
Simulation time 92243734 ps
CPU time 7.36 seconds
Started Jan 14 02:59:25 PM PST 24
Finished Jan 14 02:59:34 PM PST 24
Peak memory 249436 kb
Host smart-81fd8c4d-089d-4a43-acd1-b65273bcb0f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42350
89104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.4235089104
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.508766669
Short name T730
Test name
Test status
Simulation time 1470419610 ps
CPU time 29.11 seconds
Started Jan 14 02:59:18 PM PST 24
Finished Jan 14 02:59:48 PM PST 24
Peak memory 248736 kb
Host smart-a87a842e-4103-4e2d-af93-a594237c5578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50876
6669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.508766669
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3792940130
Short name T291
Test name
Test status
Simulation time 635192456 ps
CPU time 48.61 seconds
Started Jan 14 02:59:22 PM PST 24
Finished Jan 14 03:00:12 PM PST 24
Peak memory 248512 kb
Host smart-a8a03ee3-94f1-43c1-9d3d-afb9c64be815
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792940130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3792940130
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2938402997
Short name T508
Test name
Test status
Simulation time 123208593125 ps
CPU time 1116.83 seconds
Started Jan 14 02:59:26 PM PST 24
Finished Jan 14 03:18:04 PM PST 24
Peak memory 283020 kb
Host smart-89924222-88e2-4aa8-900c-fce25c8a2b32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938402997 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2938402997
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2224453643
Short name T135
Test name
Test status
Simulation time 38755291905 ps
CPU time 2532.88 seconds
Started Jan 14 02:59:29 PM PST 24
Finished Jan 14 03:41:44 PM PST 24
Peak memory 289524 kb
Host smart-925c978e-1b2b-418d-a64c-437e31a1d1db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224453643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2224453643
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.345851260
Short name T589
Test name
Test status
Simulation time 19767789063 ps
CPU time 118.6 seconds
Started Jan 14 02:59:29 PM PST 24
Finished Jan 14 03:01:28 PM PST 24
Peak memory 256396 kb
Host smart-8e3b21eb-1beb-4988-a7f1-a495c976a2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34585
1260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.345851260
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3728019203
Short name T462
Test name
Test status
Simulation time 1345526642 ps
CPU time 44.36 seconds
Started Jan 14 02:59:25 PM PST 24
Finished Jan 14 03:00:11 PM PST 24
Peak memory 255140 kb
Host smart-5dcbf531-ccf9-4833-956a-1d16d96ad25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37280
19203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3728019203
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1418426906
Short name T655
Test name
Test status
Simulation time 40834110325 ps
CPU time 2559.05 seconds
Started Jan 14 02:59:24 PM PST 24
Finished Jan 14 03:42:04 PM PST 24
Peak memory 273060 kb
Host smart-73a32ec2-d8ce-4856-a8ec-8026ab282c04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418426906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1418426906
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1914375447
Short name T517
Test name
Test status
Simulation time 41820509102 ps
CPU time 812.19 seconds
Started Jan 14 02:59:35 PM PST 24
Finished Jan 14 03:13:08 PM PST 24
Peak memory 269164 kb
Host smart-5bac1aac-5337-49d9-ad13-2cdc62648bb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914375447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1914375447
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2598626078
Short name T534
Test name
Test status
Simulation time 3839436260 ps
CPU time 155.03 seconds
Started Jan 14 02:59:25 PM PST 24
Finished Jan 14 03:02:01 PM PST 24
Peak memory 247400 kb
Host smart-b4c196cd-d279-443f-baef-1dd7da9ed4cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598626078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2598626078
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1986387781
Short name T298
Test name
Test status
Simulation time 189251682 ps
CPU time 4.53 seconds
Started Jan 14 02:59:28 PM PST 24
Finished Jan 14 02:59:34 PM PST 24
Peak memory 240536 kb
Host smart-c585c1ce-a3a5-42f8-b55e-6a8a9827d510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19863
87781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1986387781
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2260621474
Short name T700
Test name
Test status
Simulation time 1834832978 ps
CPU time 42.48 seconds
Started Jan 14 02:59:29 PM PST 24
Finished Jan 14 03:00:13 PM PST 24
Peak memory 254764 kb
Host smart-04e1c757-355e-47ee-b14c-de5a55bd8a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22606
21474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2260621474
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.4244002556
Short name T100
Test name
Test status
Simulation time 1144028883 ps
CPU time 20.83 seconds
Started Jan 14 02:59:25 PM PST 24
Finished Jan 14 02:59:47 PM PST 24
Peak memory 248716 kb
Host smart-fc6d7d3b-288f-4a9e-9655-556f373ebd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42440
02556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.4244002556
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.874251012
Short name T660
Test name
Test status
Simulation time 60033493829 ps
CPU time 1285.04 seconds
Started Jan 14 02:59:28 PM PST 24
Finished Jan 14 03:20:54 PM PST 24
Peak memory 273452 kb
Host smart-93aebaaa-9e81-4589-acd0-54ce65a90811
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874251012 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.874251012
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2699981064
Short name T238
Test name
Test status
Simulation time 26069628 ps
CPU time 2.38 seconds
Started Jan 14 02:59:33 PM PST 24
Finished Jan 14 02:59:36 PM PST 24
Peak memory 248892 kb
Host smart-4e5b336e-7782-4335-b668-7eb1b2245761
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2699981064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2699981064
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.917203211
Short name T538
Test name
Test status
Simulation time 33887789023 ps
CPU time 1121.41 seconds
Started Jan 14 02:59:51 PM PST 24
Finished Jan 14 03:18:33 PM PST 24
Peak memory 284428 kb
Host smart-4623c52d-bb95-45e7-8a26-57b611536ee5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917203211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.917203211
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1933774822
Short name T385
Test name
Test status
Simulation time 129561560 ps
CPU time 8.31 seconds
Started Jan 14 02:59:35 PM PST 24
Finished Jan 14 02:59:44 PM PST 24
Peak memory 240460 kb
Host smart-6863afe6-3baf-4f2f-8448-2fe99514269a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1933774822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1933774822
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.4271487818
Short name T707
Test name
Test status
Simulation time 5450741008 ps
CPU time 188.67 seconds
Started Jan 14 02:59:50 PM PST 24
Finished Jan 14 03:03:00 PM PST 24
Peak memory 255856 kb
Host smart-41724d26-4bf0-4e11-95f9-50c2a5881dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42714
87818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.4271487818
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2534512334
Short name T550
Test name
Test status
Simulation time 188612485 ps
CPU time 20.58 seconds
Started Jan 14 02:59:42 PM PST 24
Finished Jan 14 03:00:03 PM PST 24
Peak memory 254928 kb
Host smart-a96e432d-4e58-4f7c-8a32-7caaafd2344e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25345
12334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2534512334
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3755112167
Short name T638
Test name
Test status
Simulation time 19874637111 ps
CPU time 1059.22 seconds
Started Jan 14 02:59:35 PM PST 24
Finished Jan 14 03:17:15 PM PST 24
Peak memory 273132 kb
Host smart-b1073b7a-7cd0-44d5-8c42-30e9b7d76c2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755112167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3755112167
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.706027426
Short name T708
Test name
Test status
Simulation time 40273377678 ps
CPU time 409.36 seconds
Started Jan 14 02:59:43 PM PST 24
Finished Jan 14 03:06:33 PM PST 24
Peak memory 248712 kb
Host smart-d80d85d9-7d7c-4849-932f-344067e3ca1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706027426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.706027426
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1628980643
Short name T599
Test name
Test status
Simulation time 2380023560 ps
CPU time 73.43 seconds
Started Jan 14 02:59:46 PM PST 24
Finished Jan 14 03:01:00 PM PST 24
Peak memory 248692 kb
Host smart-7e278c04-117b-4f4b-8b42-60b133c1680c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16289
80643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1628980643
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.873260005
Short name T454
Test name
Test status
Simulation time 1249528473 ps
CPU time 73.84 seconds
Started Jan 14 02:59:50 PM PST 24
Finished Jan 14 03:01:05 PM PST 24
Peak memory 255248 kb
Host smart-dfe2ddf8-5e47-4529-bb47-c23fbdaf598d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87326
0005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.873260005
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3548597797
Short name T527
Test name
Test status
Simulation time 3452531576 ps
CPU time 53.02 seconds
Started Jan 14 02:59:40 PM PST 24
Finished Jan 14 03:00:33 PM PST 24
Peak memory 254700 kb
Host smart-2f33c3f6-2dfb-412c-99a2-9bbccfd8f072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35485
97797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3548597797
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.316190599
Short name T476
Test name
Test status
Simulation time 247432497154 ps
CPU time 1224.27 seconds
Started Jan 14 02:59:37 PM PST 24
Finished Jan 14 03:20:03 PM PST 24
Peak memory 286448 kb
Host smart-b1b48218-cba1-418a-91da-e4fbaf681f13
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316190599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.316190599
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1408548699
Short name T278
Test name
Test status
Simulation time 140369555117 ps
CPU time 2714.65 seconds
Started Jan 14 02:59:33 PM PST 24
Finished Jan 14 03:44:49 PM PST 24
Peak memory 305564 kb
Host smart-6715e464-d223-4c73-af66-6b4cf9ad96bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408548699 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1408548699
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.4082795436
Short name T231
Test name
Test status
Simulation time 129245183 ps
CPU time 3.62 seconds
Started Jan 14 02:59:42 PM PST 24
Finished Jan 14 02:59:47 PM PST 24
Peak memory 248760 kb
Host smart-49849fbd-6c17-4482-8023-90ddb9339a13
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4082795436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.4082795436
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2519780166
Short name T627
Test name
Test status
Simulation time 4539828532 ps
CPU time 44.47 seconds
Started Jan 14 02:59:38 PM PST 24
Finished Jan 14 03:00:23 PM PST 24
Peak memory 240464 kb
Host smart-9d2d4aa0-da9f-46ed-b926-7a5db47a5cd4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2519780166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2519780166
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3989365845
Short name T720
Test name
Test status
Simulation time 399938064 ps
CPU time 26.81 seconds
Started Jan 14 02:59:38 PM PST 24
Finished Jan 14 03:00:06 PM PST 24
Peak memory 254380 kb
Host smart-9cf12414-88b0-4ea1-bf41-948040817d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39893
65845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3989365845
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1000763127
Short name T361
Test name
Test status
Simulation time 19687511388 ps
CPU time 668.52 seconds
Started Jan 14 02:59:37 PM PST 24
Finished Jan 14 03:10:47 PM PST 24
Peak memory 273064 kb
Host smart-852382eb-435e-43ed-a16b-9c9fbc283054
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000763127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1000763127
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2457972745
Short name T519
Test name
Test status
Simulation time 122286610940 ps
CPU time 2714.11 seconds
Started Jan 14 02:59:51 PM PST 24
Finished Jan 14 03:45:06 PM PST 24
Peak memory 289108 kb
Host smart-82a25ed0-57b4-4b93-a759-8fff91dcd918
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457972745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2457972745
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.4146426469
Short name T8
Test name
Test status
Simulation time 4040195448 ps
CPU time 175.71 seconds
Started Jan 14 02:59:34 PM PST 24
Finished Jan 14 03:02:31 PM PST 24
Peak memory 246576 kb
Host smart-5ad62588-2844-4c2d-8fd8-c589cebb78b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146426469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.4146426469
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.948844612
Short name T78
Test name
Test status
Simulation time 446861636 ps
CPU time 17.77 seconds
Started Jan 14 02:59:37 PM PST 24
Finished Jan 14 02:59:55 PM PST 24
Peak memory 255456 kb
Host smart-e341eaf5-dfbf-496a-b35e-6f32c838ddd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94884
4612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.948844612
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3394300233
Short name T662
Test name
Test status
Simulation time 21322431 ps
CPU time 3.05 seconds
Started Jan 14 02:59:33 PM PST 24
Finished Jan 14 02:59:37 PM PST 24
Peak memory 238580 kb
Host smart-9fd75360-8de7-421f-a5d2-8d82b712b23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33943
00233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3394300233
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2478454116
Short name T92
Test name
Test status
Simulation time 249253822 ps
CPU time 17.22 seconds
Started Jan 14 02:59:41 PM PST 24
Finished Jan 14 02:59:58 PM PST 24
Peak memory 248544 kb
Host smart-ee5fa203-a6d4-4aed-9bbf-ba2ab2a831db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24784
54116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2478454116
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.4251261220
Short name T729
Test name
Test status
Simulation time 181617281 ps
CPU time 12.04 seconds
Started Jan 14 02:59:34 PM PST 24
Finished Jan 14 02:59:47 PM PST 24
Peak memory 248664 kb
Host smart-6b1891ed-9f53-45df-bbf1-4a6c08309dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42512
61220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.4251261220
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3424603104
Short name T576
Test name
Test status
Simulation time 20810375147 ps
CPU time 307.47 seconds
Started Jan 14 02:59:37 PM PST 24
Finished Jan 14 03:04:46 PM PST 24
Peak memory 256888 kb
Host smart-001da5df-d1ed-4ce4-9714-aa308b9ebdd1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424603104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3424603104
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.480093592
Short name T18
Test name
Test status
Simulation time 25002664 ps
CPU time 2.55 seconds
Started Jan 14 02:59:36 PM PST 24
Finished Jan 14 02:59:39 PM PST 24
Peak memory 248812 kb
Host smart-b2da4d72-48dc-4fcf-afdf-c1da55bb09e3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=480093592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.480093592
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.4269222568
Short name T61
Test name
Test status
Simulation time 135797505668 ps
CPU time 2307.34 seconds
Started Jan 14 02:59:42 PM PST 24
Finished Jan 14 03:38:10 PM PST 24
Peak memory 273136 kb
Host smart-3b52326c-342f-4375-9d84-acf1d5be008d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269222568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.4269222568
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.838090675
Short name T610
Test name
Test status
Simulation time 421089267 ps
CPU time 8.38 seconds
Started Jan 14 02:59:35 PM PST 24
Finished Jan 14 02:59:44 PM PST 24
Peak memory 240464 kb
Host smart-bfef7059-2399-4d27-881f-60b31462906a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=838090675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.838090675
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1454742087
Short name T288
Test name
Test status
Simulation time 4573968153 ps
CPU time 99.1 seconds
Started Jan 14 02:59:44 PM PST 24
Finished Jan 14 03:01:23 PM PST 24
Peak memory 249704 kb
Host smart-161c7f7a-4044-47b3-acc6-616ed342c316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14547
42087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1454742087
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3456714048
Short name T547
Test name
Test status
Simulation time 2715113073 ps
CPU time 51.26 seconds
Started Jan 14 02:59:29 PM PST 24
Finished Jan 14 03:00:22 PM PST 24
Peak memory 254724 kb
Host smart-9da23edb-9bd2-4ce1-a3ec-ba06c09dd410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34567
14048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3456714048
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.889724157
Short name T313
Test name
Test status
Simulation time 110014889382 ps
CPU time 1669.18 seconds
Started Jan 14 02:59:43 PM PST 24
Finished Jan 14 03:27:34 PM PST 24
Peak memory 267196 kb
Host smart-e5ab9046-b040-41ec-8e4c-c08f51f2bc39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889724157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.889724157
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.174354692
Short name T427
Test name
Test status
Simulation time 41245530330 ps
CPU time 1330.83 seconds
Started Jan 14 02:59:34 PM PST 24
Finished Jan 14 03:21:46 PM PST 24
Peak memory 286640 kb
Host smart-3b56e726-c9c2-4b6f-981b-a561c6c04c34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174354692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.174354692
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1080281886
Short name T598
Test name
Test status
Simulation time 25546699401 ps
CPU time 312.66 seconds
Started Jan 14 02:59:33 PM PST 24
Finished Jan 14 03:04:47 PM PST 24
Peak memory 247332 kb
Host smart-76f44f09-f644-48c1-9691-6f92abdbf013
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080281886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1080281886
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2447770843
Short name T101
Test name
Test status
Simulation time 886914764 ps
CPU time 6.83 seconds
Started Jan 14 02:59:26 PM PST 24
Finished Jan 14 02:59:34 PM PST 24
Peak memory 240520 kb
Host smart-a0840034-1a21-4cbe-84bc-853aaf0619a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24477
70843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2447770843
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.787998442
Short name T286
Test name
Test status
Simulation time 425474218 ps
CPU time 32.87 seconds
Started Jan 14 02:59:40 PM PST 24
Finished Jan 14 03:00:13 PM PST 24
Peak memory 255600 kb
Host smart-a90a56f7-04dc-4a18-98cf-10ba1e15e9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78799
8442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.787998442
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3677171830
Short name T123
Test name
Test status
Simulation time 1029170474 ps
CPU time 35.97 seconds
Started Jan 14 02:59:51 PM PST 24
Finished Jan 14 03:00:28 PM PST 24
Peak memory 255240 kb
Host smart-9b3feca1-2a95-43bd-9134-2928c2ad13af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36771
71830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3677171830
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1571575530
Short name T701
Test name
Test status
Simulation time 848857682 ps
CPU time 21.66 seconds
Started Jan 14 02:59:32 PM PST 24
Finished Jan 14 02:59:54 PM PST 24
Peak memory 248692 kb
Host smart-ed91877b-b8d5-4a76-a489-8ec83ede2157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15715
75530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1571575530
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2470920004
Short name T227
Test name
Test status
Simulation time 56347732 ps
CPU time 2.65 seconds
Started Jan 14 02:59:43 PM PST 24
Finished Jan 14 02:59:46 PM PST 24
Peak memory 248920 kb
Host smart-69d08fc3-f46a-433e-95cf-0a040ea7ecd4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2470920004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2470920004
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2357392805
Short name T42
Test name
Test status
Simulation time 112377397434 ps
CPU time 1701.97 seconds
Started Jan 14 02:59:47 PM PST 24
Finished Jan 14 03:28:10 PM PST 24
Peak memory 272148 kb
Host smart-d57de8d9-3897-4a38-9598-664f5844f9be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357392805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2357392805
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1219174199
Short name T145
Test name
Test status
Simulation time 2627935743 ps
CPU time 55.85 seconds
Started Jan 14 02:59:45 PM PST 24
Finished Jan 14 03:00:42 PM PST 24
Peak memory 239720 kb
Host smart-b1e4db92-066f-475e-ac7a-773ea52b0a82
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1219174199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1219174199
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.890755299
Short name T531
Test name
Test status
Simulation time 2448445207 ps
CPU time 149.42 seconds
Started Jan 14 02:59:33 PM PST 24
Finished Jan 14 03:02:04 PM PST 24
Peak memory 249752 kb
Host smart-c62d9cce-3e84-4646-8e41-23ab80249fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89075
5299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.890755299
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1759547142
Short name T506
Test name
Test status
Simulation time 185428589 ps
CPU time 18.06 seconds
Started Jan 14 02:59:28 PM PST 24
Finished Jan 14 02:59:47 PM PST 24
Peak memory 247996 kb
Host smart-185ba021-d9ea-43f2-9937-aab3489724cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17595
47142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1759547142
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2007280181
Short name T344
Test name
Test status
Simulation time 115967919371 ps
CPU time 1614.55 seconds
Started Jan 14 02:59:50 PM PST 24
Finished Jan 14 03:26:45 PM PST 24
Peak memory 285420 kb
Host smart-27abc247-c62d-4769-a688-401734ca6c65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007280181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2007280181
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3167746484
Short name T409
Test name
Test status
Simulation time 91523589733 ps
CPU time 1411.92 seconds
Started Jan 14 02:59:50 PM PST 24
Finished Jan 14 03:23:23 PM PST 24
Peak memory 289160 kb
Host smart-9dca0b5d-fe7a-44dc-92ad-03f6791192ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167746484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3167746484
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2117591396
Short name T699
Test name
Test status
Simulation time 7225415691 ps
CPU time 300.24 seconds
Started Jan 14 02:59:42 PM PST 24
Finished Jan 14 03:04:43 PM PST 24
Peak memory 247532 kb
Host smart-e2f09e5e-d1ea-490f-80f1-fa58d22d0272
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117591396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2117591396
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.810740318
Short name T644
Test name
Test status
Simulation time 255037498 ps
CPU time 10.32 seconds
Started Jan 14 02:59:42 PM PST 24
Finished Jan 14 02:59:53 PM PST 24
Peak memory 254136 kb
Host smart-08b8a3b2-7d56-4814-b055-6a0174c1410b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81074
0318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.810740318
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1199919597
Short name T447
Test name
Test status
Simulation time 417505555 ps
CPU time 30.33 seconds
Started Jan 14 02:59:35 PM PST 24
Finished Jan 14 03:00:06 PM PST 24
Peak memory 253736 kb
Host smart-495ca358-1d3b-410d-ad0f-049e5d9bf63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11999
19597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1199919597
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1098150804
Short name T142
Test name
Test status
Simulation time 924271099 ps
CPU time 15.82 seconds
Started Jan 14 02:59:35 PM PST 24
Finished Jan 14 02:59:52 PM PST 24
Peak memory 247188 kb
Host smart-9f33d49c-98f7-418d-b99b-30c068ef8d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10981
50804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1098150804
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3334723507
Short name T398
Test name
Test status
Simulation time 4858998532 ps
CPU time 64.79 seconds
Started Jan 14 02:59:36 PM PST 24
Finished Jan 14 03:00:42 PM PST 24
Peak memory 255380 kb
Host smart-ce89fb96-5e2b-4e79-85c0-b34ffc8fa4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33347
23507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3334723507
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.594276345
Short name T62
Test name
Test status
Simulation time 47022164833 ps
CPU time 3088.54 seconds
Started Jan 14 02:59:50 PM PST 24
Finished Jan 14 03:51:20 PM PST 24
Peak memory 289088 kb
Host smart-01ecc9c6-55fd-49ce-8f87-a42dbc52e6c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594276345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.594276345
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1626300116
Short name T602
Test name
Test status
Simulation time 40125632035 ps
CPU time 1167.22 seconds
Started Jan 14 02:59:46 PM PST 24
Finished Jan 14 03:19:14 PM PST 24
Peak memory 288356 kb
Host smart-42b033b8-861a-4ada-8131-d4f2f08c8bcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626300116 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1626300116
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.676679074
Short name T544
Test name
Test status
Simulation time 44713712629 ps
CPU time 2838.74 seconds
Started Jan 14 02:59:51 PM PST 24
Finished Jan 14 03:47:11 PM PST 24
Peak memory 289544 kb
Host smart-add53a71-076d-48df-9794-0b79c2e6ae12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676679074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.676679074
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.63393285
Short name T560
Test name
Test status
Simulation time 188234738 ps
CPU time 11.25 seconds
Started Jan 14 02:59:43 PM PST 24
Finished Jan 14 02:59:55 PM PST 24
Peak memory 240420 kb
Host smart-8a3dd67d-6884-48f9-be29-8faac632376a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=63393285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.63393285
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3882324717
Short name T695
Test name
Test status
Simulation time 11878123271 ps
CPU time 139.08 seconds
Started Jan 14 02:59:50 PM PST 24
Finished Jan 14 03:02:10 PM PST 24
Peak memory 249848 kb
Host smart-71becf3c-fa88-45db-8a59-8d138223b939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38823
24717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3882324717
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1694823550
Short name T144
Test name
Test status
Simulation time 1088539456 ps
CPU time 28.24 seconds
Started Jan 14 02:59:46 PM PST 24
Finished Jan 14 03:00:15 PM PST 24
Peak memory 254744 kb
Host smart-7ab79515-0ef1-4acb-b170-fce0e14916a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16948
23550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1694823550
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.166752652
Short name T369
Test name
Test status
Simulation time 13061227688 ps
CPU time 1306.85 seconds
Started Jan 14 02:59:41 PM PST 24
Finished Jan 14 03:21:29 PM PST 24
Peak memory 289100 kb
Host smart-b477e79e-64ba-4a5e-affb-fb035089d6da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166752652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.166752652
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1583342568
Short name T652
Test name
Test status
Simulation time 26031985952 ps
CPU time 1343.95 seconds
Started Jan 14 02:59:45 PM PST 24
Finished Jan 14 03:22:09 PM PST 24
Peak memory 289124 kb
Host smart-269edc46-b288-462d-9363-90b2e67946d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583342568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1583342568
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1127773453
Short name T651
Test name
Test status
Simulation time 2092391337 ps
CPU time 23.47 seconds
Started Jan 14 02:59:47 PM PST 24
Finished Jan 14 03:00:11 PM PST 24
Peak memory 248676 kb
Host smart-997e0266-3ff3-47e4-9133-272770a7bbb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11277
73453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1127773453
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3787593749
Short name T672
Test name
Test status
Simulation time 328417022 ps
CPU time 6.91 seconds
Started Jan 14 02:59:43 PM PST 24
Finished Jan 14 02:59:50 PM PST 24
Peak memory 250536 kb
Host smart-e0725a98-d44f-4890-b893-cfa8f827802f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37875
93749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3787593749
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1996094408
Short name T91
Test name
Test status
Simulation time 1464548822 ps
CPU time 56.23 seconds
Started Jan 14 02:59:41 PM PST 24
Finished Jan 14 03:00:38 PM PST 24
Peak memory 255344 kb
Host smart-d3175f88-7f72-4071-bfd4-84d372d30389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19960
94408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1996094408
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3744976040
Short name T406
Test name
Test status
Simulation time 145808953 ps
CPU time 15.16 seconds
Started Jan 14 02:59:52 PM PST 24
Finished Jan 14 03:00:08 PM PST 24
Peak memory 248892 kb
Host smart-f167d6b6-2dab-41b2-8fbc-f7755fdb72cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37449
76040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3744976040
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.4254439749
Short name T618
Test name
Test status
Simulation time 215732190184 ps
CPU time 2943.94 seconds
Started Jan 14 02:59:41 PM PST 24
Finished Jan 14 03:48:46 PM PST 24
Peak memory 305724 kb
Host smart-97845d66-3b99-4eeb-9fd7-24b7967fadd0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254439749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.4254439749
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.559683895
Short name T679
Test name
Test status
Simulation time 1106242652592 ps
CPU time 9544.13 seconds
Started Jan 14 02:59:38 PM PST 24
Finished Jan 14 05:38:44 PM PST 24
Peak memory 394764 kb
Host smart-4cea0a27-3484-47f2-840e-d150038f15ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559683895 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.559683895
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1459832644
Short name T234
Test name
Test status
Simulation time 40186469 ps
CPU time 3.6 seconds
Started Jan 14 02:59:50 PM PST 24
Finished Jan 14 02:59:54 PM PST 24
Peak memory 248952 kb
Host smart-23650787-d521-4606-8519-a4b786d65c74
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1459832644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1459832644
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.792697337
Short name T453
Test name
Test status
Simulation time 47963602746 ps
CPU time 1092.6 seconds
Started Jan 14 02:59:42 PM PST 24
Finished Jan 14 03:17:55 PM PST 24
Peak memory 289604 kb
Host smart-9c340f55-7f51-4474-84cc-1c9715fd6649
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792697337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.792697337
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3905734947
Short name T504
Test name
Test status
Simulation time 168446116 ps
CPU time 9.71 seconds
Started Jan 14 02:59:44 PM PST 24
Finished Jan 14 02:59:54 PM PST 24
Peak memory 248612 kb
Host smart-f8ebf6b0-f536-47cc-b6fe-d4f0bb042aa0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3905734947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3905734947
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2016465754
Short name T444
Test name
Test status
Simulation time 2667135176 ps
CPU time 114.05 seconds
Started Jan 14 02:59:50 PM PST 24
Finished Jan 14 03:01:44 PM PST 24
Peak memory 256236 kb
Host smart-1c648f4f-04ed-4abf-9035-ff1e307848dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20164
65754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2016465754
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1238443141
Short name T455
Test name
Test status
Simulation time 1836014257 ps
CPU time 35.56 seconds
Started Jan 14 02:59:51 PM PST 24
Finished Jan 14 03:00:27 PM PST 24
Peak memory 254276 kb
Host smart-7f0715d5-72f4-40c0-a9d3-894106399bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12384
43141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1238443141
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1268949449
Short name T539
Test name
Test status
Simulation time 175786426400 ps
CPU time 2310.7 seconds
Started Jan 14 02:59:39 PM PST 24
Finished Jan 14 03:38:10 PM PST 24
Peak memory 273084 kb
Host smart-633a9f68-628a-4b57-b1ed-7cbb78cf8b7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268949449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1268949449
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.887289684
Short name T559
Test name
Test status
Simulation time 29033016320 ps
CPU time 455.32 seconds
Started Jan 14 02:59:51 PM PST 24
Finished Jan 14 03:07:27 PM PST 24
Peak memory 246320 kb
Host smart-57327c75-7455-41c3-90cd-dfabb955ee96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887289684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.887289684
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3407161273
Short name T60
Test name
Test status
Simulation time 731643122 ps
CPU time 42.32 seconds
Started Jan 14 02:59:44 PM PST 24
Finished Jan 14 03:00:27 PM PST 24
Peak memory 248692 kb
Host smart-9d7eb9bd-8ae7-45c2-b4c4-bcaca14d5b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34071
61273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3407161273
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2137301674
Short name T76
Test name
Test status
Simulation time 274408872 ps
CPU time 21.11 seconds
Started Jan 14 02:59:50 PM PST 24
Finished Jan 14 03:00:12 PM PST 24
Peak memory 253160 kb
Host smart-7c5d2b4d-7be7-4951-a48e-e59e13f3cbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21373
01674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2137301674
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1561031521
Short name T124
Test name
Test status
Simulation time 96232795 ps
CPU time 14.21 seconds
Started Jan 14 02:59:45 PM PST 24
Finished Jan 14 03:00:00 PM PST 24
Peak memory 246908 kb
Host smart-18a42a03-0d11-4ea8-8713-5d9a7bab3008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15610
31521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1561031521
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1645146493
Short name T629
Test name
Test status
Simulation time 1300962941 ps
CPU time 67.17 seconds
Started Jan 14 02:59:43 PM PST 24
Finished Jan 14 03:00:51 PM PST 24
Peak memory 256860 kb
Host smart-c283c5ed-c4ca-4292-a78e-d884860e1d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16451
46493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1645146493
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.832526887
Short name T93
Test name
Test status
Simulation time 17211560727 ps
CPU time 534.69 seconds
Started Jan 14 02:59:50 PM PST 24
Finished Jan 14 03:08:46 PM PST 24
Peak memory 256892 kb
Host smart-0a98de39-8100-4f28-bb8a-598bea44658c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832526887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.832526887
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.3820684504
Short name T513
Test name
Test status
Simulation time 110566571181 ps
CPU time 5014.91 seconds
Started Jan 14 02:59:43 PM PST 24
Finished Jan 14 04:23:19 PM PST 24
Peak memory 306220 kb
Host smart-7cb8bd76-b975-48f9-b12a-57a8d6ead468
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820684504 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.3820684504
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3169859212
Short name T224
Test name
Test status
Simulation time 42957741 ps
CPU time 2.29 seconds
Started Jan 14 02:59:47 PM PST 24
Finished Jan 14 02:59:50 PM PST 24
Peak memory 248904 kb
Host smart-5f3b1159-88f9-4a61-ad74-2dda554efcc9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3169859212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3169859212
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2055669858
Short name T384
Test name
Test status
Simulation time 43143936730 ps
CPU time 2603.82 seconds
Started Jan 14 02:59:48 PM PST 24
Finished Jan 14 03:43:13 PM PST 24
Peak memory 282332 kb
Host smart-16ee1b42-2d8c-425f-a415-54b9c97e5bee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055669858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2055669858
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1687727547
Short name T521
Test name
Test status
Simulation time 364170950 ps
CPU time 17.26 seconds
Started Jan 14 02:59:41 PM PST 24
Finished Jan 14 02:59:59 PM PST 24
Peak memory 240480 kb
Host smart-a6dd3873-26ce-4cfc-bcb3-1476dfce7b41
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1687727547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1687727547
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2117020555
Short name T79
Test name
Test status
Simulation time 33290710 ps
CPU time 3.03 seconds
Started Jan 14 02:59:43 PM PST 24
Finished Jan 14 02:59:47 PM PST 24
Peak memory 238768 kb
Host smart-51d34285-894a-4ef8-9b2e-c291b58cf652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21170
20555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2117020555
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1025914633
Short name T573
Test name
Test status
Simulation time 275286569 ps
CPU time 26.81 seconds
Started Jan 14 02:59:51 PM PST 24
Finished Jan 14 03:00:18 PM PST 24
Peak memory 248028 kb
Host smart-351db180-0be1-4492-98f4-de1b23b732ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10259
14633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1025914633
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2244268596
Short name T332
Test name
Test status
Simulation time 76395984336 ps
CPU time 1841.64 seconds
Started Jan 14 02:59:52 PM PST 24
Finished Jan 14 03:30:35 PM PST 24
Peak memory 269220 kb
Host smart-4f304762-a1a9-4ce1-a9de-0a34b570d180
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244268596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2244268596
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.887344393
Short name T583
Test name
Test status
Simulation time 145193468092 ps
CPU time 2421.21 seconds
Started Jan 14 02:59:42 PM PST 24
Finished Jan 14 03:40:04 PM PST 24
Peak memory 288552 kb
Host smart-55d11a1b-b1eb-40d1-80ca-c0a87a602a5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887344393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.887344393
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.244305888
Short name T690
Test name
Test status
Simulation time 7421843168 ps
CPU time 97.55 seconds
Started Jan 14 02:59:51 PM PST 24
Finished Jan 14 03:01:30 PM PST 24
Peak memory 247296 kb
Host smart-5395764b-1848-4840-933f-b65cc1a15070
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244305888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.244305888
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.221630163
Short name T382
Test name
Test status
Simulation time 197380110 ps
CPU time 9.95 seconds
Started Jan 14 02:59:50 PM PST 24
Finished Jan 14 03:00:01 PM PST 24
Peak memory 248356 kb
Host smart-3366d516-7c1a-4702-8cd3-39caec379e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22163
0163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.221630163
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.445427795
Short name T77
Test name
Test status
Simulation time 1099161412 ps
CPU time 28.92 seconds
Started Jan 14 02:59:45 PM PST 24
Finished Jan 14 03:00:15 PM PST 24
Peak memory 254048 kb
Host smart-1c638c27-b81b-4f4d-8ea2-c5bcf003bd6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44542
7795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.445427795
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.771136245
Short name T718
Test name
Test status
Simulation time 1564890929 ps
CPU time 49.9 seconds
Started Jan 14 02:59:48 PM PST 24
Finished Jan 14 03:00:39 PM PST 24
Peak memory 254596 kb
Host smart-23eae3ad-bcd5-4dd6-8e89-11cd370f5278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77113
6245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.771136245
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.523214436
Short name T545
Test name
Test status
Simulation time 932670689 ps
CPU time 26.68 seconds
Started Jan 14 02:59:50 PM PST 24
Finished Jan 14 03:00:18 PM PST 24
Peak memory 248608 kb
Host smart-3eced804-f6a0-4dbf-85a3-d99af33a9bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52321
4436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.523214436
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.483282233
Short name T132
Test name
Test status
Simulation time 9591876168 ps
CPU time 917.44 seconds
Started Jan 14 02:59:47 PM PST 24
Finished Jan 14 03:15:05 PM PST 24
Peak memory 281872 kb
Host smart-3c30bd3b-cef2-407e-af03-ca4b3887038d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483282233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.483282233
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3926733318
Short name T247
Test name
Test status
Simulation time 12002165044 ps
CPU time 864.61 seconds
Started Jan 14 02:59:51 PM PST 24
Finished Jan 14 03:14:17 PM PST 24
Peak memory 272796 kb
Host smart-d55c6c7a-65dd-4972-ae99-8f3ebcb2d33f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926733318 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3926733318
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.664476270
Short name T237
Test name
Test status
Simulation time 83702942 ps
CPU time 2.39 seconds
Started Jan 14 02:59:54 PM PST 24
Finished Jan 14 02:59:57 PM PST 24
Peak memory 248920 kb
Host smart-09ec28da-4819-48b4-bdf5-5782cae1e4cd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=664476270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.664476270
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.531394708
Short name T503
Test name
Test status
Simulation time 27374614128 ps
CPU time 1783.44 seconds
Started Jan 14 02:59:50 PM PST 24
Finished Jan 14 03:29:35 PM PST 24
Peak memory 265064 kb
Host smart-07230eee-4f90-4a5e-b5a8-a65103ba4eb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531394708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.531394708
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2216215726
Short name T611
Test name
Test status
Simulation time 1819024856 ps
CPU time 8.49 seconds
Started Jan 14 02:59:49 PM PST 24
Finished Jan 14 02:59:58 PM PST 24
Peak memory 240452 kb
Host smart-497ebe17-6b5e-4748-9d46-710c6caa4ae3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2216215726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2216215726
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2186489400
Short name T682
Test name
Test status
Simulation time 14440082445 ps
CPU time 212.81 seconds
Started Jan 14 02:59:51 PM PST 24
Finished Jan 14 03:03:25 PM PST 24
Peak memory 256340 kb
Host smart-d0023734-d8c1-480c-af9f-943648a0c104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21864
89400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2186489400
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3701169849
Short name T676
Test name
Test status
Simulation time 321459115 ps
CPU time 19.71 seconds
Started Jan 14 02:59:48 PM PST 24
Finished Jan 14 03:00:08 PM PST 24
Peak memory 254352 kb
Host smart-bc70fd7d-30ce-4cdb-987e-d572462a783a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37011
69849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3701169849
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.4138119610
Short name T347
Test name
Test status
Simulation time 508298093913 ps
CPU time 2228 seconds
Started Jan 14 02:59:48 PM PST 24
Finished Jan 14 03:36:57 PM PST 24
Peak memory 273320 kb
Host smart-05f553cc-a3ed-48fa-bd17-286fe1ceb88c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138119610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.4138119610
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1645471403
Short name T102
Test name
Test status
Simulation time 4317544217 ps
CPU time 20.32 seconds
Started Jan 14 02:59:43 PM PST 24
Finished Jan 14 03:00:04 PM PST 24
Peak memory 248768 kb
Host smart-33fcc5aa-25ab-4f28-b749-453ac0c2a2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16454
71403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1645471403
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3749310212
Short name T20
Test name
Test status
Simulation time 559102326 ps
CPU time 11.79 seconds
Started Jan 14 02:59:51 PM PST 24
Finished Jan 14 03:00:04 PM PST 24
Peak memory 247024 kb
Host smart-929b45b9-2143-4538-8f03-dd7c90831dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37493
10212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3749310212
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3726389551
Short name T465
Test name
Test status
Simulation time 204295408 ps
CPU time 26.26 seconds
Started Jan 14 02:59:52 PM PST 24
Finished Jan 14 03:00:19 PM PST 24
Peak memory 248724 kb
Host smart-41bf5415-f7bc-49a4-b972-05daf7c9e340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37263
89551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3726389551
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.612197226
Short name T445
Test name
Test status
Simulation time 4177735858 ps
CPU time 120.36 seconds
Started Jan 14 02:59:48 PM PST 24
Finished Jan 14 03:01:49 PM PST 24
Peak memory 256896 kb
Host smart-9afd4f66-bfdd-4aa7-a4c7-bb5bc1f00c9a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612197226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.612197226
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2936940615
Short name T222
Test name
Test status
Simulation time 23510231 ps
CPU time 2.46 seconds
Started Jan 14 02:58:55 PM PST 24
Finished Jan 14 02:59:00 PM PST 24
Peak memory 248868 kb
Host smart-9bbba175-d7a6-4c3d-95b1-17226077f6a1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2936940615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2936940615
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2224420548
Short name T457
Test name
Test status
Simulation time 171950066322 ps
CPU time 2954.76 seconds
Started Jan 14 02:58:49 PM PST 24
Finished Jan 14 03:48:05 PM PST 24
Peak memory 289604 kb
Host smart-0fb10fb9-be87-4436-a511-342671241d18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224420548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2224420548
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.327766275
Short name T689
Test name
Test status
Simulation time 453349600 ps
CPU time 7.74 seconds
Started Jan 14 02:58:49 PM PST 24
Finished Jan 14 02:58:58 PM PST 24
Peak memory 240376 kb
Host smart-135ab500-b54e-4560-a36a-4768d0caa610
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=327766275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.327766275
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.438660481
Short name T582
Test name
Test status
Simulation time 16168208082 ps
CPU time 277.08 seconds
Started Jan 14 02:58:53 PM PST 24
Finished Jan 14 03:03:31 PM PST 24
Peak memory 256492 kb
Host smart-0e132f8d-2493-4dc7-8b3f-c4e1a1bda1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43866
0481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.438660481
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3345328321
Short name T705
Test name
Test status
Simulation time 713894053 ps
CPU time 45.18 seconds
Started Jan 14 02:58:44 PM PST 24
Finished Jan 14 02:59:31 PM PST 24
Peak memory 255164 kb
Host smart-a8ae4cf4-1a38-4e84-a6ca-148bac20ae45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33453
28321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3345328321
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1787884606
Short name T351
Test name
Test status
Simulation time 70697991351 ps
CPU time 1556.77 seconds
Started Jan 14 02:58:48 PM PST 24
Finished Jan 14 03:24:46 PM PST 24
Peak memory 283912 kb
Host smart-7725e8ed-eb62-4bdf-b82e-cf20a0923386
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787884606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1787884606
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.116727631
Short name T113
Test name
Test status
Simulation time 14978420179 ps
CPU time 1433.04 seconds
Started Jan 14 02:58:45 PM PST 24
Finished Jan 14 03:22:40 PM PST 24
Peak memory 288988 kb
Host smart-33985a08-3680-4eda-a2ec-8738d47b0395
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116727631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.116727631
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.521694475
Short name T49
Test name
Test status
Simulation time 13517298549 ps
CPU time 267.03 seconds
Started Jan 14 02:58:41 PM PST 24
Finished Jan 14 03:03:10 PM PST 24
Peak memory 247384 kb
Host smart-00831784-7f00-4e8b-99a4-4027c514cdae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521694475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.521694475
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.593851403
Short name T678
Test name
Test status
Simulation time 1493226668 ps
CPU time 36.01 seconds
Started Jan 14 02:58:53 PM PST 24
Finished Jan 14 02:59:30 PM PST 24
Peak memory 248676 kb
Host smart-aacecd4a-ac85-479f-9a95-980b42405a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59385
1403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.593851403
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2793824805
Short name T565
Test name
Test status
Simulation time 239555317 ps
CPU time 14.85 seconds
Started Jan 14 02:58:46 PM PST 24
Finished Jan 14 02:59:02 PM PST 24
Peak memory 253444 kb
Host smart-00bf0216-3ec2-4609-8074-3b6648efc4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27938
24805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2793824805
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3258351272
Short name T613
Test name
Test status
Simulation time 599124775 ps
CPU time 17.21 seconds
Started Jan 14 02:58:44 PM PST 24
Finished Jan 14 02:59:03 PM PST 24
Peak memory 247588 kb
Host smart-d55ddd98-f634-4389-b66f-eca9c06e0a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32583
51272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3258351272
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.331293470
Short name T98
Test name
Test status
Simulation time 101651461 ps
CPU time 9.07 seconds
Started Jan 14 02:58:43 PM PST 24
Finished Jan 14 02:58:54 PM PST 24
Peak memory 248732 kb
Host smart-86913e3b-627b-4abd-a3f0-7786dcfc92f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33129
3470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.331293470
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.4097170267
Short name T697
Test name
Test status
Simulation time 202135756898 ps
CPU time 2635.73 seconds
Started Jan 14 02:58:49 PM PST 24
Finished Jan 14 03:42:46 PM PST 24
Peak memory 285604 kb
Host smart-4ba416af-7afa-4c72-8d8d-2d933e2fa868
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097170267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.4097170267
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2400436906
Short name T129
Test name
Test status
Simulation time 160223550020 ps
CPU time 1858.99 seconds
Started Jan 14 02:58:57 PM PST 24
Finished Jan 14 03:29:58 PM PST 24
Peak memory 281616 kb
Host smart-5880f9ce-3597-4123-899d-282d55b36efc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400436906 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2400436906
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.207466285
Short name T535
Test name
Test status
Simulation time 9820800721 ps
CPU time 829.53 seconds
Started Jan 14 03:00:02 PM PST 24
Finished Jan 14 03:13:53 PM PST 24
Peak memory 272196 kb
Host smart-45f36884-7129-4747-88ae-1eef955372f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207466285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.207466285
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.153769044
Short name T259
Test name
Test status
Simulation time 4139153690 ps
CPU time 83.49 seconds
Started Jan 14 03:00:02 PM PST 24
Finished Jan 14 03:01:27 PM PST 24
Peak memory 256064 kb
Host smart-a3125241-43a6-4700-9823-e371ff39330e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15376
9044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.153769044
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.467976867
Short name T405
Test name
Test status
Simulation time 819054175 ps
CPU time 42.86 seconds
Started Jan 14 02:59:58 PM PST 24
Finished Jan 14 03:00:42 PM PST 24
Peak memory 254420 kb
Host smart-5bd4be02-ee3d-4ed2-954d-d21869368756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46797
6867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.467976867
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2928340126
Short name T703
Test name
Test status
Simulation time 127165321565 ps
CPU time 2062.87 seconds
Started Jan 14 03:00:02 PM PST 24
Finished Jan 14 03:34:26 PM PST 24
Peak memory 273256 kb
Host smart-8cd4f0b0-0552-4cd2-94ab-2cb3609b02cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928340126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2928340126
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3764010518
Short name T667
Test name
Test status
Simulation time 9376236955 ps
CPU time 376.07 seconds
Started Jan 14 02:59:56 PM PST 24
Finished Jan 14 03:06:13 PM PST 24
Peak memory 247328 kb
Host smart-848e6d5c-8a1f-473f-9716-07ef5f4ce528
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764010518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3764010518
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2554833691
Short name T498
Test name
Test status
Simulation time 1592096549 ps
CPU time 26 seconds
Started Jan 14 03:00:00 PM PST 24
Finished Jan 14 03:00:27 PM PST 24
Peak memory 255036 kb
Host smart-0d85ce69-5c4c-442c-b0a6-59101a65ba0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25548
33691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2554833691
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.596734400
Short name T641
Test name
Test status
Simulation time 798552720 ps
CPU time 55.06 seconds
Started Jan 14 02:59:58 PM PST 24
Finished Jan 14 03:00:54 PM PST 24
Peak memory 255116 kb
Host smart-99702747-6b88-4c79-ac1d-0fd94058463c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59673
4400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.596734400
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2572620667
Short name T674
Test name
Test status
Simulation time 501536913 ps
CPU time 13.29 seconds
Started Jan 14 03:00:02 PM PST 24
Finished Jan 14 03:00:16 PM PST 24
Peak memory 246848 kb
Host smart-ca3ada79-b15e-473a-9090-10ca15b1b6c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25726
20667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2572620667
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1355040590
Short name T137
Test name
Test status
Simulation time 611003638 ps
CPU time 30.17 seconds
Started Jan 14 02:59:50 PM PST 24
Finished Jan 14 03:00:20 PM PST 24
Peak memory 248744 kb
Host smart-758a8af5-5097-41ae-8ed0-c553422c8133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13550
40590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1355040590
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1434123424
Short name T592
Test name
Test status
Simulation time 37065671868 ps
CPU time 2069.75 seconds
Started Jan 14 03:00:00 PM PST 24
Finished Jan 14 03:34:32 PM PST 24
Peak memory 305656 kb
Host smart-885bf823-7a06-4270-af16-0a7318ee9e10
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434123424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1434123424
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.230567462
Short name T597
Test name
Test status
Simulation time 48302076727 ps
CPU time 5485.91 seconds
Started Jan 14 02:59:57 PM PST 24
Finished Jan 14 04:31:24 PM PST 24
Peak memory 354580 kb
Host smart-f016db51-1ca7-458c-9ebd-7001bbce4810
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230567462 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.230567462
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2433051526
Short name T302
Test name
Test status
Simulation time 94122542680 ps
CPU time 269.74 seconds
Started Jan 14 03:00:03 PM PST 24
Finished Jan 14 03:04:34 PM PST 24
Peak memory 256108 kb
Host smart-18b6b835-07bf-452e-b47c-4134b235ba69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24330
51526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2433051526
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1301023506
Short name T706
Test name
Test status
Simulation time 1800516808 ps
CPU time 23.19 seconds
Started Jan 14 03:00:04 PM PST 24
Finished Jan 14 03:00:28 PM PST 24
Peak memory 248668 kb
Host smart-f31f615f-b859-4e87-8e5d-b9579d8dca3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13010
23506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1301023506
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.943701942
Short name T358
Test name
Test status
Simulation time 58443522360 ps
CPU time 1391.2 seconds
Started Jan 14 03:00:03 PM PST 24
Finished Jan 14 03:23:15 PM PST 24
Peak memory 289200 kb
Host smart-dd9baa61-e7c5-4df1-bcc1-581a0711b858
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943701942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.943701942
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3604907480
Short name T339
Test name
Test status
Simulation time 120313230538 ps
CPU time 383.9 seconds
Started Jan 14 03:00:13 PM PST 24
Finished Jan 14 03:06:38 PM PST 24
Peak memory 247560 kb
Host smart-07d728c5-2bce-4079-baa1-f143d096e023
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604907480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3604907480
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.165919730
Short name T658
Test name
Test status
Simulation time 312834037 ps
CPU time 32.04 seconds
Started Jan 14 02:59:55 PM PST 24
Finished Jan 14 03:00:28 PM PST 24
Peak memory 248608 kb
Host smart-3bd15741-f504-4472-b2bf-9083af53a710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16591
9730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.165919730
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.159015482
Short name T677
Test name
Test status
Simulation time 347327970 ps
CPU time 25.66 seconds
Started Jan 14 03:00:12 PM PST 24
Finished Jan 14 03:00:39 PM PST 24
Peak memory 253728 kb
Host smart-c9b58e4e-0d3c-46b9-a81a-c8f9a7c80e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15901
5482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.159015482
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1947077090
Short name T495
Test name
Test status
Simulation time 830946131 ps
CPU time 46.5 seconds
Started Jan 14 03:00:03 PM PST 24
Finished Jan 14 03:00:51 PM PST 24
Peak memory 255336 kb
Host smart-2434b929-55d8-4845-8b58-56ee27ba91d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19470
77090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1947077090
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2942347967
Short name T390
Test name
Test status
Simulation time 295265530 ps
CPU time 29.45 seconds
Started Jan 14 02:59:58 PM PST 24
Finished Jan 14 03:00:28 PM PST 24
Peak memory 255312 kb
Host smart-46881653-92fc-46d5-8000-ab32e6aa97ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29423
47967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2942347967
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2462785726
Short name T89
Test name
Test status
Simulation time 100595585492 ps
CPU time 1429.16 seconds
Started Jan 14 03:00:06 PM PST 24
Finished Jan 14 03:23:56 PM PST 24
Peak memory 268940 kb
Host smart-9dda83c4-f47a-44f7-a4cd-53f721bace23
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462785726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2462785726
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1742100835
Short name T474
Test name
Test status
Simulation time 16561661586 ps
CPU time 795.5 seconds
Started Jan 14 03:00:04 PM PST 24
Finished Jan 14 03:13:20 PM PST 24
Peak memory 269980 kb
Host smart-d86bc73a-ca36-40a7-8552-838c8a887596
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742100835 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1742100835
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.704746075
Short name T537
Test name
Test status
Simulation time 58920119424 ps
CPU time 1460.65 seconds
Started Jan 14 03:00:18 PM PST 24
Finished Jan 14 03:24:40 PM PST 24
Peak memory 289116 kb
Host smart-d0d41853-1bce-43d0-aade-5754b7766f8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704746075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.704746075
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1468467206
Short name T594
Test name
Test status
Simulation time 3682842430 ps
CPU time 227.15 seconds
Started Jan 14 03:00:03 PM PST 24
Finished Jan 14 03:03:51 PM PST 24
Peak memory 249752 kb
Host smart-648e1bc3-a558-4880-8483-b1322417cdf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14684
67206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1468467206
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.110384369
Short name T614
Test name
Test status
Simulation time 1002365715 ps
CPU time 59.46 seconds
Started Jan 14 03:00:07 PM PST 24
Finished Jan 14 03:01:08 PM PST 24
Peak memory 255400 kb
Host smart-cc05bf76-ab54-436d-858d-34bde6bfda43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11038
4369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.110384369
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.4263352934
Short name T356
Test name
Test status
Simulation time 20312480080 ps
CPU time 1568.7 seconds
Started Jan 14 03:00:14 PM PST 24
Finished Jan 14 03:26:25 PM PST 24
Peak memory 289216 kb
Host smart-72287c24-6baa-472f-b0d2-91d25ac86b3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263352934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.4263352934
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3385448991
Short name T510
Test name
Test status
Simulation time 49730538756 ps
CPU time 3139.54 seconds
Started Jan 14 03:00:11 PM PST 24
Finished Jan 14 03:52:32 PM PST 24
Peak memory 289636 kb
Host smart-e425cc89-a39b-4270-8859-73f1e7dce816
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385448991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3385448991
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1915269795
Short name T380
Test name
Test status
Simulation time 104672400 ps
CPU time 7.75 seconds
Started Jan 14 03:00:03 PM PST 24
Finished Jan 14 03:00:12 PM PST 24
Peak memory 248600 kb
Host smart-efcadf58-7cd2-4782-af3f-b8727bed5034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19152
69795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1915269795
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3771587592
Short name T64
Test name
Test status
Simulation time 1801145451 ps
CPU time 52.59 seconds
Started Jan 14 03:00:04 PM PST 24
Finished Jan 14 03:00:58 PM PST 24
Peak memory 247472 kb
Host smart-3f95e20c-a493-4e34-bfc9-71dbbf6985f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37715
87592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3771587592
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3825366066
Short name T710
Test name
Test status
Simulation time 221353539 ps
CPU time 21.12 seconds
Started Jan 14 03:00:12 PM PST 24
Finished Jan 14 03:00:34 PM PST 24
Peak memory 254812 kb
Host smart-e493eaf2-ff05-4240-b011-eba802f55bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38253
66066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3825366066
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.84590808
Short name T83
Test name
Test status
Simulation time 1754047689 ps
CPU time 32.88 seconds
Started Jan 14 03:00:07 PM PST 24
Finished Jan 14 03:00:40 PM PST 24
Peak memory 255264 kb
Host smart-91d26ba9-34c8-4b49-b5ee-5e99c771b69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84590
808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.84590808
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3257733138
Short name T67
Test name
Test status
Simulation time 4332529520 ps
CPU time 191.17 seconds
Started Jan 14 03:00:17 PM PST 24
Finished Jan 14 03:03:28 PM PST 24
Peak memory 256924 kb
Host smart-6026617a-0e02-45e7-95a7-096267b424cc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257733138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3257733138
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.4093104417
Short name T469
Test name
Test status
Simulation time 256938477569 ps
CPU time 3156.3 seconds
Started Jan 14 03:00:21 PM PST 24
Finished Jan 14 03:52:58 PM PST 24
Peak memory 289124 kb
Host smart-b0754cde-46eb-4bbb-8b08-d021e0bf2c13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093104417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.4093104417
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1299791889
Short name T420
Test name
Test status
Simulation time 1022121790 ps
CPU time 101.53 seconds
Started Jan 14 03:00:19 PM PST 24
Finished Jan 14 03:02:01 PM PST 24
Peak memory 255964 kb
Host smart-4941c8a1-5e47-4632-86e2-3e948715db9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12997
91889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1299791889
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1587430382
Short name T478
Test name
Test status
Simulation time 20656995 ps
CPU time 3.11 seconds
Started Jan 14 03:00:12 PM PST 24
Finished Jan 14 03:00:16 PM PST 24
Peak memory 238796 kb
Host smart-cb873edc-0633-445d-acd1-0417179409ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15874
30382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1587430382
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1765996539
Short name T595
Test name
Test status
Simulation time 32159389165 ps
CPU time 818.01 seconds
Started Jan 14 03:00:23 PM PST 24
Finished Jan 14 03:14:02 PM PST 24
Peak memory 272688 kb
Host smart-cae8291e-80b4-42ab-b5cc-9af1f03f90b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765996539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1765996539
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.128255810
Short name T307
Test name
Test status
Simulation time 29808437679 ps
CPU time 1882.72 seconds
Started Jan 14 03:00:24 PM PST 24
Finished Jan 14 03:31:48 PM PST 24
Peak memory 273232 kb
Host smart-b91e9dd8-230a-477b-9182-8964c5ca9078
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128255810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.128255810
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3696492604
Short name T348
Test name
Test status
Simulation time 56222321393 ps
CPU time 589.38 seconds
Started Jan 14 03:00:23 PM PST 24
Finished Jan 14 03:10:14 PM PST 24
Peak memory 246388 kb
Host smart-751998fe-0fb2-46b7-adb1-ef2ba809e12b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696492604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3696492604
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2974317501
Short name T412
Test name
Test status
Simulation time 682461971 ps
CPU time 47.34 seconds
Started Jan 14 03:00:10 PM PST 24
Finished Jan 14 03:00:59 PM PST 24
Peak memory 248680 kb
Host smart-c19852f1-463c-4a40-b1ba-e24e8adc2445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29743
17501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2974317501
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.292434359
Short name T403
Test name
Test status
Simulation time 1025498640 ps
CPU time 41.06 seconds
Started Jan 14 03:00:13 PM PST 24
Finished Jan 14 03:00:55 PM PST 24
Peak memory 248792 kb
Host smart-256ea0b1-f050-4c43-ab1b-330f0a8b3391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29243
4359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.292434359
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2172360542
Short name T448
Test name
Test status
Simulation time 1760008497 ps
CPU time 51.25 seconds
Started Jan 14 03:00:17 PM PST 24
Finished Jan 14 03:01:09 PM PST 24
Peak memory 255540 kb
Host smart-4996c8cd-0e8c-44d2-97f4-63184c32ec71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21723
60542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2172360542
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3129750780
Short name T717
Test name
Test status
Simulation time 1174593782 ps
CPU time 36.23 seconds
Started Jan 14 03:00:12 PM PST 24
Finished Jan 14 03:00:50 PM PST 24
Peak memory 248624 kb
Host smart-cf2516df-921c-4430-abea-24c36bb99126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31297
50780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3129750780
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.813385628
Short name T578
Test name
Test status
Simulation time 23146693891 ps
CPU time 183.1 seconds
Started Jan 14 03:00:25 PM PST 24
Finished Jan 14 03:03:29 PM PST 24
Peak memory 256860 kb
Host smart-0722f606-7971-4219-86e3-49df2fd0b4c7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813385628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.813385628
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1718998230
Short name T299
Test name
Test status
Simulation time 108026716479 ps
CPU time 2260.2 seconds
Started Jan 14 03:00:24 PM PST 24
Finished Jan 14 03:38:05 PM PST 24
Peak memory 305472 kb
Host smart-08282c0d-03bc-4d2e-a97d-1e47760a7cd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718998230 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1718998230
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2067258795
Short name T635
Test name
Test status
Simulation time 134728017054 ps
CPU time 1909.23 seconds
Started Jan 14 03:00:22 PM PST 24
Finished Jan 14 03:32:12 PM PST 24
Peak memory 273100 kb
Host smart-639fcec5-5bde-4e37-92cb-25b9af2e2f73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067258795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2067258795
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3950035651
Short name T287
Test name
Test status
Simulation time 13270498874 ps
CPU time 192.05 seconds
Started Jan 14 03:00:24 PM PST 24
Finished Jan 14 03:03:37 PM PST 24
Peak memory 249672 kb
Host smart-225187aa-43be-4730-914d-11803a7cbfb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39500
35651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3950035651
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1802699555
Short name T383
Test name
Test status
Simulation time 215622497 ps
CPU time 4.1 seconds
Started Jan 14 03:00:30 PM PST 24
Finished Jan 14 03:00:34 PM PST 24
Peak memory 239584 kb
Host smart-b341be8b-7747-4360-bd29-7a4f20e47773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18026
99555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1802699555
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1572565466
Short name T440
Test name
Test status
Simulation time 42247291083 ps
CPU time 2592.88 seconds
Started Jan 14 03:00:27 PM PST 24
Finished Jan 14 03:43:41 PM PST 24
Peak memory 285524 kb
Host smart-3b23dd2a-d572-48a6-83be-eecd5643977a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572565466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1572565466
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3504092496
Short name T721
Test name
Test status
Simulation time 5817525677 ps
CPU time 223.49 seconds
Started Jan 14 03:00:23 PM PST 24
Finished Jan 14 03:04:07 PM PST 24
Peak memory 247532 kb
Host smart-9cee591b-3fcd-4651-b482-1a510d87760c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504092496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3504092496
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3166234478
Short name T723
Test name
Test status
Simulation time 997604715 ps
CPU time 30.73 seconds
Started Jan 14 03:00:23 PM PST 24
Finished Jan 14 03:00:55 PM PST 24
Peak memory 248528 kb
Host smart-5e4de354-b306-4e18-98fa-c0db333c4611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31662
34478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3166234478
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2493199722
Short name T702
Test name
Test status
Simulation time 1084222766 ps
CPU time 64.55 seconds
Started Jan 14 03:00:25 PM PST 24
Finished Jan 14 03:01:30 PM PST 24
Peak memory 254908 kb
Host smart-2d8f944d-aec9-458c-a2a2-c6ce720b816c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24931
99722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2493199722
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2132691894
Short name T47
Test name
Test status
Simulation time 301032238 ps
CPU time 27.82 seconds
Started Jan 14 03:00:23 PM PST 24
Finished Jan 14 03:00:52 PM PST 24
Peak memory 247728 kb
Host smart-c59925d1-e4fc-4eb8-9c71-02badff61fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21326
91894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2132691894
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1057933650
Short name T585
Test name
Test status
Simulation time 1056904357 ps
CPU time 18.05 seconds
Started Jan 14 03:00:29 PM PST 24
Finished Jan 14 03:00:47 PM PST 24
Peak memory 256828 kb
Host smart-0051df2c-52b0-40fa-a8f1-6173946a198b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10579
33650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1057933650
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1839355130
Short name T54
Test name
Test status
Simulation time 200729584608 ps
CPU time 3222.83 seconds
Started Jan 14 03:00:30 PM PST 24
Finished Jan 14 03:54:14 PM PST 24
Peak memory 287980 kb
Host smart-30e4678d-bed2-48d9-9726-a601d04544f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839355130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1839355130
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.867590771
Short name T520
Test name
Test status
Simulation time 821070023 ps
CPU time 72.67 seconds
Started Jan 14 03:00:33 PM PST 24
Finished Jan 14 03:01:47 PM PST 24
Peak memory 256276 kb
Host smart-a5b5f82d-b0ea-4e21-9a69-38a431b8b76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86759
0771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.867590771
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.4247340605
Short name T483
Test name
Test status
Simulation time 145728301 ps
CPU time 7.8 seconds
Started Jan 14 03:00:29 PM PST 24
Finished Jan 14 03:00:37 PM PST 24
Peak memory 252336 kb
Host smart-8d7a3b1c-2494-41df-bcf8-f4ab70d3c903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42473
40605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4247340605
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.21085996
Short name T364
Test name
Test status
Simulation time 29576817664 ps
CPU time 2073.73 seconds
Started Jan 14 03:00:28 PM PST 24
Finished Jan 14 03:35:03 PM PST 24
Peak memory 281904 kb
Host smart-0d7f1f09-d7ca-424e-80fe-e07f1ac8a315
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21085996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.21085996
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3487821333
Short name T75
Test name
Test status
Simulation time 45806909507 ps
CPU time 1535.5 seconds
Started Jan 14 03:00:28 PM PST 24
Finished Jan 14 03:26:05 PM PST 24
Peak memory 265120 kb
Host smart-029e4f06-bd4a-41bc-b1e0-43cc2e87874c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487821333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3487821333
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2373928061
Short name T650
Test name
Test status
Simulation time 1792222187 ps
CPU time 31.22 seconds
Started Jan 14 03:00:26 PM PST 24
Finished Jan 14 03:00:58 PM PST 24
Peak memory 248680 kb
Host smart-9a913fee-6ba7-4dd2-b617-15b89f86cacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23739
28061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2373928061
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1870279114
Short name T648
Test name
Test status
Simulation time 4162848219 ps
CPU time 60.98 seconds
Started Jan 14 03:00:28 PM PST 24
Finished Jan 14 03:01:30 PM PST 24
Peak memory 248700 kb
Host smart-a3a6e36b-390c-4317-bdac-959b2993631f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18702
79114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1870279114
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3179803918
Short name T501
Test name
Test status
Simulation time 62856359118 ps
CPU time 2335.3 seconds
Started Jan 14 03:00:32 PM PST 24
Finished Jan 14 03:39:29 PM PST 24
Peak memory 289268 kb
Host smart-a8848bf2-5278-4a69-a93f-49a31d79baab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179803918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3179803918
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.4246390628
Short name T267
Test name
Test status
Simulation time 67747108262 ps
CPU time 5275.34 seconds
Started Jan 14 03:00:26 PM PST 24
Finished Jan 14 04:28:23 PM PST 24
Peak memory 330540 kb
Host smart-7ea8c9d8-82ac-4520-bb11-f6ebd91cbd37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246390628 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.4246390628
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.300577548
Short name T712
Test name
Test status
Simulation time 3626941087 ps
CPU time 147.43 seconds
Started Jan 14 03:01:11 PM PST 24
Finished Jan 14 03:03:42 PM PST 24
Peak memory 249768 kb
Host smart-a7930b73-fc6f-4813-bc6e-4853e45019a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30057
7548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.300577548
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.4244428741
Short name T640
Test name
Test status
Simulation time 95466416 ps
CPU time 7.24 seconds
Started Jan 14 03:01:08 PM PST 24
Finished Jan 14 03:01:18 PM PST 24
Peak memory 251328 kb
Host smart-c3291e4c-e18c-4698-8a13-51ff79b52482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42444
28741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.4244428741
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1674792466
Short name T317
Test name
Test status
Simulation time 23395963770 ps
CPU time 1027.49 seconds
Started Jan 14 03:01:07 PM PST 24
Finished Jan 14 03:18:18 PM PST 24
Peak memory 265112 kb
Host smart-2499a821-f3ac-47ec-9adf-f5cea3a51577
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674792466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1674792466
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3428670025
Short name T327
Test name
Test status
Simulation time 8712114217 ps
CPU time 371.33 seconds
Started Jan 14 03:01:09 PM PST 24
Finished Jan 14 03:07:22 PM PST 24
Peak memory 246548 kb
Host smart-89eaa536-dee6-4b4c-8186-6be841ba211a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428670025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3428670025
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1571990992
Short name T709
Test name
Test status
Simulation time 1750826160 ps
CPU time 60.95 seconds
Started Jan 14 03:01:08 PM PST 24
Finished Jan 14 03:02:12 PM PST 24
Peak memory 248680 kb
Host smart-d8dcc811-1a89-4074-bcfd-d04851e904cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15719
90992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1571990992
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3745924439
Short name T540
Test name
Test status
Simulation time 108104946 ps
CPU time 8.44 seconds
Started Jan 14 03:01:10 PM PST 24
Finished Jan 14 03:01:22 PM PST 24
Peak memory 251052 kb
Host smart-f3b7b87d-ced8-4b34-9574-689049a10f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37459
24439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3745924439
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2507962822
Short name T415
Test name
Test status
Simulation time 8733918363 ps
CPU time 41.25 seconds
Started Jan 14 03:01:08 PM PST 24
Finished Jan 14 03:01:52 PM PST 24
Peak memory 255380 kb
Host smart-5db8cfd9-8d6a-44f9-a4e4-f42cb2c30b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25079
62822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2507962822
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3642803020
Short name T401
Test name
Test status
Simulation time 394082008 ps
CPU time 21.67 seconds
Started Jan 14 03:01:10 PM PST 24
Finished Jan 14 03:01:36 PM PST 24
Peak memory 248800 kb
Host smart-8828fbbc-abce-4741-8cdf-bbc906ad7371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36428
03020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3642803020
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1515625231
Short name T50
Test name
Test status
Simulation time 316920170952 ps
CPU time 3898.34 seconds
Started Jan 14 03:01:12 PM PST 24
Finished Jan 14 04:06:14 PM PST 24
Peak memory 299916 kb
Host smart-4a0e2ca0-72fb-4de3-8e72-fc8770bdaecd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515625231 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1515625231
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2101256423
Short name T244
Test name
Test status
Simulation time 28695158562 ps
CPU time 2108.47 seconds
Started Jan 14 03:00:47 PM PST 24
Finished Jan 14 03:36:01 PM PST 24
Peak memory 282784 kb
Host smart-02b2c026-11a1-4803-981e-66f43289931a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101256423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2101256423
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2353257641
Short name T553
Test name
Test status
Simulation time 1881103815 ps
CPU time 67.02 seconds
Started Jan 14 03:00:50 PM PST 24
Finished Jan 14 03:02:00 PM PST 24
Peak memory 248684 kb
Host smart-f7dce8ea-4867-4ade-9422-c5fc7a1e9560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23532
57641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2353257641
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.200496917
Short name T397
Test name
Test status
Simulation time 76554269 ps
CPU time 6.02 seconds
Started Jan 14 03:00:46 PM PST 24
Finished Jan 14 03:00:53 PM PST 24
Peak memory 252596 kb
Host smart-b3e255a2-43ea-42ee-939e-0adde401034e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20049
6917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.200496917
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.4038689956
Short name T698
Test name
Test status
Simulation time 16452769570 ps
CPU time 1375.1 seconds
Started Jan 14 03:00:46 PM PST 24
Finished Jan 14 03:23:42 PM PST 24
Peak memory 289472 kb
Host smart-1e0ecd58-948f-4a9c-bb37-b696c85ad07b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038689956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.4038689956
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1600986258
Short name T289
Test name
Test status
Simulation time 42397956947 ps
CPU time 2411.81 seconds
Started Jan 14 03:00:48 PM PST 24
Finished Jan 14 03:41:05 PM PST 24
Peak memory 289112 kb
Host smart-35643ea7-5c43-4724-9422-bb7bde4494cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600986258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1600986258
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1531886445
Short name T507
Test name
Test status
Simulation time 29222800264 ps
CPU time 175.11 seconds
Started Jan 14 03:00:46 PM PST 24
Finished Jan 14 03:03:43 PM PST 24
Peak memory 247300 kb
Host smart-ec33027f-5c77-4e62-9970-9fd256105ee1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531886445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1531886445
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.185052047
Short name T428
Test name
Test status
Simulation time 2726981068 ps
CPU time 39.25 seconds
Started Jan 14 03:01:17 PM PST 24
Finished Jan 14 03:01:58 PM PST 24
Peak memory 248692 kb
Host smart-5eaff591-1f26-4286-a93f-fa34706b80bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18505
2047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.185052047
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1731589276
Short name T72
Test name
Test status
Simulation time 1566483694 ps
CPU time 33.34 seconds
Started Jan 14 03:00:45 PM PST 24
Finished Jan 14 03:01:19 PM PST 24
Peak memory 255212 kb
Host smart-71e7e047-93d4-4b57-88b4-fc41b5beed02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17315
89276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1731589276
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3350586563
Short name T17
Test name
Test status
Simulation time 799225861 ps
CPU time 35.7 seconds
Started Jan 14 03:01:16 PM PST 24
Finished Jan 14 03:01:52 PM PST 24
Peak memory 248680 kb
Host smart-2ed3f059-c4d0-4283-b6cd-0fa670ac013d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33505
86563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3350586563
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2847028286
Short name T442
Test name
Test status
Simulation time 25787903752 ps
CPU time 393.3 seconds
Started Jan 14 03:00:44 PM PST 24
Finished Jan 14 03:07:18 PM PST 24
Peak memory 256148 kb
Host smart-7939ea9a-281b-4b19-84ec-36fa9505ef91
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847028286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2847028286
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.4136429380
Short name T407
Test name
Test status
Simulation time 2415636208 ps
CPU time 64.94 seconds
Started Jan 14 03:00:44 PM PST 24
Finished Jan 14 03:01:49 PM PST 24
Peak memory 248304 kb
Host smart-1b10ac52-93ed-47cf-bb7a-dd02f43790c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41364
29380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.4136429380
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1737255666
Short name T402
Test name
Test status
Simulation time 91538321 ps
CPU time 11.4 seconds
Started Jan 14 03:00:47 PM PST 24
Finished Jan 14 03:01:03 PM PST 24
Peak memory 254120 kb
Host smart-e32be49c-f9b3-4ab2-8bc9-be9cd47846c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17372
55666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1737255666
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.266390835
Short name T114
Test name
Test status
Simulation time 50110430428 ps
CPU time 921.82 seconds
Started Jan 14 03:00:45 PM PST 24
Finished Jan 14 03:16:09 PM PST 24
Peak memory 272388 kb
Host smart-fd1f0035-dd05-4e4d-90a9-c07ec095e8a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266390835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.266390835
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.475089737
Short name T324
Test name
Test status
Simulation time 12612208350 ps
CPU time 522.41 seconds
Started Jan 14 03:00:46 PM PST 24
Finished Jan 14 03:09:29 PM PST 24
Peak memory 247300 kb
Host smart-71cbb9d5-e95b-4563-b1ec-7aca24f5151d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475089737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.475089737
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3813083155
Short name T571
Test name
Test status
Simulation time 113150940 ps
CPU time 11.43 seconds
Started Jan 14 03:00:43 PM PST 24
Finished Jan 14 03:00:55 PM PST 24
Peak memory 255556 kb
Host smart-021458f9-154e-42ff-a96d-b196164f050c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38130
83155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3813083155
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3881856746
Short name T680
Test name
Test status
Simulation time 2857433698 ps
CPU time 37.47 seconds
Started Jan 14 03:00:44 PM PST 24
Finished Jan 14 03:01:23 PM PST 24
Peak memory 247796 kb
Host smart-407ba3e6-3b4f-4095-a5ee-727424845009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38818
56746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3881856746
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2436847432
Short name T391
Test name
Test status
Simulation time 7004741849 ps
CPU time 31.09 seconds
Started Jan 14 03:00:45 PM PST 24
Finished Jan 14 03:01:17 PM PST 24
Peak memory 248660 kb
Host smart-575d2ac0-7c99-4422-92fc-955aeddbcca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24368
47432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2436847432
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2714666635
Short name T140
Test name
Test status
Simulation time 1807264200 ps
CPU time 54.62 seconds
Started Jan 14 03:00:46 PM PST 24
Finished Jan 14 03:01:42 PM PST 24
Peak memory 248756 kb
Host smart-0dea167b-92b4-4276-806b-9ae29bc8cfff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27146
66635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2714666635
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3566409058
Short name T255
Test name
Test status
Simulation time 52968801037 ps
CPU time 2208.13 seconds
Started Jan 14 03:01:13 PM PST 24
Finished Jan 14 03:38:04 PM PST 24
Peak memory 273188 kb
Host smart-3db6b471-9503-436a-bd17-bcbaa6a91888
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566409058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3566409058
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1468821135
Short name T586
Test name
Test status
Simulation time 7108420183 ps
CPU time 193.45 seconds
Started Jan 14 03:01:12 PM PST 24
Finished Jan 14 03:04:29 PM PST 24
Peak memory 255968 kb
Host smart-b187f247-976b-4bd2-b5d6-2953d0ed5adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14688
21135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1468821135
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1765783077
Short name T691
Test name
Test status
Simulation time 1106580944 ps
CPU time 57.31 seconds
Started Jan 14 03:01:14 PM PST 24
Finished Jan 14 03:02:13 PM PST 24
Peak memory 254304 kb
Host smart-5e3cbcd0-4acf-480b-a109-0576e4a6d4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17657
83077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1765783077
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1434285000
Short name T646
Test name
Test status
Simulation time 26769603660 ps
CPU time 1551.23 seconds
Started Jan 14 03:01:15 PM PST 24
Finished Jan 14 03:27:08 PM PST 24
Peak memory 289012 kb
Host smart-6cfc6769-ec81-48b7-a510-126906b55b84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434285000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1434285000
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1638103167
Short name T321
Test name
Test status
Simulation time 7457477989 ps
CPU time 77.79 seconds
Started Jan 14 03:01:15 PM PST 24
Finished Jan 14 03:02:34 PM PST 24
Peak memory 246576 kb
Host smart-cc0af8c7-1959-45b8-9f2f-c29ee8ed2f00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638103167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1638103167
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.932412053
Short name T581
Test name
Test status
Simulation time 1238142498 ps
CPU time 68.54 seconds
Started Jan 14 03:01:17 PM PST 24
Finished Jan 14 03:02:27 PM PST 24
Peak memory 255528 kb
Host smart-29683146-a61a-4305-a533-ad3e990001f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93241
2053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.932412053
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1135114418
Short name T518
Test name
Test status
Simulation time 576955375 ps
CPU time 35.25 seconds
Started Jan 14 03:01:24 PM PST 24
Finished Jan 14 03:02:01 PM PST 24
Peak memory 254880 kb
Host smart-05bd18f3-a859-4c87-aa5c-cf8f3b9cba9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11351
14418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1135114418
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1749296039
Short name T96
Test name
Test status
Simulation time 1182760746 ps
CPU time 21.99 seconds
Started Jan 14 03:01:09 PM PST 24
Finished Jan 14 03:01:34 PM PST 24
Peak memory 253528 kb
Host smart-0d969da8-3b08-4720-a12f-a81610ff1d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17492
96039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1749296039
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.773545781
Short name T245
Test name
Test status
Simulation time 405030516 ps
CPU time 25.49 seconds
Started Jan 14 03:01:16 PM PST 24
Finished Jan 14 03:01:42 PM PST 24
Peak memory 248752 kb
Host smart-aa97195c-1058-4580-bb24-82938c448832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77354
5781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.773545781
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1563552982
Short name T574
Test name
Test status
Simulation time 141604485445 ps
CPU time 3488.4 seconds
Started Jan 14 03:01:16 PM PST 24
Finished Jan 14 03:59:25 PM PST 24
Peak memory 289136 kb
Host smart-84f07d75-ac12-4976-9585-b01fadbbdd25
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563552982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1563552982
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2908935815
Short name T105
Test name
Test status
Simulation time 93396081861 ps
CPU time 1647.61 seconds
Started Jan 14 03:00:58 PM PST 24
Finished Jan 14 03:28:27 PM PST 24
Peak memory 285508 kb
Host smart-f82dc74f-e2a1-419a-b974-444814f0a0e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908935815 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2908935815
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1387324886
Short name T226
Test name
Test status
Simulation time 26129429 ps
CPU time 2.33 seconds
Started Jan 14 02:58:53 PM PST 24
Finished Jan 14 02:58:57 PM PST 24
Peak memory 248864 kb
Host smart-b5e864b2-d565-48b8-ba1a-b82c8664cb0f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1387324886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1387324886
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1330262869
Short name T449
Test name
Test status
Simulation time 162087428130 ps
CPU time 1750.7 seconds
Started Jan 14 02:58:55 PM PST 24
Finished Jan 14 03:28:08 PM PST 24
Peak memory 272620 kb
Host smart-1aab36f0-b12d-4a4a-942f-6e67bc8f3662
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330262869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1330262869
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1669888902
Short name T4
Test name
Test status
Simulation time 169500861 ps
CPU time 9.87 seconds
Started Jan 14 02:58:56 PM PST 24
Finished Jan 14 02:59:07 PM PST 24
Peak memory 248684 kb
Host smart-2e50cd0a-d754-42d2-af46-19c756ca92b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1669888902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1669888902
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1810627873
Short name T620
Test name
Test status
Simulation time 1642778403 ps
CPU time 25.33 seconds
Started Jan 14 02:58:57 PM PST 24
Finished Jan 14 02:59:24 PM PST 24
Peak memory 255368 kb
Host smart-4bed6202-7057-4a64-9b73-85fc184fab78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18106
27873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1810627873
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.79591437
Short name T443
Test name
Test status
Simulation time 110505744 ps
CPU time 7.92 seconds
Started Jan 14 02:58:58 PM PST 24
Finished Jan 14 02:59:07 PM PST 24
Peak memory 240452 kb
Host smart-428eeeec-8c0a-40fc-8826-1e99bde00a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79591
437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.79591437
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1788865036
Short name T363
Test name
Test status
Simulation time 58676380629 ps
CPU time 1252.91 seconds
Started Jan 14 02:58:57 PM PST 24
Finished Jan 14 03:19:52 PM PST 24
Peak memory 289608 kb
Host smart-d14c31b1-e2fa-4546-895c-795345e74e95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788865036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1788865036
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.4108352565
Short name T6
Test name
Test status
Simulation time 214709007338 ps
CPU time 3274.26 seconds
Started Jan 14 02:58:57 PM PST 24
Finished Jan 14 03:53:33 PM PST 24
Peak memory 289104 kb
Host smart-50132dcd-7aed-4515-8966-4c47b2f818dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108352565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.4108352565
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2073441632
Short name T328
Test name
Test status
Simulation time 11485264544 ps
CPU time 495.49 seconds
Started Jan 14 02:59:00 PM PST 24
Finished Jan 14 03:07:16 PM PST 24
Peak memory 247548 kb
Host smart-79a092e0-ab3a-4b6c-a173-6eba9483e275
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073441632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2073441632
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3515038430
Short name T292
Test name
Test status
Simulation time 3141649182 ps
CPU time 46.77 seconds
Started Jan 14 02:58:58 PM PST 24
Finished Jan 14 02:59:46 PM PST 24
Peak memory 248740 kb
Host smart-c72a7241-8593-4e05-8092-8ba58625ec14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35150
38430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3515038430
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3395728303
Short name T671
Test name
Test status
Simulation time 223205235 ps
CPU time 14.85 seconds
Started Jan 14 02:58:54 PM PST 24
Finished Jan 14 02:59:11 PM PST 24
Peak memory 252460 kb
Host smart-04e002dc-cbe7-4d81-82ab-4780e3a93886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33957
28303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3395728303
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2283600197
Short name T11
Test name
Test status
Simulation time 693113055 ps
CPU time 11.25 seconds
Started Jan 14 02:58:57 PM PST 24
Finished Jan 14 02:59:09 PM PST 24
Peak memory 272496 kb
Host smart-ca64afa3-06dc-4b5c-bd4c-731caf665445
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2283600197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2283600197
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2753046454
Short name T532
Test name
Test status
Simulation time 543872003 ps
CPU time 21.35 seconds
Started Jan 14 02:58:56 PM PST 24
Finished Jan 14 02:59:19 PM PST 24
Peak memory 248728 kb
Host smart-84bbe00c-34af-4832-8894-5e0abae8b714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27530
46454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2753046454
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3009642415
Short name T494
Test name
Test status
Simulation time 28916575 ps
CPU time 3.04 seconds
Started Jan 14 02:58:58 PM PST 24
Finished Jan 14 02:59:02 PM PST 24
Peak memory 240412 kb
Host smart-cd19fcb1-5408-4951-86ac-11f3d05751e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30096
42415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3009642415
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2142995932
Short name T55
Test name
Test status
Simulation time 29684730964 ps
CPU time 934.88 seconds
Started Jan 14 02:58:58 PM PST 24
Finished Jan 14 03:14:34 PM PST 24
Peak memory 272736 kb
Host smart-dff77395-a093-4220-bcc4-a02e3c3bc19a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142995932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2142995932
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.907888578
Short name T68
Test name
Test status
Simulation time 44659086689 ps
CPU time 1405.57 seconds
Started Jan 14 02:58:59 PM PST 24
Finished Jan 14 03:22:25 PM PST 24
Peak memory 281228 kb
Host smart-d5e06620-6ebf-454e-9dcd-f8402203c09a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907888578 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.907888578
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3159383229
Short name T645
Test name
Test status
Simulation time 168730262914 ps
CPU time 2785.14 seconds
Started Jan 14 03:01:00 PM PST 24
Finished Jan 14 03:47:26 PM PST 24
Peak memory 289428 kb
Host smart-c8946d8f-1b26-4b86-885a-66c7975ce698
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159383229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3159383229
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1645579070
Short name T558
Test name
Test status
Simulation time 8381649115 ps
CPU time 116.93 seconds
Started Jan 14 03:01:00 PM PST 24
Finished Jan 14 03:02:58 PM PST 24
Peak memory 256508 kb
Host smart-73fb6e16-1818-47d2-80d6-916a85e618bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16455
79070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1645579070
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1549875749
Short name T21
Test name
Test status
Simulation time 975640960 ps
CPU time 29.49 seconds
Started Jan 14 03:01:00 PM PST 24
Finished Jan 14 03:01:31 PM PST 24
Peak memory 255108 kb
Host smart-5e49e3c1-099b-453c-b6c7-089192ed5114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15498
75749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1549875749
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.264032437
Short name T128
Test name
Test status
Simulation time 171018712455 ps
CPU time 1318.81 seconds
Started Jan 14 03:00:58 PM PST 24
Finished Jan 14 03:22:58 PM PST 24
Peak memory 289220 kb
Host smart-7e176078-2666-488d-86e0-1490473fd058
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264032437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.264032437
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.4110619689
Short name T333
Test name
Test status
Simulation time 9677386078 ps
CPU time 414.63 seconds
Started Jan 14 03:00:58 PM PST 24
Finished Jan 14 03:07:54 PM PST 24
Peak memory 247596 kb
Host smart-e55792ae-de06-48c8-a383-74177a199b02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110619689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.4110619689
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.866277620
Short name T59
Test name
Test status
Simulation time 2054860279 ps
CPU time 63.16 seconds
Started Jan 14 03:00:59 PM PST 24
Finished Jan 14 03:02:03 PM PST 24
Peak memory 255212 kb
Host smart-06c4727c-8b06-4b31-a753-6339b7b5ccb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86627
7620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.866277620
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2824692001
Short name T40
Test name
Test status
Simulation time 2841123753 ps
CPU time 53.41 seconds
Started Jan 14 03:00:59 PM PST 24
Finished Jan 14 03:01:54 PM PST 24
Peak memory 254448 kb
Host smart-289047ca-5e26-4f95-a1a5-e68dc604e33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28246
92001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2824692001
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1641408597
Short name T687
Test name
Test status
Simulation time 300194085 ps
CPU time 5.74 seconds
Started Jan 14 03:01:01 PM PST 24
Finished Jan 14 03:01:08 PM PST 24
Peak memory 248612 kb
Host smart-c467d482-d0bb-402c-b7ae-25b2fed47108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16414
08597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1641408597
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1338312985
Short name T411
Test name
Test status
Simulation time 737154002 ps
CPU time 47.99 seconds
Started Jan 14 03:00:59 PM PST 24
Finished Jan 14 03:01:48 PM PST 24
Peak memory 248592 kb
Host smart-b37c9026-42ad-4301-942d-7c3899e7f55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13383
12985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1338312985
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.625686865
Short name T485
Test name
Test status
Simulation time 105974767907 ps
CPU time 1747.42 seconds
Started Jan 14 03:00:58 PM PST 24
Finished Jan 14 03:30:07 PM PST 24
Peak memory 273304 kb
Host smart-f32cc8f2-96fb-49d6-ada3-9381d4ecb752
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625686865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.625686865
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.146804961
Short name T566
Test name
Test status
Simulation time 23592506184 ps
CPU time 2861.02 seconds
Started Jan 14 03:01:00 PM PST 24
Finished Jan 14 03:48:42 PM PST 24
Peak memory 321752 kb
Host smart-44752328-1973-41fc-a59e-2bba4194f048
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146804961 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.146804961
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3646298955
Short name T492
Test name
Test status
Simulation time 59546438248 ps
CPU time 2057.38 seconds
Started Jan 14 03:01:15 PM PST 24
Finished Jan 14 03:35:33 PM PST 24
Peak memory 273168 kb
Host smart-ce5cd2b5-15ad-4bc5-b69c-e15eed6b873a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646298955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3646298955
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1359741477
Short name T575
Test name
Test status
Simulation time 3925198638 ps
CPU time 90.4 seconds
Started Jan 14 03:01:21 PM PST 24
Finished Jan 14 03:02:52 PM PST 24
Peak memory 256144 kb
Host smart-a978dd3b-ad34-48db-b90b-1a22eb92242c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13597
41477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1359741477
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.962883259
Short name T496
Test name
Test status
Simulation time 4282012516 ps
CPU time 28.24 seconds
Started Jan 14 03:01:18 PM PST 24
Finished Jan 14 03:01:47 PM PST 24
Peak memory 248912 kb
Host smart-888f8626-8cd4-46c3-b072-02ef7facf968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96288
3259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.962883259
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3141777987
Short name T622
Test name
Test status
Simulation time 22805740605 ps
CPU time 1313.83 seconds
Started Jan 14 03:01:17 PM PST 24
Finished Jan 14 03:23:12 PM PST 24
Peak memory 271820 kb
Host smart-d0c9b9f8-9c3d-4d5b-a4a3-d20302fedf58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141777987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3141777987
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2275359659
Short name T5
Test name
Test status
Simulation time 8444559464 ps
CPU time 338.12 seconds
Started Jan 14 03:01:19 PM PST 24
Finished Jan 14 03:06:58 PM PST 24
Peak memory 246524 kb
Host smart-8c4141f5-e6ee-4578-94e6-c85969aea490
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275359659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2275359659
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.981163940
Short name T568
Test name
Test status
Simulation time 4216580054 ps
CPU time 63.76 seconds
Started Jan 14 03:01:19 PM PST 24
Finished Jan 14 03:02:24 PM PST 24
Peak memory 248752 kb
Host smart-58ebe717-8cbe-45a2-9aac-bbb534e87e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98116
3940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.981163940
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2059275957
Short name T479
Test name
Test status
Simulation time 251282987 ps
CPU time 26.5 seconds
Started Jan 14 03:01:17 PM PST 24
Finished Jan 14 03:01:45 PM PST 24
Peak memory 248868 kb
Host smart-34a3ae4b-834a-4c58-8f12-d41b539a2183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20592
75957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2059275957
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1423573105
Short name T265
Test name
Test status
Simulation time 264150298 ps
CPU time 19.83 seconds
Started Jan 14 03:01:20 PM PST 24
Finished Jan 14 03:01:41 PM PST 24
Peak memory 255780 kb
Host smart-1be89196-e3c7-44ca-abcd-a1a62b53cda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14235
73105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1423573105
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1253757683
Short name T381
Test name
Test status
Simulation time 278162741 ps
CPU time 25.72 seconds
Started Jan 14 03:01:15 PM PST 24
Finished Jan 14 03:01:42 PM PST 24
Peak memory 248544 kb
Host smart-37c4c67c-ac93-4260-bf98-f8664f898c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12537
57683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1253757683
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1353976172
Short name T94
Test name
Test status
Simulation time 25377880712 ps
CPU time 1845.06 seconds
Started Jan 14 03:01:17 PM PST 24
Finished Jan 14 03:32:03 PM PST 24
Peak memory 273304 kb
Host smart-417a94a2-93ff-429c-8d04-4dba5268356e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353976172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1353976172
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1215040610
Short name T273
Test name
Test status
Simulation time 26776019440 ps
CPU time 2713.01 seconds
Started Jan 14 03:01:17 PM PST 24
Finished Jan 14 03:46:32 PM PST 24
Peak memory 301244 kb
Host smart-362189b8-3c7a-406c-9b07-f6c06e3601be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215040610 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1215040610
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1150974037
Short name T601
Test name
Test status
Simulation time 47567539504 ps
CPU time 899.29 seconds
Started Jan 14 03:01:24 PM PST 24
Finished Jan 14 03:16:24 PM PST 24
Peak memory 273128 kb
Host smart-3d18b4be-eeae-4d34-9fae-7e13d7c71385
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150974037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1150974037
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3114482227
Short name T551
Test name
Test status
Simulation time 709630286 ps
CPU time 53.47 seconds
Started Jan 14 03:01:22 PM PST 24
Finished Jan 14 03:02:16 PM PST 24
Peak memory 256276 kb
Host smart-7b749aa2-487e-4cda-9ba2-b3bfa89c4d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31144
82227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3114482227
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3618879276
Short name T400
Test name
Test status
Simulation time 1409031488 ps
CPU time 29.65 seconds
Started Jan 14 03:01:21 PM PST 24
Finished Jan 14 03:01:52 PM PST 24
Peak memory 248700 kb
Host smart-5bce9b44-65b8-4a76-908a-ddc2d36de5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36188
79276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3618879276
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3270684111
Short name T441
Test name
Test status
Simulation time 108640854854 ps
CPU time 3530.63 seconds
Started Jan 14 03:01:18 PM PST 24
Finished Jan 14 04:00:10 PM PST 24
Peak memory 289644 kb
Host smart-fa3c9a56-5c63-4de7-a7b5-5b6f4fd81e53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270684111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3270684111
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3355902213
Short name T587
Test name
Test status
Simulation time 45466322738 ps
CPU time 523.85 seconds
Started Jan 14 03:01:21 PM PST 24
Finished Jan 14 03:10:06 PM PST 24
Peak memory 247628 kb
Host smart-e2a2c382-47f1-42a5-bedb-ceeca934ba1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355902213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3355902213
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.4247313092
Short name T456
Test name
Test status
Simulation time 354078372 ps
CPU time 23.88 seconds
Started Jan 14 03:01:18 PM PST 24
Finished Jan 14 03:01:43 PM PST 24
Peak memory 248672 kb
Host smart-d9a4e99f-2d97-4d0d-a281-a1e6244c039a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42473
13092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.4247313092
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3775823392
Short name T502
Test name
Test status
Simulation time 3780481234 ps
CPU time 61.7 seconds
Started Jan 14 03:01:19 PM PST 24
Finished Jan 14 03:02:21 PM PST 24
Peak memory 256248 kb
Host smart-39cf7e47-9115-45c5-b3c7-243a32e7cb0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37758
23392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3775823392
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3003969562
Short name T82
Test name
Test status
Simulation time 622861693 ps
CPU time 25.18 seconds
Started Jan 14 03:01:15 PM PST 24
Finished Jan 14 03:01:41 PM PST 24
Peak memory 255292 kb
Host smart-19b4e37c-0b5d-460c-a0b9-00701c28f14d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30039
69562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3003969562
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.4140108010
Short name T630
Test name
Test status
Simulation time 3374302018 ps
CPU time 48.05 seconds
Started Jan 14 03:01:17 PM PST 24
Finished Jan 14 03:02:06 PM PST 24
Peak memory 255768 kb
Host smart-9c1d7570-31ad-4532-b8b7-dd6f79a8282c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41401
08010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.4140108010
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2199329252
Short name T425
Test name
Test status
Simulation time 660400190 ps
CPU time 38.06 seconds
Started Jan 14 03:01:24 PM PST 24
Finished Jan 14 03:02:03 PM PST 24
Peak memory 255780 kb
Host smart-247a9ae3-8525-4c94-a7ee-549e046b0ac3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199329252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2199329252
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3462638096
Short name T268
Test name
Test status
Simulation time 33544230604 ps
CPU time 1132.63 seconds
Started Jan 14 03:01:20 PM PST 24
Finished Jan 14 03:20:14 PM PST 24
Peak memory 289308 kb
Host smart-0a16c9f5-fde4-41ac-8cf3-b5ee52d67623
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462638096 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3462638096
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.62151759
Short name T104
Test name
Test status
Simulation time 26351014080 ps
CPU time 767.28 seconds
Started Jan 14 03:01:24 PM PST 24
Finished Jan 14 03:14:13 PM PST 24
Peak memory 272184 kb
Host smart-4cd6f6ad-565b-4a0c-bcd8-f046ed1784a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62151759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.62151759
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.167617445
Short name T308
Test name
Test status
Simulation time 818413194 ps
CPU time 76.89 seconds
Started Jan 14 03:01:24 PM PST 24
Finished Jan 14 03:02:42 PM PST 24
Peak memory 256144 kb
Host smart-b774485e-cdc7-4262-9cd2-08253aeb6a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16761
7445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.167617445
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3401370522
Short name T393
Test name
Test status
Simulation time 2755944291 ps
CPU time 50.81 seconds
Started Jan 14 03:01:23 PM PST 24
Finished Jan 14 03:02:15 PM PST 24
Peak memory 254524 kb
Host smart-2e15bb13-e565-4305-bf70-c3f021d45907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34013
70522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3401370522
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1340171645
Short name T355
Test name
Test status
Simulation time 59788972369 ps
CPU time 1570.82 seconds
Started Jan 14 03:01:24 PM PST 24
Finished Jan 14 03:27:37 PM PST 24
Peak memory 289092 kb
Host smart-c64d747b-afd7-4454-a2d6-5d66d64c7d2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340171645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1340171645
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3531188926
Short name T433
Test name
Test status
Simulation time 170956715978 ps
CPU time 2771.63 seconds
Started Jan 14 03:01:26 PM PST 24
Finished Jan 14 03:47:39 PM PST 24
Peak memory 285456 kb
Host smart-be7b5ed4-543e-423c-9140-8f981d29115b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531188926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3531188926
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3692189710
Short name T349
Test name
Test status
Simulation time 3840833826 ps
CPU time 151.39 seconds
Started Jan 14 03:01:26 PM PST 24
Finished Jan 14 03:03:58 PM PST 24
Peak memory 247340 kb
Host smart-a77f44ac-df59-470c-a5ef-795f0f8d68b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692189710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3692189710
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1402598190
Short name T516
Test name
Test status
Simulation time 85576821 ps
CPU time 7.15 seconds
Started Jan 14 03:01:16 PM PST 24
Finished Jan 14 03:01:24 PM PST 24
Peak memory 248720 kb
Host smart-d83956c9-7654-4799-b90d-0fbbe459fb13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14025
98190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1402598190
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.581702872
Short name T416
Test name
Test status
Simulation time 907222086 ps
CPU time 15.31 seconds
Started Jan 14 03:01:16 PM PST 24
Finished Jan 14 03:01:32 PM PST 24
Peak memory 252676 kb
Host smart-a99af05a-8a54-46c8-84cd-f8d705047c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58170
2872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.581702872
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2846522614
Short name T262
Test name
Test status
Simulation time 8976772061 ps
CPU time 56.52 seconds
Started Jan 14 03:01:23 PM PST 24
Finished Jan 14 03:02:20 PM PST 24
Peak memory 256736 kb
Host smart-e413909b-b6ac-463f-a2a2-6431b7e00ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28465
22614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2846522614
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3404779730
Short name T394
Test name
Test status
Simulation time 632587512 ps
CPU time 40.2 seconds
Started Jan 14 03:01:17 PM PST 24
Finished Jan 14 03:01:58 PM PST 24
Peak memory 248676 kb
Host smart-182e05c6-aaa2-4769-a27d-eb1f57f3f47e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34047
79730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3404779730
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2963077794
Short name T34
Test name
Test status
Simulation time 140663481329 ps
CPU time 2441.89 seconds
Started Jan 14 03:01:24 PM PST 24
Finished Jan 14 03:42:07 PM PST 24
Peak memory 286164 kb
Host smart-83dbfa91-3662-47d4-94b9-b5a7fde0aea1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963077794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2963077794
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2395529878
Short name T686
Test name
Test status
Simulation time 173898353074 ps
CPU time 2015.94 seconds
Started Jan 14 03:01:24 PM PST 24
Finished Jan 14 03:35:01 PM PST 24
Peak memory 289316 kb
Host smart-e948614e-7ee8-44eb-9a5e-800c80aa0953
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395529878 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2395529878
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1380731559
Short name T134
Test name
Test status
Simulation time 46254595659 ps
CPU time 1262.15 seconds
Started Jan 14 03:01:33 PM PST 24
Finished Jan 14 03:22:36 PM PST 24
Peak memory 285632 kb
Host smart-4be8f874-c195-43ac-8c24-513f8056510d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380731559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1380731559
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.896016767
Short name T524
Test name
Test status
Simulation time 2041807057 ps
CPU time 67.31 seconds
Started Jan 14 03:01:33 PM PST 24
Finished Jan 14 03:02:42 PM PST 24
Peak memory 255932 kb
Host smart-82c802eb-6f0c-4466-a641-efe826f67348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89601
6767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.896016767
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.462203850
Short name T623
Test name
Test status
Simulation time 908425373 ps
CPU time 6.67 seconds
Started Jan 14 03:01:32 PM PST 24
Finished Jan 14 03:01:39 PM PST 24
Peak memory 239880 kb
Host smart-e4f3296d-2881-4e68-ae47-c760c9f4c852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46220
3850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.462203850
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.609647946
Short name T694
Test name
Test status
Simulation time 24793342097 ps
CPU time 1386.77 seconds
Started Jan 14 03:01:36 PM PST 24
Finished Jan 14 03:24:43 PM PST 24
Peak memory 287348 kb
Host smart-28c0ff1a-49c5-4b92-a602-e73f1e5540e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609647946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.609647946
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1208404655
Short name T693
Test name
Test status
Simulation time 17777570299 ps
CPU time 1851.52 seconds
Started Jan 14 03:01:33 PM PST 24
Finished Jan 14 03:32:26 PM PST 24
Peak memory 289100 kb
Host smart-c99b28e0-872d-46ca-b2e4-cc376b75ff3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208404655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1208404655
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3052826917
Short name T436
Test name
Test status
Simulation time 8488080305 ps
CPU time 54.43 seconds
Started Jan 14 03:01:33 PM PST 24
Finished Jan 14 03:02:29 PM PST 24
Peak memory 248652 kb
Host smart-ff404950-2dba-4e1e-9d87-95fe37b0e89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30528
26917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3052826917
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3063880021
Short name T84
Test name
Test status
Simulation time 553192599 ps
CPU time 28.15 seconds
Started Jan 14 03:01:33 PM PST 24
Finished Jan 14 03:02:03 PM PST 24
Peak memory 255220 kb
Host smart-bb2a37ea-84c9-4d0b-9f08-5ac5cbd6f5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30638
80021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3063880021
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.4226281851
Short name T282
Test name
Test status
Simulation time 183350692 ps
CPU time 17.96 seconds
Started Jan 14 03:01:33 PM PST 24
Finished Jan 14 03:01:51 PM PST 24
Peak memory 255280 kb
Host smart-20f61c05-ec5c-4fd1-a1aa-20efcd32a353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42262
81851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.4226281851
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.853221948
Short name T44
Test name
Test status
Simulation time 416797277 ps
CPU time 9.43 seconds
Started Jan 14 03:01:33 PM PST 24
Finished Jan 14 03:01:43 PM PST 24
Peak memory 248656 kb
Host smart-af38fc6d-d5e1-47bc-bf51-a75d190e8f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85322
1948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.853221948
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1365928305
Short name T312
Test name
Test status
Simulation time 84747096573 ps
CPU time 7975.57 seconds
Started Jan 14 03:01:38 PM PST 24
Finished Jan 14 05:14:35 PM PST 24
Peak memory 355184 kb
Host smart-af5250e7-dee2-45b3-a08b-c0caca055abf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365928305 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1365928305
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3282310794
Short name T523
Test name
Test status
Simulation time 139749190898 ps
CPU time 2171.21 seconds
Started Jan 14 03:01:37 PM PST 24
Finished Jan 14 03:37:49 PM PST 24
Peak memory 285500 kb
Host smart-a6692434-3ad9-4e75-85fc-297c42a895b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282310794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3282310794
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2351405023
Short name T387
Test name
Test status
Simulation time 919907132 ps
CPU time 56.01 seconds
Started Jan 14 03:01:41 PM PST 24
Finished Jan 14 03:02:38 PM PST 24
Peak memory 247872 kb
Host smart-ddb4eae3-1e32-4664-8901-ce86c516978e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23514
05023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2351405023
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2378594033
Short name T728
Test name
Test status
Simulation time 480251408 ps
CPU time 9 seconds
Started Jan 14 03:01:37 PM PST 24
Finished Jan 14 03:01:46 PM PST 24
Peak memory 252148 kb
Host smart-d34a9361-ea52-4ee3-a844-486c3668e427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23785
94033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2378594033
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3427697903
Short name T354
Test name
Test status
Simulation time 11089037097 ps
CPU time 1009.68 seconds
Started Jan 14 03:01:46 PM PST 24
Finished Jan 14 03:18:37 PM PST 24
Peak memory 282976 kb
Host smart-eb52643c-1225-4e20-8663-822c2fd18e06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427697903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3427697903
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2906289975
Short name T306
Test name
Test status
Simulation time 557899891632 ps
CPU time 2556.26 seconds
Started Jan 14 03:01:41 PM PST 24
Finished Jan 14 03:44:18 PM PST 24
Peak memory 288828 kb
Host smart-b57e73e3-0c76-4ec7-8495-b89821b49aaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906289975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2906289975
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2366580537
Short name T330
Test name
Test status
Simulation time 11449666009 ps
CPU time 479.29 seconds
Started Jan 14 03:01:40 PM PST 24
Finished Jan 14 03:09:40 PM PST 24
Peak memory 247540 kb
Host smart-d7360e75-851e-4bdd-866c-2c5c148846b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366580537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2366580537
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2177280611
Short name T33
Test name
Test status
Simulation time 439347817 ps
CPU time 15.01 seconds
Started Jan 14 03:01:39 PM PST 24
Finished Jan 14 03:01:55 PM PST 24
Peak memory 248452 kb
Host smart-ee9f57f5-df23-479c-bfdd-d3d0a4c9e63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21772
80611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2177280611
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3512110927
Short name T438
Test name
Test status
Simulation time 165505124 ps
CPU time 20.55 seconds
Started Jan 14 03:01:46 PM PST 24
Finished Jan 14 03:02:08 PM PST 24
Peak memory 248648 kb
Host smart-73cb8763-3791-4e6b-8a56-b42ebebd3fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35121
10927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3512110927
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3325841267
Short name T681
Test name
Test status
Simulation time 107309846 ps
CPU time 11.21 seconds
Started Jan 14 03:01:41 PM PST 24
Finished Jan 14 03:01:53 PM PST 24
Peak memory 255632 kb
Host smart-68b84812-b164-4532-8141-4ce44469490a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33258
41267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3325841267
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1436565332
Short name T309
Test name
Test status
Simulation time 374218443 ps
CPU time 19.37 seconds
Started Jan 14 03:01:41 PM PST 24
Finished Jan 14 03:02:02 PM PST 24
Peak memory 248608 kb
Host smart-0edb5137-1b67-479c-b303-f90937fc5127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14365
65332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1436565332
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1440985130
Short name T670
Test name
Test status
Simulation time 12363132693 ps
CPU time 1123.05 seconds
Started Jan 14 03:01:53 PM PST 24
Finished Jan 14 03:20:37 PM PST 24
Peak memory 285712 kb
Host smart-497e519c-eede-436b-9aa4-30f3b727b567
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440985130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1440985130
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3842782402
Short name T563
Test name
Test status
Simulation time 136989640160 ps
CPU time 2822.87 seconds
Started Jan 14 03:01:54 PM PST 24
Finished Jan 14 03:48:58 PM PST 24
Peak memory 288872 kb
Host smart-09faf395-68d4-4326-a026-7b2fbd9af827
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842782402 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3842782402
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1445974351
Short name T486
Test name
Test status
Simulation time 22734009431 ps
CPU time 1167.89 seconds
Started Jan 14 03:01:51 PM PST 24
Finished Jan 14 03:21:20 PM PST 24
Peak memory 281548 kb
Host smart-07b0db77-e2e3-4ec2-a2f0-36ea0a6dfbec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445974351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1445974351
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.276950281
Short name T536
Test name
Test status
Simulation time 977916490 ps
CPU time 33.39 seconds
Started Jan 14 03:01:56 PM PST 24
Finished Jan 14 03:02:31 PM PST 24
Peak memory 254908 kb
Host smart-62b1a606-50ef-44b9-8d90-2a3b4aef0d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27695
0281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.276950281
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1788034521
Short name T439
Test name
Test status
Simulation time 249184478 ps
CPU time 16.85 seconds
Started Jan 14 03:01:47 PM PST 24
Finished Jan 14 03:02:04 PM PST 24
Peak memory 252224 kb
Host smart-92f83c33-f4bf-43db-9776-d0835e98f2ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17880
34521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1788034521
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2643206356
Short name T336
Test name
Test status
Simulation time 55390285996 ps
CPU time 493.99 seconds
Started Jan 14 03:01:58 PM PST 24
Finished Jan 14 03:10:13 PM PST 24
Peak memory 247608 kb
Host smart-4874dcae-3e0e-487a-bf58-35b9247cfac6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643206356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2643206356
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1031887442
Short name T514
Test name
Test status
Simulation time 911087913 ps
CPU time 27.66 seconds
Started Jan 14 03:01:48 PM PST 24
Finished Jan 14 03:02:17 PM PST 24
Peak memory 248604 kb
Host smart-7676c706-4ae3-4844-b025-4ef0e69433a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10318
87442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1031887442
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3424932155
Short name T552
Test name
Test status
Simulation time 4041777735 ps
CPU time 56.19 seconds
Started Jan 14 03:01:53 PM PST 24
Finished Jan 14 03:02:50 PM PST 24
Peak memory 247172 kb
Host smart-16d4b2d4-9c86-4474-b740-ae441361635b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34249
32155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3424932155
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.952428274
Short name T461
Test name
Test status
Simulation time 771030035 ps
CPU time 9.06 seconds
Started Jan 14 03:01:50 PM PST 24
Finished Jan 14 03:02:00 PM PST 24
Peak memory 246796 kb
Host smart-e6b567d4-fdf1-4236-9358-eb59c0c55c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95242
8274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.952428274
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1240395952
Short name T716
Test name
Test status
Simulation time 866108576 ps
CPU time 54.97 seconds
Started Jan 14 03:01:46 PM PST 24
Finished Jan 14 03:02:42 PM PST 24
Peak memory 248620 kb
Host smart-eb3814c6-e859-432b-a6ac-cf0fda127d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12403
95952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1240395952
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3825865857
Short name T281
Test name
Test status
Simulation time 54550752822 ps
CPU time 2588.63 seconds
Started Jan 14 03:01:53 PM PST 24
Finished Jan 14 03:45:03 PM PST 24
Peak memory 289604 kb
Host smart-967c17d4-a040-4c5e-8355-0d4a8f1d33c7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825865857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3825865857
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3303073545
Short name T271
Test name
Test status
Simulation time 86922647465 ps
CPU time 5864.35 seconds
Started Jan 14 03:01:52 PM PST 24
Finished Jan 14 04:39:38 PM PST 24
Peak memory 305464 kb
Host smart-ddaddd65-d6de-437e-b397-e1076dea13e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303073545 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3303073545
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2994291575
Short name T562
Test name
Test status
Simulation time 10485283774 ps
CPU time 1034.94 seconds
Started Jan 14 03:02:02 PM PST 24
Finished Jan 14 03:19:18 PM PST 24
Peak memory 272948 kb
Host smart-7dd58495-803f-4013-97c9-d363fba34ab9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994291575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2994291575
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1212811216
Short name T386
Test name
Test status
Simulation time 1240612431 ps
CPU time 57.45 seconds
Started Jan 14 03:02:03 PM PST 24
Finished Jan 14 03:03:01 PM PST 24
Peak memory 248296 kb
Host smart-2df89b2c-0172-40e6-96a6-5b2f681bbc46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12128
11216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1212811216
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3266659381
Short name T85
Test name
Test status
Simulation time 43554237 ps
CPU time 4.39 seconds
Started Jan 14 03:01:57 PM PST 24
Finished Jan 14 03:02:03 PM PST 24
Peak memory 238848 kb
Host smart-e6f30ec1-ba5a-4b34-9495-2729f79c925b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32666
59381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3266659381
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.338517381
Short name T343
Test name
Test status
Simulation time 173396309498 ps
CPU time 1941.23 seconds
Started Jan 14 03:02:10 PM PST 24
Finished Jan 14 03:34:32 PM PST 24
Peak memory 271580 kb
Host smart-d1304224-f477-4ae4-9dce-1e470b212ff5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338517381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.338517381
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1132826655
Short name T490
Test name
Test status
Simulation time 20326041132 ps
CPU time 1456.5 seconds
Started Jan 14 03:02:12 PM PST 24
Finished Jan 14 03:26:30 PM PST 24
Peak memory 273212 kb
Host smart-96ae233b-5dc9-4d52-8378-2dbcd56c46f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132826655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1132826655
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1844863223
Short name T340
Test name
Test status
Simulation time 7329872862 ps
CPU time 311.26 seconds
Started Jan 14 03:02:09 PM PST 24
Finished Jan 14 03:07:21 PM PST 24
Peak memory 247288 kb
Host smart-613334a8-2e0d-45c9-a8e0-da6092038344
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844863223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1844863223
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.407593687
Short name T243
Test name
Test status
Simulation time 308582037 ps
CPU time 27.43 seconds
Started Jan 14 03:01:57 PM PST 24
Finished Jan 14 03:02:26 PM PST 24
Peak memory 248668 kb
Host smart-ebb95fd6-33a8-4e95-be1c-d43f3a7fd6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40759
3687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.407593687
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.623489819
Short name T108
Test name
Test status
Simulation time 881635085 ps
CPU time 31.87 seconds
Started Jan 14 03:01:58 PM PST 24
Finished Jan 14 03:02:31 PM PST 24
Peak memory 247384 kb
Host smart-65a656b5-c046-4476-b3ba-2030ad438356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62348
9819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.623489819
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1767419860
Short name T272
Test name
Test status
Simulation time 567987782 ps
CPU time 18.49 seconds
Started Jan 14 03:02:01 PM PST 24
Finished Jan 14 03:02:21 PM PST 24
Peak memory 255436 kb
Host smart-b8505f29-6f1c-400b-9060-7fae6a114fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17674
19860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1767419860
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.203754757
Short name T458
Test name
Test status
Simulation time 211033463 ps
CPU time 16.49 seconds
Started Jan 14 03:01:57 PM PST 24
Finished Jan 14 03:02:15 PM PST 24
Peak memory 248640 kb
Host smart-a98f0044-c9b2-4731-99ff-f5b6bd01db93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20375
4757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.203754757
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1363166127
Short name T249
Test name
Test status
Simulation time 23950421299 ps
CPU time 1572.2 seconds
Started Jan 14 03:02:10 PM PST 24
Finished Jan 14 03:28:24 PM PST 24
Peak memory 272348 kb
Host smart-d56766ba-ee39-48b5-96e2-0db89716d35f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363166127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1363166127
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.1120753521
Short name T276
Test name
Test status
Simulation time 28092693486 ps
CPU time 1960.8 seconds
Started Jan 14 03:02:11 PM PST 24
Finished Jan 14 03:34:53 PM PST 24
Peak memory 289796 kb
Host smart-a29a229d-88f8-4e99-847a-b2e6159f9ef2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120753521 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.1120753521
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2000518406
Short name T116
Test name
Test status
Simulation time 39116770001 ps
CPU time 1058.99 seconds
Started Jan 14 03:02:15 PM PST 24
Finished Jan 14 03:19:55 PM PST 24
Peak memory 272884 kb
Host smart-7e646b0e-ebea-4227-9db1-5e7f4b18474e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000518406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2000518406
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.241238124
Short name T666
Test name
Test status
Simulation time 3905386544 ps
CPU time 112.78 seconds
Started Jan 14 03:02:11 PM PST 24
Finished Jan 14 03:04:05 PM PST 24
Peak memory 248776 kb
Host smart-974837f2-4fed-481d-974b-3b72e7a86448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24123
8124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.241238124
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.4140928549
Short name T604
Test name
Test status
Simulation time 866880128 ps
CPU time 46.81 seconds
Started Jan 14 03:02:12 PM PST 24
Finished Jan 14 03:02:59 PM PST 24
Peak memory 254528 kb
Host smart-adc89d09-3166-427b-ada3-74dae7b1b7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41409
28549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.4140928549
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.4060042423
Short name T297
Test name
Test status
Simulation time 13491533906 ps
CPU time 1397.09 seconds
Started Jan 14 03:02:14 PM PST 24
Finished Jan 14 03:25:33 PM PST 24
Peak memory 283092 kb
Host smart-8d5ae24b-67c0-4d43-bd40-5a6bb427b607
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060042423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.4060042423
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3957374811
Short name T473
Test name
Test status
Simulation time 23257564763 ps
CPU time 1376.94 seconds
Started Jan 14 03:02:24 PM PST 24
Finished Jan 14 03:25:21 PM PST 24
Peak memory 268172 kb
Host smart-7c68db12-a8ca-4dda-9ff2-8e51131bbb56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957374811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3957374811
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3324103236
Short name T696
Test name
Test status
Simulation time 2715109424 ps
CPU time 116.69 seconds
Started Jan 14 03:02:14 PM PST 24
Finished Jan 14 03:04:12 PM PST 24
Peak memory 246548 kb
Host smart-496dc0c1-c03d-48e8-893b-1cec2cb6d0d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324103236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3324103236
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1627213011
Short name T471
Test name
Test status
Simulation time 219281846 ps
CPU time 5 seconds
Started Jan 14 03:02:10 PM PST 24
Finished Jan 14 03:02:16 PM PST 24
Peak memory 240528 kb
Host smart-024c3495-34b1-4314-9db3-9cb4cbaf0338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16272
13011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1627213011
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1079377020
Short name T472
Test name
Test status
Simulation time 196170198 ps
CPU time 7.05 seconds
Started Jan 14 03:02:15 PM PST 24
Finished Jan 14 03:02:23 PM PST 24
Peak memory 251492 kb
Host smart-1138a0ee-1771-4e04-8356-409dddf1dcd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10793
77020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1079377020
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.4022636877
Short name T555
Test name
Test status
Simulation time 627948212 ps
CPU time 45.47 seconds
Started Jan 14 03:02:11 PM PST 24
Finished Jan 14 03:02:58 PM PST 24
Peak memory 254548 kb
Host smart-bb571ca5-cf8f-4ad6-930c-2fa102921cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40226
36877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.4022636877
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2067793000
Short name T464
Test name
Test status
Simulation time 3711945792 ps
CPU time 73.58 seconds
Started Jan 14 03:02:09 PM PST 24
Finished Jan 14 03:03:23 PM PST 24
Peak memory 248668 kb
Host smart-25d713a8-d77f-4585-bfc0-287bb52c9aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20677
93000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2067793000
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1959741854
Short name T37
Test name
Test status
Simulation time 152611064400 ps
CPU time 2191.58 seconds
Started Jan 14 03:02:22 PM PST 24
Finished Jan 14 03:38:55 PM PST 24
Peak memory 297864 kb
Host smart-13bb381e-08e5-4a7b-b1b0-54c21af2a2c0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959741854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1959741854
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.602027873
Short name T643
Test name
Test status
Simulation time 172962921325 ps
CPU time 3097.6 seconds
Started Jan 14 03:02:16 PM PST 24
Finished Jan 14 03:53:55 PM PST 24
Peak memory 289848 kb
Host smart-31a68168-3e13-4839-bb7c-15175ccd1724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602027873 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.602027873
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1879070082
Short name T639
Test name
Test status
Simulation time 36828566717 ps
CPU time 1326.42 seconds
Started Jan 14 03:02:40 PM PST 24
Finished Jan 14 03:24:47 PM PST 24
Peak memory 289500 kb
Host smart-3b0647ad-1cfd-42aa-ae0a-2d5926e8b2fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879070082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1879070082
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1962519449
Short name T136
Test name
Test status
Simulation time 800520431 ps
CPU time 45.22 seconds
Started Jan 14 03:02:44 PM PST 24
Finished Jan 14 03:03:30 PM PST 24
Peak memory 255896 kb
Host smart-2dc88b40-42f7-43a7-8770-c68dd6ea0fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19625
19449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1962519449
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3627252899
Short name T688
Test name
Test status
Simulation time 740078077 ps
CPU time 31.34 seconds
Started Jan 14 03:02:41 PM PST 24
Finished Jan 14 03:03:14 PM PST 24
Peak memory 255116 kb
Host smart-a5917c86-c020-4e05-98ef-251111818e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36272
52899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3627252899
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1099675610
Short name T368
Test name
Test status
Simulation time 104821046021 ps
CPU time 3094.76 seconds
Started Jan 14 03:02:45 PM PST 24
Finished Jan 14 03:54:21 PM PST 24
Peak memory 289556 kb
Host smart-0dcd75cf-080c-4f19-8d95-a1f4d07bc345
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099675610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1099675610
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1411895218
Short name T451
Test name
Test status
Simulation time 13964981418 ps
CPU time 1639.23 seconds
Started Jan 14 03:02:35 PM PST 24
Finished Jan 14 03:29:55 PM PST 24
Peak memory 289008 kb
Host smart-a355aea0-6ac5-4048-bb32-f5ffafd9da43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411895218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1411895218
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1917797123
Short name T511
Test name
Test status
Simulation time 12679406496 ps
CPU time 147.47 seconds
Started Jan 14 03:02:35 PM PST 24
Finished Jan 14 03:05:03 PM PST 24
Peak memory 247604 kb
Host smart-e7f617ed-e1ed-4ce6-9596-2b7f0593f8b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917797123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1917797123
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1124529654
Short name T395
Test name
Test status
Simulation time 1145804882 ps
CPU time 60.42 seconds
Started Jan 14 03:02:14 PM PST 24
Finished Jan 14 03:03:16 PM PST 24
Peak memory 248640 kb
Host smart-646a0adc-a28e-4c1d-8b77-fd70d1bb922a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11245
29654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1124529654
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2047574276
Short name T424
Test name
Test status
Simulation time 1311482999 ps
CPU time 29.19 seconds
Started Jan 14 03:02:23 PM PST 24
Finished Jan 14 03:02:52 PM PST 24
Peak memory 256360 kb
Host smart-1bcf1877-ae24-4649-b0d4-4cfd91e308a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20475
74276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2047574276
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.876550261
Short name T713
Test name
Test status
Simulation time 993901371 ps
CPU time 62.33 seconds
Started Jan 14 03:02:31 PM PST 24
Finished Jan 14 03:03:34 PM PST 24
Peak memory 255556 kb
Host smart-965cd648-85d5-4f98-a4b2-0ee93e27151f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87655
0261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.876550261
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3948722093
Short name T73
Test name
Test status
Simulation time 1109011629 ps
CPU time 19.35 seconds
Started Jan 14 03:02:24 PM PST 24
Finished Jan 14 03:02:44 PM PST 24
Peak memory 248624 kb
Host smart-65530572-b02f-4318-9674-379085b9e596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39487
22093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3948722093
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1235290097
Short name T131
Test name
Test status
Simulation time 105370765705 ps
CPU time 1806.01 seconds
Started Jan 14 03:02:41 PM PST 24
Finished Jan 14 03:32:49 PM PST 24
Peak memory 272880 kb
Host smart-0ff1eb4e-d6d8-4230-9f21-6546d2d5ae03
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235290097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1235290097
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.817599729
Short name T240
Test name
Test status
Simulation time 95481294429 ps
CPU time 6512.21 seconds
Started Jan 14 03:02:34 PM PST 24
Finished Jan 14 04:51:08 PM PST 24
Peak memory 367500 kb
Host smart-899ac6ff-e228-4b2f-84d9-349db7267be0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817599729 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.817599729
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.796205336
Short name T239
Test name
Test status
Simulation time 107990462 ps
CPU time 3.37 seconds
Started Jan 14 02:59:07 PM PST 24
Finished Jan 14 02:59:11 PM PST 24
Peak memory 248832 kb
Host smart-938f7fea-7cdf-4c96-bc3f-5de2c9d183ae
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=796205336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.796205336
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2867384306
Short name T631
Test name
Test status
Simulation time 15414003407 ps
CPU time 1455.95 seconds
Started Jan 14 02:59:04 PM PST 24
Finished Jan 14 03:23:21 PM PST 24
Peak memory 284588 kb
Host smart-8fe17860-9985-4c58-bfb5-40c82254f58c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867384306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2867384306
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1782751145
Short name T572
Test name
Test status
Simulation time 180716174 ps
CPU time 11.19 seconds
Started Jan 14 02:59:06 PM PST 24
Finished Jan 14 02:59:18 PM PST 24
Peak memory 240540 kb
Host smart-ce9e6c94-5a1b-4537-89b4-2e3994bd1b9b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1782751145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1782751145
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1480295509
Short name T642
Test name
Test status
Simulation time 636053063 ps
CPU time 16.88 seconds
Started Jan 14 02:59:07 PM PST 24
Finished Jan 14 02:59:25 PM PST 24
Peak memory 248152 kb
Host smart-84b3f9ac-f159-4e5a-85a3-afa34cef9553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14802
95509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1480295509
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1316267735
Short name T657
Test name
Test status
Simulation time 1564460416 ps
CPU time 25.45 seconds
Started Jan 14 02:59:01 PM PST 24
Finished Jan 14 02:59:27 PM PST 24
Peak memory 248812 kb
Host smart-066c9fa3-551b-4140-bf84-7d2905726d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13162
67735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1316267735
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1871799392
Short name T370
Test name
Test status
Simulation time 136596158998 ps
CPU time 2773.78 seconds
Started Jan 14 02:59:06 PM PST 24
Finished Jan 14 03:45:21 PM PST 24
Peak memory 288600 kb
Host smart-0bc1f916-4558-4a7a-90b0-0e42badde499
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871799392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1871799392
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.901392982
Short name T530
Test name
Test status
Simulation time 43356275274 ps
CPU time 2907.45 seconds
Started Jan 14 02:59:03 PM PST 24
Finished Jan 14 03:47:31 PM PST 24
Peak memory 288424 kb
Host smart-5d438f1c-e700-4126-ba98-c6efa7b93620
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901392982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.901392982
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3968230002
Short name T542
Test name
Test status
Simulation time 4054556685 ps
CPU time 167.32 seconds
Started Jan 14 02:59:07 PM PST 24
Finished Jan 14 03:01:55 PM PST 24
Peak memory 247524 kb
Host smart-729608d1-684c-4085-9ecf-31d0ce3d511f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968230002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3968230002
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3928901306
Short name T421
Test name
Test status
Simulation time 670892783 ps
CPU time 38.95 seconds
Started Jan 14 02:58:57 PM PST 24
Finished Jan 14 02:59:38 PM PST 24
Peak memory 248696 kb
Host smart-4c175b1b-2802-4644-9f70-ae444034aced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39289
01306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3928901306
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3751606642
Short name T477
Test name
Test status
Simulation time 1740113011 ps
CPU time 41.33 seconds
Started Jan 14 02:59:03 PM PST 24
Finished Jan 14 02:59:46 PM PST 24
Peak memory 255068 kb
Host smart-39ecada1-109c-4716-942d-86ffe5a2c9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37516
06642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3751606642
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.819380659
Short name T45
Test name
Test status
Simulation time 3339480332 ps
CPU time 26.75 seconds
Started Jan 14 02:59:02 PM PST 24
Finished Jan 14 02:59:30 PM PST 24
Peak memory 276584 kb
Host smart-4976c906-17c8-4e37-a362-724572c83724
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=819380659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.819380659
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1080336115
Short name T269
Test name
Test status
Simulation time 1080234367 ps
CPU time 67.01 seconds
Started Jan 14 02:59:02 PM PST 24
Finished Jan 14 03:00:10 PM PST 24
Peak memory 254856 kb
Host smart-c07b1332-8bf4-47dc-8e3c-68a99c0b9df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10803
36115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1080336115
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2251729829
Short name T567
Test name
Test status
Simulation time 1815371202 ps
CPU time 8.14 seconds
Started Jan 14 02:58:56 PM PST 24
Finished Jan 14 02:59:06 PM PST 24
Peak memory 248832 kb
Host smart-d05ea9fb-8709-4524-b245-a3474defa1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22517
29829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2251729829
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3720445851
Short name T725
Test name
Test status
Simulation time 621698083314 ps
CPU time 1936.58 seconds
Started Jan 14 02:59:04 PM PST 24
Finished Jan 14 03:31:22 PM PST 24
Peak memory 284732 kb
Host smart-bf65778d-3d9e-4092-95b4-481dce1dd37d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720445851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3720445851
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2617277822
Short name T526
Test name
Test status
Simulation time 14478754569 ps
CPU time 1194.61 seconds
Started Jan 14 02:59:03 PM PST 24
Finished Jan 14 03:18:58 PM PST 24
Peak memory 282260 kb
Host smart-edf8616b-4c10-4999-9fa1-09957c25003e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617277822 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2617277822
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.266539427
Short name T88
Test name
Test status
Simulation time 12357933952 ps
CPU time 1201.55 seconds
Started Jan 14 03:02:41 PM PST 24
Finished Jan 14 03:22:44 PM PST 24
Peak memory 272824 kb
Host smart-4d071a64-e462-4c70-9f01-0544b04119ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266539427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.266539427
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3716276240
Short name T533
Test name
Test status
Simulation time 23077580741 ps
CPU time 157.12 seconds
Started Jan 14 03:02:35 PM PST 24
Finished Jan 14 03:05:12 PM PST 24
Peak memory 255896 kb
Host smart-a60455e0-5729-4e7f-ac41-d0d7030daf27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37162
76240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3716276240
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2847985326
Short name T512
Test name
Test status
Simulation time 175669215 ps
CPU time 21.58 seconds
Started Jan 14 03:02:47 PM PST 24
Finished Jan 14 03:03:09 PM PST 24
Peak memory 255148 kb
Host smart-817dcd33-2888-46bd-a00f-1efee57327e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28479
85326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2847985326
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.133290254
Short name T353
Test name
Test status
Simulation time 33788542477 ps
CPU time 2370.34 seconds
Started Jan 14 03:02:46 PM PST 24
Finished Jan 14 03:42:17 PM PST 24
Peak memory 284340 kb
Host smart-fcc9b261-af7d-4a5b-a9c2-2161fd3f6d73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133290254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.133290254
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.608973741
Short name T656
Test name
Test status
Simulation time 40437815653 ps
CPU time 1217.23 seconds
Started Jan 14 03:02:45 PM PST 24
Finished Jan 14 03:23:03 PM PST 24
Peak memory 273428 kb
Host smart-2d54e597-e717-4809-813b-685c492930a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608973741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.608973741
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2571179523
Short name T389
Test name
Test status
Simulation time 369288516 ps
CPU time 12.55 seconds
Started Jan 14 03:02:40 PM PST 24
Finished Jan 14 03:02:54 PM PST 24
Peak memory 256788 kb
Host smart-b40d185c-1969-44c7-ba0a-2759330a6342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25711
79523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2571179523
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.451631193
Short name T103
Test name
Test status
Simulation time 842471456 ps
CPU time 46.63 seconds
Started Jan 14 03:02:40 PM PST 24
Finished Jan 14 03:03:27 PM PST 24
Peak memory 248204 kb
Host smart-e89c40b2-628c-4055-89b1-dabab7533743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45163
1193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.451631193
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2515190953
Short name T275
Test name
Test status
Simulation time 585326548 ps
CPU time 20.42 seconds
Started Jan 14 03:02:43 PM PST 24
Finished Jan 14 03:03:04 PM PST 24
Peak memory 254332 kb
Host smart-497b279e-f377-4e15-8577-8da79b66cea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25151
90953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2515190953
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2000027748
Short name T460
Test name
Test status
Simulation time 194703247 ps
CPU time 14.53 seconds
Started Jan 14 03:02:36 PM PST 24
Finished Jan 14 03:02:51 PM PST 24
Peak memory 248660 kb
Host smart-de555739-65d2-4ab5-9652-02a2faf03440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20000
27748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2000027748
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.506055912
Short name T119
Test name
Test status
Simulation time 63390141623 ps
CPU time 2096.34 seconds
Started Jan 14 03:02:40 PM PST 24
Finished Jan 14 03:37:37 PM PST 24
Peak memory 289536 kb
Host smart-8b9c5e7a-b232-4ce4-9bf6-1f84777401e8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506055912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.506055912
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2642544126
Short name T95
Test name
Test status
Simulation time 50711633910 ps
CPU time 885.77 seconds
Started Jan 14 03:02:42 PM PST 24
Finished Jan 14 03:17:29 PM PST 24
Peak memory 270616 kb
Host smart-7b8d1674-27d6-4e7e-bfd2-54381ee10bf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642544126 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2642544126
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1073163452
Short name T57
Test name
Test status
Simulation time 106115543043 ps
CPU time 1549.65 seconds
Started Jan 14 03:02:42 PM PST 24
Finished Jan 14 03:28:33 PM PST 24
Peak memory 265092 kb
Host smart-4daddd57-c0fe-41d8-9da2-81e835093c61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073163452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1073163452
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.339085462
Short name T257
Test name
Test status
Simulation time 1226432308 ps
CPU time 76.19 seconds
Started Jan 14 03:02:44 PM PST 24
Finished Jan 14 03:04:00 PM PST 24
Peak memory 248212 kb
Host smart-ea14c86b-3b1f-43de-89ad-619e31499b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33908
5462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.339085462
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1489820197
Short name T605
Test name
Test status
Simulation time 678094281 ps
CPU time 20.83 seconds
Started Jan 14 03:02:42 PM PST 24
Finished Jan 14 03:03:04 PM PST 24
Peak memory 254796 kb
Host smart-f8872dd1-e93d-475e-b8f3-1a959bb2c0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14898
20197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1489820197
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2521402331
Short name T69
Test name
Test status
Simulation time 15948964779 ps
CPU time 804.32 seconds
Started Jan 14 03:02:45 PM PST 24
Finished Jan 14 03:16:10 PM PST 24
Peak memory 272556 kb
Host smart-f71d3b70-cbc0-45a2-b3d8-9ad8b80e386c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521402331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2521402331
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.87720607
Short name T112
Test name
Test status
Simulation time 11851512826 ps
CPU time 671.08 seconds
Started Jan 14 03:02:50 PM PST 24
Finished Jan 14 03:14:02 PM PST 24
Peak memory 272508 kb
Host smart-3af754c1-741f-42eb-962f-7d20256a1f26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87720607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.87720607
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2279854972
Short name T326
Test name
Test status
Simulation time 41790404278 ps
CPU time 447.58 seconds
Started Jan 14 03:02:45 PM PST 24
Finished Jan 14 03:10:13 PM PST 24
Peak memory 247300 kb
Host smart-1cce1e33-9839-4d42-a0de-26d21e5db901
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279854972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2279854972
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.561937126
Short name T561
Test name
Test status
Simulation time 1050835606 ps
CPU time 38.59 seconds
Started Jan 14 03:02:45 PM PST 24
Finished Jan 14 03:03:25 PM PST 24
Peak memory 255484 kb
Host smart-7e70e9d9-8362-4f53-804b-6cc37e50c41d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56193
7126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.561937126
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1177958713
Short name T141
Test name
Test status
Simulation time 1233778074 ps
CPU time 39.88 seconds
Started Jan 14 03:02:45 PM PST 24
Finished Jan 14 03:03:26 PM PST 24
Peak memory 248168 kb
Host smart-7f46eef3-ef8e-4d05-ad4d-d0c235457233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11779
58713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1177958713
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.808280876
Short name T274
Test name
Test status
Simulation time 555353907 ps
CPU time 47.39 seconds
Started Jan 14 03:02:46 PM PST 24
Finished Jan 14 03:03:34 PM PST 24
Peak memory 254884 kb
Host smart-d9e2e8aa-f042-4160-89b8-f9d4df28d481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80828
0876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.808280876
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1593751076
Short name T663
Test name
Test status
Simulation time 5800151386 ps
CPU time 56.21 seconds
Started Jan 14 03:02:41 PM PST 24
Finished Jan 14 03:03:39 PM PST 24
Peak memory 255740 kb
Host smart-b78ddfa1-71f5-4391-84b9-af4afee0bdc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15937
51076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1593751076
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3155449532
Short name T577
Test name
Test status
Simulation time 22866627413 ps
CPU time 1356.36 seconds
Started Jan 14 03:02:48 PM PST 24
Finished Jan 14 03:25:25 PM PST 24
Peak memory 289232 kb
Host smart-84e5119c-f221-48e7-960f-36f16263c1b3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155449532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3155449532
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4049515523
Short name T111
Test name
Test status
Simulation time 23959655104 ps
CPU time 1492.76 seconds
Started Jan 14 03:02:50 PM PST 24
Finished Jan 14 03:27:43 PM PST 24
Peak memory 288792 kb
Host smart-e0d195f6-d836-4dcb-89fb-c5dfc6e802fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049515523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4049515523
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2630268997
Short name T493
Test name
Test status
Simulation time 9786688259 ps
CPU time 151.17 seconds
Started Jan 14 03:02:52 PM PST 24
Finished Jan 14 03:05:24 PM PST 24
Peak memory 256912 kb
Host smart-80901bf3-adf7-4e68-8294-e5eecdd20253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26302
68997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2630268997
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1977234914
Short name T564
Test name
Test status
Simulation time 139134410 ps
CPU time 3.69 seconds
Started Jan 14 03:02:51 PM PST 24
Finished Jan 14 03:02:55 PM PST 24
Peak memory 250484 kb
Host smart-dd059d84-4847-4221-911a-a16261ce08d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19772
34914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1977234914
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2450390013
Short name T352
Test name
Test status
Simulation time 530044391259 ps
CPU time 2875.33 seconds
Started Jan 14 03:02:51 PM PST 24
Finished Jan 14 03:50:48 PM PST 24
Peak memory 289036 kb
Host smart-0abdf5e6-d98e-4d1f-8c41-b765e219f688
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450390013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2450390013
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3510406553
Short name T606
Test name
Test status
Simulation time 101433375825 ps
CPU time 3443.07 seconds
Started Jan 14 03:02:49 PM PST 24
Finished Jan 14 04:00:13 PM PST 24
Peak memory 289100 kb
Host smart-975e3aa2-f98d-42d5-a3f8-63bd0edaaa6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510406553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3510406553
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1944577290
Short name T617
Test name
Test status
Simulation time 7373385084 ps
CPU time 309.91 seconds
Started Jan 14 03:02:52 PM PST 24
Finished Jan 14 03:08:03 PM PST 24
Peak memory 247540 kb
Host smart-4c68d930-3d99-4aa5-bc9d-91de76ccad49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944577290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1944577290
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.476117004
Short name T481
Test name
Test status
Simulation time 219465089 ps
CPU time 29.27 seconds
Started Jan 14 03:02:50 PM PST 24
Finished Jan 14 03:03:20 PM PST 24
Peak memory 255016 kb
Host smart-db3bd08c-687a-4305-ac68-21b2b9999717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47611
7004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.476117004
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2521589675
Short name T488
Test name
Test status
Simulation time 2577221929 ps
CPU time 40.41 seconds
Started Jan 14 03:02:51 PM PST 24
Finished Jan 14 03:03:32 PM PST 24
Peak memory 248688 kb
Host smart-c4addf8f-fcd4-472e-903e-1160c4cb1e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25215
89675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2521589675
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3034669507
Short name T1
Test name
Test status
Simulation time 1225858518 ps
CPU time 19.82 seconds
Started Jan 14 03:02:47 PM PST 24
Finished Jan 14 03:03:07 PM PST 24
Peak memory 254172 kb
Host smart-92c07d6c-d9a4-43c3-be76-8fe2df5315a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30346
69507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3034669507
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.665465570
Short name T727
Test name
Test status
Simulation time 639592978 ps
CPU time 15.47 seconds
Started Jan 14 03:02:47 PM PST 24
Finished Jan 14 03:03:03 PM PST 24
Peak memory 253588 kb
Host smart-59d0cedf-9809-4e68-8170-ff395604e981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66546
5570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.665465570
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3555392687
Short name T714
Test name
Test status
Simulation time 14538168536 ps
CPU time 1744.4 seconds
Started Jan 14 03:02:47 PM PST 24
Finished Jan 14 03:31:52 PM PST 24
Peak memory 289736 kb
Host smart-6b9f65f3-62d3-4b1b-a8c0-d2d8ed6c1e56
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555392687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3555392687
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3693322842
Short name T120
Test name
Test status
Simulation time 260679924449 ps
CPU time 7085.49 seconds
Started Jan 14 03:02:51 PM PST 24
Finished Jan 14 05:00:58 PM PST 24
Peak memory 354440 kb
Host smart-3a42acb0-2980-4618-93bb-bca4ed7f34f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693322842 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3693322842
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1077217932
Short name T305
Test name
Test status
Simulation time 111362676823 ps
CPU time 1787.91 seconds
Started Jan 14 03:02:53 PM PST 24
Finished Jan 14 03:32:42 PM PST 24
Peak memory 272420 kb
Host smart-ab8987a4-300d-4aea-87cb-4f746c777aef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077217932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1077217932
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.4080110227
Short name T616
Test name
Test status
Simulation time 12543348719 ps
CPU time 248.75 seconds
Started Jan 14 03:02:55 PM PST 24
Finished Jan 14 03:07:05 PM PST 24
Peak memory 255812 kb
Host smart-a125143e-6119-4630-9185-ea62d6a06ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40801
10227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.4080110227
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2483972284
Short name T452
Test name
Test status
Simulation time 1658428793 ps
CPU time 56.96 seconds
Started Jan 14 03:02:54 PM PST 24
Finished Jan 14 03:03:52 PM PST 24
Peak memory 256136 kb
Host smart-d8fda156-aac9-47a5-b8ca-b7e4994a6fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24839
72284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2483972284
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2143451286
Short name T335
Test name
Test status
Simulation time 12237208336 ps
CPU time 1001.27 seconds
Started Jan 14 03:03:06 PM PST 24
Finished Jan 14 03:19:47 PM PST 24
Peak memory 268208 kb
Host smart-b2d0b38c-133d-4a94-a736-33d206c2c014
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143451286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2143451286
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1711687395
Short name T509
Test name
Test status
Simulation time 37058689999 ps
CPU time 985.6 seconds
Started Jan 14 03:03:06 PM PST 24
Finished Jan 14 03:19:32 PM PST 24
Peak memory 273380 kb
Host smart-498ac304-7e2d-49ca-a135-aae11e4f86d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711687395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1711687395
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1360698058
Short name T320
Test name
Test status
Simulation time 6780326297 ps
CPU time 149.36 seconds
Started Jan 14 03:02:53 PM PST 24
Finished Jan 14 03:05:23 PM PST 24
Peak memory 247672 kb
Host smart-603ebd68-3765-4f90-a922-73cd9f1a4038
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360698058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1360698058
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3069170921
Short name T58
Test name
Test status
Simulation time 2914069097 ps
CPU time 46.53 seconds
Started Jan 14 03:02:53 PM PST 24
Finished Jan 14 03:03:40 PM PST 24
Peak memory 248768 kb
Host smart-880d1c25-a7a2-4b94-a20f-01808131e4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30691
70921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3069170921
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1554155337
Short name T65
Test name
Test status
Simulation time 478096287 ps
CPU time 35.83 seconds
Started Jan 14 03:02:55 PM PST 24
Finished Jan 14 03:03:32 PM PST 24
Peak memory 254952 kb
Host smart-25f935c1-9ecd-4ca7-a882-43b29c207e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15541
55337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1554155337
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.407746097
Short name T263
Test name
Test status
Simulation time 188691239 ps
CPU time 11.84 seconds
Started Jan 14 03:02:55 PM PST 24
Finished Jan 14 03:03:07 PM PST 24
Peak memory 253704 kb
Host smart-1aa3f4b6-dc5d-45a5-8cb7-6ba4f0b83bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40774
6097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.407746097
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2634321603
Short name T410
Test name
Test status
Simulation time 745657779 ps
CPU time 48.48 seconds
Started Jan 14 03:02:52 PM PST 24
Finished Jan 14 03:03:41 PM PST 24
Peak memory 248760 kb
Host smart-1dd77b2c-6208-4956-be3a-5cdd6010363b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26343
21603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2634321603
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2468047383
Short name T130
Test name
Test status
Simulation time 96183932834 ps
CPU time 2100.79 seconds
Started Jan 14 03:03:06 PM PST 24
Finished Jan 14 03:38:07 PM PST 24
Peak memory 304844 kb
Host smart-4ada5905-9639-48d3-9919-9410f1b302ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468047383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2468047383
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.806460019
Short name T591
Test name
Test status
Simulation time 8623068659 ps
CPU time 640.52 seconds
Started Jan 14 03:03:12 PM PST 24
Finished Jan 14 03:13:53 PM PST 24
Peak memory 265112 kb
Host smart-98d2d61e-5b8c-4c7f-9f08-1d8ebb656954
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806460019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.806460019
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.4193239734
Short name T588
Test name
Test status
Simulation time 13516698333 ps
CPU time 97.99 seconds
Started Jan 14 03:03:16 PM PST 24
Finished Jan 14 03:04:55 PM PST 24
Peak memory 255960 kb
Host smart-d97309fc-b89f-4d7a-8625-604e4874624c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41932
39734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.4193239734
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.381034139
Short name T556
Test name
Test status
Simulation time 711536206 ps
CPU time 42.44 seconds
Started Jan 14 03:03:11 PM PST 24
Finished Jan 14 03:03:54 PM PST 24
Peak memory 254380 kb
Host smart-ea86b5bb-0a0a-4b2f-9f30-c62a8f5e17af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38103
4139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.381034139
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1170944823
Short name T365
Test name
Test status
Simulation time 67106145987 ps
CPU time 1282.04 seconds
Started Jan 14 03:03:10 PM PST 24
Finished Jan 14 03:24:33 PM PST 24
Peak memory 283020 kb
Host smart-37531f4a-7706-4c73-bd34-4e67a87fa79a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170944823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1170944823
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3357679389
Short name T323
Test name
Test status
Simulation time 57876442358 ps
CPU time 599.18 seconds
Started Jan 14 03:03:13 PM PST 24
Finished Jan 14 03:13:13 PM PST 24
Peak memory 247300 kb
Host smart-e4c88ecd-a948-444c-9bb6-aec96f14b112
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357679389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3357679389
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.294555966
Short name T422
Test name
Test status
Simulation time 185344207 ps
CPU time 10.99 seconds
Started Jan 14 03:03:05 PM PST 24
Finished Jan 14 03:03:16 PM PST 24
Peak memory 248720 kb
Host smart-e15a9fd2-e79c-46b4-ab69-fef52cba0d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29455
5966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.294555966
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1246722651
Short name T396
Test name
Test status
Simulation time 87497835 ps
CPU time 7.02 seconds
Started Jan 14 03:03:07 PM PST 24
Finished Jan 14 03:03:15 PM PST 24
Peak memory 249308 kb
Host smart-dfa901f3-d9b1-40e7-8ead-2f713344a212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12467
22651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1246722651
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3244866247
Short name T463
Test name
Test status
Simulation time 1453513809 ps
CPU time 28.34 seconds
Started Jan 14 03:03:12 PM PST 24
Finished Jan 14 03:03:41 PM PST 24
Peak memory 248628 kb
Host smart-1c416778-1f55-4f35-83a8-b32cd2467619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32448
66247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3244866247
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1548010744
Short name T379
Test name
Test status
Simulation time 410785578 ps
CPU time 23.68 seconds
Started Jan 14 03:03:06 PM PST 24
Finished Jan 14 03:03:31 PM PST 24
Peak memory 255660 kb
Host smart-a91294ae-0a52-4e56-b649-0a3c9a911a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15480
10744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1548010744
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1184482445
Short name T279
Test name
Test status
Simulation time 94864539218 ps
CPU time 2941.94 seconds
Started Jan 14 03:03:15 PM PST 24
Finished Jan 14 03:52:19 PM PST 24
Peak memory 289636 kb
Host smart-36847d1a-1dba-49a2-8707-06e3adcded61
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184482445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1184482445
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1583862021
Short name T417
Test name
Test status
Simulation time 59017766481 ps
CPU time 3772.98 seconds
Started Jan 14 03:03:16 PM PST 24
Finished Jan 14 04:06:11 PM PST 24
Peak memory 289784 kb
Host smart-c9405398-0bf7-4b2d-81b5-a574beaad065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583862021 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1583862021
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.206921690
Short name T499
Test name
Test status
Simulation time 74451193273 ps
CPU time 2332.4 seconds
Started Jan 14 03:03:20 PM PST 24
Finished Jan 14 03:42:14 PM PST 24
Peak memory 285200 kb
Host smart-e044dbe9-b8dd-40a2-9337-db5687bdad5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206921690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.206921690
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2311979109
Short name T683
Test name
Test status
Simulation time 3940030947 ps
CPU time 212.65 seconds
Started Jan 14 03:03:21 PM PST 24
Finished Jan 14 03:06:55 PM PST 24
Peak memory 250812 kb
Host smart-38f63094-2903-4df2-b4fb-460268d53fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23119
79109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2311979109
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3714979758
Short name T246
Test name
Test status
Simulation time 202807228883 ps
CPU time 2579.29 seconds
Started Jan 14 03:03:31 PM PST 24
Finished Jan 14 03:46:32 PM PST 24
Peak memory 288516 kb
Host smart-591c3e58-6121-435a-9e7c-8d441e7a20f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714979758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3714979758
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3537599002
Short name T634
Test name
Test status
Simulation time 127233521164 ps
CPU time 1042.81 seconds
Started Jan 14 03:03:31 PM PST 24
Finished Jan 14 03:20:55 PM PST 24
Peak memory 267108 kb
Host smart-1e435f76-295d-45b7-93da-c50176ff78e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537599002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3537599002
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1509521257
Short name T318
Test name
Test status
Simulation time 21008964433 ps
CPU time 238.57 seconds
Started Jan 14 03:03:32 PM PST 24
Finished Jan 14 03:07:32 PM PST 24
Peak memory 247296 kb
Host smart-6a0971bb-6458-4972-b216-cf6c1c26f922
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509521257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1509521257
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3505324228
Short name T431
Test name
Test status
Simulation time 558010516 ps
CPU time 27.08 seconds
Started Jan 14 03:03:20 PM PST 24
Finished Jan 14 03:03:48 PM PST 24
Peak memory 248668 kb
Host smart-67525308-0108-4486-8b93-de44c97a9a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35053
24228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3505324228
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2745954068
Short name T87
Test name
Test status
Simulation time 1263503393 ps
CPU time 77.29 seconds
Started Jan 14 03:03:20 PM PST 24
Finished Jan 14 03:04:39 PM PST 24
Peak memory 254872 kb
Host smart-35cfdf11-95aa-4e37-ab20-1d1f44124fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27459
54068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2745954068
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1311791197
Short name T304
Test name
Test status
Simulation time 1815795094 ps
CPU time 49.55 seconds
Started Jan 14 03:03:21 PM PST 24
Finished Jan 14 03:04:12 PM PST 24
Peak memory 255128 kb
Host smart-bf89f778-4616-4455-8429-35a813d0a1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13117
91197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1311791197
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3633760224
Short name T466
Test name
Test status
Simulation time 168744899 ps
CPU time 4.99 seconds
Started Jan 14 03:03:20 PM PST 24
Finished Jan 14 03:03:26 PM PST 24
Peak memory 240480 kb
Host smart-c22aa336-dd8a-449a-8d8f-1e1527b1eed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36337
60224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3633760224
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2511730306
Short name T252
Test name
Test status
Simulation time 34721166577 ps
CPU time 1271.4 seconds
Started Jan 14 03:03:27 PM PST 24
Finished Jan 14 03:24:43 PM PST 24
Peak memory 272980 kb
Host smart-9ea93309-1f56-43ac-ae99-847ffdad9beb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511730306 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2511730306
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1777203481
Short name T669
Test name
Test status
Simulation time 41193438714 ps
CPU time 2806.05 seconds
Started Jan 14 03:03:46 PM PST 24
Finished Jan 14 03:50:34 PM PST 24
Peak memory 288644 kb
Host smart-1fb46d8c-920c-4487-b7f9-d147caa0c27c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777203481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1777203481
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1122677573
Short name T260
Test name
Test status
Simulation time 545063002 ps
CPU time 44.89 seconds
Started Jan 14 03:03:35 PM PST 24
Finished Jan 14 03:04:21 PM PST 24
Peak memory 256168 kb
Host smart-839e03c6-8619-4f01-959b-6b1598f69aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11226
77573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1122677573
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2375643116
Short name T549
Test name
Test status
Simulation time 888226812 ps
CPU time 20.14 seconds
Started Jan 14 03:03:36 PM PST 24
Finished Jan 14 03:03:57 PM PST 24
Peak memory 247012 kb
Host smart-65ed1e70-5bbb-4b5b-9f23-eb693616b251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23756
43116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2375643116
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2949650965
Short name T446
Test name
Test status
Simulation time 23916623597 ps
CPU time 1235.7 seconds
Started Jan 14 03:03:47 PM PST 24
Finished Jan 14 03:24:25 PM PST 24
Peak memory 284064 kb
Host smart-ad24c1ac-1297-4ea5-8751-515365846fe0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949650965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2949650965
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1045192973
Short name T637
Test name
Test status
Simulation time 410956456820 ps
CPU time 2252.81 seconds
Started Jan 14 03:03:51 PM PST 24
Finished Jan 14 03:41:28 PM PST 24
Peak memory 281840 kb
Host smart-b1edaa73-72ac-448d-9240-e6e2582a0274
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045192973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1045192973
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.853650279
Short name T649
Test name
Test status
Simulation time 10211809243 ps
CPU time 221.65 seconds
Started Jan 14 03:03:47 PM PST 24
Finished Jan 14 03:07:30 PM PST 24
Peak memory 247460 kb
Host smart-a0fc8b26-168c-4243-a32f-452a1308456b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853650279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.853650279
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3061302726
Short name T19
Test name
Test status
Simulation time 2674672646 ps
CPU time 38.35 seconds
Started Jan 14 03:03:27 PM PST 24
Finished Jan 14 03:04:10 PM PST 24
Peak memory 255408 kb
Host smart-bca27d74-333e-4d08-898b-c35cc4742d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30613
02726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3061302726
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3970178420
Short name T579
Test name
Test status
Simulation time 6433481710 ps
CPU time 21.95 seconds
Started Jan 14 03:03:28 PM PST 24
Finished Jan 14 03:03:54 PM PST 24
Peak memory 253844 kb
Host smart-f5f3bb20-df03-4dbf-98a6-620752041867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39701
78420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3970178420
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.206036615
Short name T570
Test name
Test status
Simulation time 376925981 ps
CPU time 8.29 seconds
Started Jan 14 03:03:36 PM PST 24
Finished Jan 14 03:03:46 PM PST 24
Peak memory 240520 kb
Host smart-af44e19b-16fb-4b81-9c81-6416110fce6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20603
6615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.206036615
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.933568160
Short name T525
Test name
Test status
Simulation time 3311506539 ps
CPU time 46.59 seconds
Started Jan 14 03:03:32 PM PST 24
Finished Jan 14 03:04:20 PM PST 24
Peak memory 248768 kb
Host smart-bd311485-6bda-420a-94ad-cc65ee8a6029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93356
8160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.933568160
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2180341879
Short name T118
Test name
Test status
Simulation time 135147038931 ps
CPU time 1236.12 seconds
Started Jan 14 03:03:45 PM PST 24
Finished Jan 14 03:24:22 PM PST 24
Peak memory 289684 kb
Host smart-b1946758-086b-4a10-a444-c489ecb8f89a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180341879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2180341879
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.914066119
Short name T692
Test name
Test status
Simulation time 417604297891 ps
CPU time 5472.4 seconds
Started Jan 14 03:03:45 PM PST 24
Finished Jan 14 04:34:59 PM PST 24
Peak memory 316780 kb
Host smart-76730c85-0695-4ff8-8ac1-d1dce1190d38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914066119 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.914066119
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2658144663
Short name T719
Test name
Test status
Simulation time 120794113599 ps
CPU time 2970.54 seconds
Started Jan 14 03:03:55 PM PST 24
Finished Jan 14 03:53:30 PM PST 24
Peak memory 286652 kb
Host smart-d477903b-0dc6-4637-be75-849723b8f70e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658144663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2658144663
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.279156505
Short name T484
Test name
Test status
Simulation time 8780423480 ps
CPU time 133.14 seconds
Started Jan 14 03:03:55 PM PST 24
Finished Jan 14 03:06:12 PM PST 24
Peak memory 256488 kb
Host smart-7806ab24-7e56-4495-b95d-9eae774dd96c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27915
6505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.279156505
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1439006195
Short name T628
Test name
Test status
Simulation time 32071408 ps
CPU time 2.87 seconds
Started Jan 14 03:03:56 PM PST 24
Finished Jan 14 03:04:02 PM PST 24
Peak memory 238548 kb
Host smart-b73e3bd4-4356-46ef-a13c-d936e710e809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14390
06195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1439006195
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1232579541
Short name T371
Test name
Test status
Simulation time 28719739166 ps
CPU time 1802.28 seconds
Started Jan 14 03:03:53 PM PST 24
Finished Jan 14 03:33:58 PM PST 24
Peak memory 273308 kb
Host smart-037b684b-496c-4d13-80cd-20d3c0c08bb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232579541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1232579541
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1084121840
Short name T294
Test name
Test status
Simulation time 48446785452 ps
CPU time 1390.74 seconds
Started Jan 14 03:03:54 PM PST 24
Finished Jan 14 03:27:06 PM PST 24
Peak memory 285716 kb
Host smart-d8057912-6358-4c01-bbea-75be357e0b8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084121840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1084121840
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2710804774
Short name T711
Test name
Test status
Simulation time 9126389376 ps
CPU time 392.87 seconds
Started Jan 14 03:03:53 PM PST 24
Finished Jan 14 03:10:28 PM PST 24
Peak memory 255496 kb
Host smart-5c17de21-bdac-4d85-bc98-2c05441d4a1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710804774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2710804774
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3728557557
Short name T590
Test name
Test status
Simulation time 832513899 ps
CPU time 25.19 seconds
Started Jan 14 03:03:44 PM PST 24
Finished Jan 14 03:04:10 PM PST 24
Peak memory 255504 kb
Host smart-2106db48-83d8-4463-aa59-c64fda889905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37285
57557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3728557557
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3466507631
Short name T619
Test name
Test status
Simulation time 4331670525 ps
CPU time 74.53 seconds
Started Jan 14 03:03:53 PM PST 24
Finished Jan 14 03:05:10 PM PST 24
Peak memory 247624 kb
Host smart-91d17b6e-4648-45d6-a920-dcc3876270a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34665
07631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3466507631
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.4001535833
Short name T56
Test name
Test status
Simulation time 696321784 ps
CPU time 11.26 seconds
Started Jan 14 03:03:53 PM PST 24
Finished Jan 14 03:04:07 PM PST 24
Peak memory 251244 kb
Host smart-d1641f56-35cf-48de-8ac4-8b5bb329e6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40015
35833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.4001535833
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2986599345
Short name T515
Test name
Test status
Simulation time 679506500 ps
CPU time 39.57 seconds
Started Jan 14 03:03:49 PM PST 24
Finished Jan 14 03:04:35 PM PST 24
Peak memory 248700 kb
Host smart-86ea9e95-c4a3-4b2d-b986-e5f0eec8b9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29865
99345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2986599345
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3609493552
Short name T311
Test name
Test status
Simulation time 34625557612 ps
CPU time 996.09 seconds
Started Jan 14 03:03:54 PM PST 24
Finished Jan 14 03:20:32 PM PST 24
Peak memory 282268 kb
Host smart-b9459e86-ec18-4b55-aa62-b2c3dc25cbc1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609493552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3609493552
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2157917322
Short name T13
Test name
Test status
Simulation time 348911482484 ps
CPU time 2198.34 seconds
Started Jan 14 03:04:04 PM PST 24
Finished Jan 14 03:40:44 PM PST 24
Peak memory 273532 kb
Host smart-7bd13642-129e-407d-b2d1-205c52165406
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157917322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2157917322
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2442580788
Short name T258
Test name
Test status
Simulation time 765913919 ps
CPU time 49.28 seconds
Started Jan 14 03:04:06 PM PST 24
Finished Jan 14 03:04:56 PM PST 24
Peak memory 256260 kb
Host smart-451d93ca-eb2a-4d0b-b62c-7e6475340c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24425
80788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2442580788
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2053638870
Short name T731
Test name
Test status
Simulation time 1955290344 ps
CPU time 33.99 seconds
Started Jan 14 03:04:04 PM PST 24
Finished Jan 14 03:04:39 PM PST 24
Peak memory 254112 kb
Host smart-dcad4e06-04ea-4b1a-8605-a5351afda3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20536
38870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2053638870
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2945359768
Short name T654
Test name
Test status
Simulation time 35263235161 ps
CPU time 2122.06 seconds
Started Jan 14 03:04:12 PM PST 24
Finished Jan 14 03:39:35 PM PST 24
Peak memory 272724 kb
Host smart-4983e0ac-49f2-44ea-ac49-50acca6ef61f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945359768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2945359768
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3303781030
Short name T569
Test name
Test status
Simulation time 161384860732 ps
CPU time 3167.85 seconds
Started Jan 14 03:04:15 PM PST 24
Finished Jan 14 03:57:04 PM PST 24
Peak memory 289604 kb
Host smart-33d7a497-0b19-4331-a8c4-a95c811fa366
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303781030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3303781030
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1151789157
Short name T546
Test name
Test status
Simulation time 21347440641 ps
CPU time 213.79 seconds
Started Jan 14 03:04:04 PM PST 24
Finished Jan 14 03:07:39 PM PST 24
Peak memory 248740 kb
Host smart-5b7ca0f4-8737-4db6-9db4-7d9e76e7b43e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151789157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1151789157
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2026375361
Short name T429
Test name
Test status
Simulation time 443385037 ps
CPU time 25.69 seconds
Started Jan 14 03:04:01 PM PST 24
Finished Jan 14 03:04:28 PM PST 24
Peak memory 248580 kb
Host smart-d03a0844-1b3c-4a43-83dd-5f2e84608839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20263
75361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2026375361
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2831781978
Short name T722
Test name
Test status
Simulation time 3108248825 ps
CPU time 38.82 seconds
Started Jan 14 03:04:04 PM PST 24
Finished Jan 14 03:04:44 PM PST 24
Peak memory 248824 kb
Host smart-0f920467-3808-4365-ba1d-d8f8baa414c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28317
81978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2831781978
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1304869032
Short name T459
Test name
Test status
Simulation time 119681829 ps
CPU time 15.01 seconds
Started Jan 14 03:04:03 PM PST 24
Finished Jan 14 03:04:19 PM PST 24
Peak memory 248584 kb
Host smart-3f2551cc-b0b5-4909-820c-82f3faffce0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13048
69032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1304869032
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1816794843
Short name T71
Test name
Test status
Simulation time 354319738 ps
CPU time 17.5 seconds
Started Jan 14 03:04:02 PM PST 24
Finished Jan 14 03:04:20 PM PST 24
Peak memory 248616 kb
Host smart-9c1fa417-a055-4181-85f6-f88bfab22374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18167
94843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1816794843
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2812691618
Short name T115
Test name
Test status
Simulation time 2146667410 ps
CPU time 92.32 seconds
Started Jan 14 03:04:14 PM PST 24
Finished Jan 14 03:05:46 PM PST 24
Peak memory 249648 kb
Host smart-8ab59343-0302-4de7-8318-8509a1227e1c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812691618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2812691618
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1389430443
Short name T491
Test name
Test status
Simulation time 51704797922 ps
CPU time 3987.69 seconds
Started Jan 14 03:04:09 PM PST 24
Finished Jan 14 04:10:38 PM PST 24
Peak memory 306088 kb
Host smart-3d32e07e-db23-4030-a0b3-eb3d0a49bba8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389430443 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1389430443
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.460020495
Short name T732
Test name
Test status
Simulation time 15421560208 ps
CPU time 861.4 seconds
Started Jan 14 03:04:19 PM PST 24
Finished Jan 14 03:18:41 PM PST 24
Peak memory 273080 kb
Host smart-ddd460ec-43bb-4696-98c4-c5b8f493932b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460020495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.460020495
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1235205083
Short name T632
Test name
Test status
Simulation time 25576214856 ps
CPU time 358.02 seconds
Started Jan 14 03:04:17 PM PST 24
Finished Jan 14 03:10:16 PM PST 24
Peak memory 256888 kb
Host smart-bfe39c92-ffb2-45f9-b4bd-bac1a4a22485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12352
05083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1235205083
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.837131004
Short name T580
Test name
Test status
Simulation time 832705259 ps
CPU time 22.75 seconds
Started Jan 14 03:04:11 PM PST 24
Finished Jan 14 03:04:34 PM PST 24
Peak memory 254768 kb
Host smart-0d0ad42a-d055-4ee6-bd8d-92cf4a10d599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83713
1004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.837131004
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3400356275
Short name T366
Test name
Test status
Simulation time 31881963313 ps
CPU time 660.71 seconds
Started Jan 14 03:04:16 PM PST 24
Finished Jan 14 03:15:18 PM PST 24
Peak memory 265224 kb
Host smart-eeb7f3d6-8af7-4b83-a284-c175da9bdd59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400356275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3400356275
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2147491732
Short name T51
Test name
Test status
Simulation time 137959795482 ps
CPU time 1798.3 seconds
Started Jan 14 03:04:20 PM PST 24
Finished Jan 14 03:34:20 PM PST 24
Peak memory 273308 kb
Host smart-be7b4fa2-321a-4175-a069-9818b9f4fc3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147491732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2147491732
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2192620227
Short name T636
Test name
Test status
Simulation time 37397834917 ps
CPU time 381.54 seconds
Started Jan 14 03:04:18 PM PST 24
Finished Jan 14 03:10:40 PM PST 24
Peak memory 246632 kb
Host smart-6318d42d-d2cf-4e21-ab65-11131a40d055
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192620227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2192620227
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3689045607
Short name T404
Test name
Test status
Simulation time 79577541 ps
CPU time 3.79 seconds
Started Jan 14 03:04:11 PM PST 24
Finished Jan 14 03:04:15 PM PST 24
Peak memory 240472 kb
Host smart-c74f62d7-a2eb-434e-b215-d0f78f2028a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36890
45607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3689045607
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2481889340
Short name T685
Test name
Test status
Simulation time 490210990 ps
CPU time 28.49 seconds
Started Jan 14 03:04:10 PM PST 24
Finished Jan 14 03:04:39 PM PST 24
Peak memory 254740 kb
Host smart-8e6d32ad-1e77-41fb-9238-6cc96d13d112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24818
89340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2481889340
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.941226489
Short name T554
Test name
Test status
Simulation time 34316355 ps
CPU time 3.25 seconds
Started Jan 14 03:04:19 PM PST 24
Finished Jan 14 03:04:23 PM PST 24
Peak memory 238720 kb
Host smart-2f5a5209-499d-41ca-ae39-f634b28ed15c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94122
6489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.941226489
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.371508914
Short name T625
Test name
Test status
Simulation time 370048639 ps
CPU time 11.8 seconds
Started Jan 14 03:04:11 PM PST 24
Finished Jan 14 03:04:24 PM PST 24
Peak memory 248732 kb
Host smart-7da12670-31d8-4683-a486-0d1676e076aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37150
8914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.371508914
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.272226032
Short name T143
Test name
Test status
Simulation time 2272760204 ps
CPU time 187.35 seconds
Started Jan 14 03:04:20 PM PST 24
Finished Jan 14 03:07:28 PM PST 24
Peak memory 253560 kb
Host smart-3b6bbc40-4b7e-41e8-b5f6-1eead2d1bf06
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272226032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.272226032
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.4119948937
Short name T225
Test name
Test status
Simulation time 51875381 ps
CPU time 4.09 seconds
Started Jan 14 02:59:09 PM PST 24
Finished Jan 14 02:59:14 PM PST 24
Peak memory 248836 kb
Host smart-03e9445c-4135-4a77-8b60-4b1cf0082a5f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4119948937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.4119948937
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1844439651
Short name T413
Test name
Test status
Simulation time 50335639316 ps
CPU time 1586.14 seconds
Started Jan 14 02:59:09 PM PST 24
Finished Jan 14 03:25:36 PM PST 24
Peak memory 265056 kb
Host smart-357f29c8-ba48-450d-a395-92ce394d867c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844439651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1844439651
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.4053335385
Short name T647
Test name
Test status
Simulation time 518562994 ps
CPU time 15.03 seconds
Started Jan 14 02:59:08 PM PST 24
Finished Jan 14 02:59:24 PM PST 24
Peak memory 248524 kb
Host smart-502df706-ac2f-41c3-9b03-f2152cb87083
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4053335385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.4053335385
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1223951195
Short name T256
Test name
Test status
Simulation time 679038084 ps
CPU time 56.02 seconds
Started Jan 14 02:59:02 PM PST 24
Finished Jan 14 02:59:58 PM PST 24
Peak memory 247912 kb
Host smart-870b5c7a-4060-40a9-ad39-6d59f74fd781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12239
51195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1223951195
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1375177125
Short name T659
Test name
Test status
Simulation time 45018725 ps
CPU time 4.04 seconds
Started Jan 14 02:59:04 PM PST 24
Finished Jan 14 02:59:09 PM PST 24
Peak memory 238732 kb
Host smart-36919549-0268-4347-bb81-2501e34fb667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13751
77125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1375177125
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1049237388
Short name T357
Test name
Test status
Simulation time 31619105893 ps
CPU time 933.1 seconds
Started Jan 14 02:59:02 PM PST 24
Finished Jan 14 03:14:36 PM PST 24
Peak memory 272796 kb
Host smart-d252da36-2555-4508-84d2-3cccd9127c4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049237388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1049237388
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1643027489
Short name T437
Test name
Test status
Simulation time 12913293663 ps
CPU time 1411.66 seconds
Started Jan 14 02:59:03 PM PST 24
Finished Jan 14 03:22:36 PM PST 24
Peak memory 289156 kb
Host smart-f4a1b338-9b77-426a-abb7-10f08eaa14c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643027489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1643027489
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.162495684
Short name T468
Test name
Test status
Simulation time 476647280 ps
CPU time 10.45 seconds
Started Jan 14 02:59:01 PM PST 24
Finished Jan 14 02:59:12 PM PST 24
Peak memory 248584 kb
Host smart-bf55ffc0-6684-4ccc-a0e6-a29f902a2301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16249
5684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.162495684
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3810437366
Short name T497
Test name
Test status
Simulation time 691797881 ps
CPU time 34.66 seconds
Started Jan 14 02:59:01 PM PST 24
Finished Jan 14 02:59:37 PM PST 24
Peak memory 254964 kb
Host smart-f7c13073-8c34-4859-9c7a-66dfb8b1bba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38104
37366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3810437366
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2468978656
Short name T423
Test name
Test status
Simulation time 2013622509 ps
CPU time 23.16 seconds
Started Jan 14 02:59:05 PM PST 24
Finished Jan 14 02:59:29 PM PST 24
Peak memory 255212 kb
Host smart-b895c339-c042-487d-8eb2-e2c66653e772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24689
78656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2468978656
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.951031634
Short name T99
Test name
Test status
Simulation time 658473228 ps
CPU time 13.9 seconds
Started Jan 14 02:59:03 PM PST 24
Finished Jan 14 02:59:18 PM PST 24
Peak memory 248676 kb
Host smart-bf3e12c8-d79c-464b-bb8d-e5d6f829589b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95103
1634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.951031634
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.63131083
Short name T283
Test name
Test status
Simulation time 110238823100 ps
CPU time 2081.13 seconds
Started Jan 14 02:59:01 PM PST 24
Finished Jan 14 03:33:44 PM PST 24
Peak memory 283184 kb
Host smart-ef18bdc5-07c8-4c4c-b96e-602ecec25e6a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63131083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handl
er_stress_all.63131083
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1711730273
Short name T626
Test name
Test status
Simulation time 59366193088 ps
CPU time 1303.61 seconds
Started Jan 14 02:59:04 PM PST 24
Finished Jan 14 03:20:49 PM PST 24
Peak memory 289740 kb
Host smart-89f2d097-1b61-4f5c-803a-7dbac3800191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711730273 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1711730273
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2923865273
Short name T229
Test name
Test status
Simulation time 38639185 ps
CPU time 3.4 seconds
Started Jan 14 02:59:13 PM PST 24
Finished Jan 14 02:59:18 PM PST 24
Peak memory 248948 kb
Host smart-71f40865-7228-4948-8d42-0396e6b5bf0f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2923865273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2923865273
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1357552797
Short name T310
Test name
Test status
Simulation time 23989067269 ps
CPU time 1146.02 seconds
Started Jan 14 02:59:14 PM PST 24
Finished Jan 14 03:18:21 PM PST 24
Peak memory 271604 kb
Host smart-1342ca84-7f8a-4495-b83a-c7d86629cb7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357552797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1357552797
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1517776270
Short name T467
Test name
Test status
Simulation time 505848510 ps
CPU time 15.08 seconds
Started Jan 14 02:59:10 PM PST 24
Finished Jan 14 02:59:26 PM PST 24
Peak memory 240392 kb
Host smart-3ce5fef8-f4ac-4954-a628-98f21f630b50
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1517776270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1517776270
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3042158831
Short name T609
Test name
Test status
Simulation time 1767202891 ps
CPU time 102.48 seconds
Started Jan 14 02:59:11 PM PST 24
Finished Jan 14 03:00:54 PM PST 24
Peak memory 248088 kb
Host smart-9b41d5e8-4744-4e7c-8556-c9e4f1b32dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30421
58831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3042158831
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.657435034
Short name T264
Test name
Test status
Simulation time 664625077 ps
CPU time 38.01 seconds
Started Jan 14 02:59:14 PM PST 24
Finished Jan 14 02:59:54 PM PST 24
Peak memory 248204 kb
Host smart-848de376-de3c-4cb9-8df7-91d6d61d74f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65743
5034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.657435034
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1093868871
Short name T607
Test name
Test status
Simulation time 46936211856 ps
CPU time 3080.01 seconds
Started Jan 14 02:59:12 PM PST 24
Finished Jan 14 03:50:34 PM PST 24
Peak memory 288744 kb
Host smart-8ad931c6-324d-4f91-b9d9-cb8397b7da2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093868871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1093868871
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.323730866
Short name T325
Test name
Test status
Simulation time 43333691767 ps
CPU time 467.79 seconds
Started Jan 14 02:59:12 PM PST 24
Finished Jan 14 03:07:01 PM PST 24
Peak memory 247636 kb
Host smart-4e7482d7-7ea0-4a32-a479-97092d8dd10d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323730866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.323730866
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1588606769
Short name T528
Test name
Test status
Simulation time 75201320 ps
CPU time 5.75 seconds
Started Jan 14 02:59:12 PM PST 24
Finished Jan 14 02:59:19 PM PST 24
Peak memory 252148 kb
Host smart-df46d4b2-bce2-4cd3-9860-41a8d026fa4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15886
06769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1588606769
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2456162018
Short name T2
Test name
Test status
Simulation time 1147129214 ps
CPU time 64.98 seconds
Started Jan 14 02:59:15 PM PST 24
Finished Jan 14 03:00:21 PM PST 24
Peak memory 256200 kb
Host smart-027bfcff-291b-4544-88cf-18d40235d80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24561
62018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2456162018
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.16749315
Short name T500
Test name
Test status
Simulation time 121824759 ps
CPU time 14.98 seconds
Started Jan 14 02:59:04 PM PST 24
Finished Jan 14 02:59:20 PM PST 24
Peak memory 255176 kb
Host smart-51ac460f-cc17-4a2c-ad30-cc68ace6d03f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16749
315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.16749315
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.4105421176
Short name T557
Test name
Test status
Simulation time 124207231153 ps
CPU time 2331.52 seconds
Started Jan 14 02:59:15 PM PST 24
Finished Jan 14 03:38:08 PM PST 24
Peak memory 284800 kb
Host smart-7b918ef6-2ac1-433e-af31-473aad6392d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105421176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.4105421176
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2287416510
Short name T230
Test name
Test status
Simulation time 55597320 ps
CPU time 3.16 seconds
Started Jan 14 02:59:16 PM PST 24
Finished Jan 14 02:59:20 PM PST 24
Peak memory 248908 kb
Host smart-52152513-8fd8-47bd-a6e4-508841931951
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2287416510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2287416510
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.347640373
Short name T608
Test name
Test status
Simulation time 68596749076 ps
CPU time 1498.97 seconds
Started Jan 14 02:59:13 PM PST 24
Finished Jan 14 03:24:13 PM PST 24
Peak memory 265188 kb
Host smart-fe759af6-185a-4167-ae33-43c567bb4b98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347640373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.347640373
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.389634674
Short name T470
Test name
Test status
Simulation time 2254331055 ps
CPU time 25.49 seconds
Started Jan 14 02:59:20 PM PST 24
Finished Jan 14 02:59:47 PM PST 24
Peak memory 240436 kb
Host smart-0afee902-1e35-4360-8699-719d6521ffd2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=389634674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.389634674
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1035441813
Short name T522
Test name
Test status
Simulation time 6627223043 ps
CPU time 88.47 seconds
Started Jan 14 02:59:13 PM PST 24
Finished Jan 14 03:00:43 PM PST 24
Peak memory 248172 kb
Host smart-2b4f6a37-c2d5-4792-ad90-94103b61c812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10354
41813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1035441813
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2235685425
Short name T548
Test name
Test status
Simulation time 184790630 ps
CPU time 14.75 seconds
Started Jan 14 02:59:16 PM PST 24
Finished Jan 14 02:59:32 PM PST 24
Peak memory 248800 kb
Host smart-36c09eaa-a543-46fd-953f-cb0242bbc9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22356
85425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2235685425
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.939157332
Short name T315
Test name
Test status
Simulation time 689671088276 ps
CPU time 2588.93 seconds
Started Jan 14 02:59:21 PM PST 24
Finished Jan 14 03:42:31 PM PST 24
Peak memory 283120 kb
Host smart-4f9d4ce3-d585-42e6-841f-b9d838599911
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939157332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.939157332
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2197378179
Short name T624
Test name
Test status
Simulation time 43852466749 ps
CPU time 2316.01 seconds
Started Jan 14 02:59:16 PM PST 24
Finished Jan 14 03:37:53 PM PST 24
Peak memory 285236 kb
Host smart-dc460074-e74b-402c-a55b-fe1f97bcd306
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197378179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2197378179
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1224508145
Short name T337
Test name
Test status
Simulation time 8839816166 ps
CPU time 347 seconds
Started Jan 14 02:59:13 PM PST 24
Finished Jan 14 03:05:02 PM PST 24
Peak memory 247584 kb
Host smart-d934b493-7b71-41fa-a5c4-bebe195bd180
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224508145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1224508145
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2434314898
Short name T408
Test name
Test status
Simulation time 416841250 ps
CPU time 26.02 seconds
Started Jan 14 02:59:12 PM PST 24
Finished Jan 14 02:59:39 PM PST 24
Peak memory 248652 kb
Host smart-3087d2db-94f8-4e84-8931-454b37ebd302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24343
14898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2434314898
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3279793146
Short name T300
Test name
Test status
Simulation time 6688273963 ps
CPU time 48.28 seconds
Started Jan 14 02:59:13 PM PST 24
Finished Jan 14 03:00:02 PM PST 24
Peak memory 255608 kb
Host smart-dd429b69-18c4-4ac4-9307-42f5915d196a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32797
93146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3279793146
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.975869716
Short name T480
Test name
Test status
Simulation time 1029512344 ps
CPU time 49.58 seconds
Started Jan 14 02:59:10 PM PST 24
Finished Jan 14 03:00:01 PM PST 24
Peak memory 256692 kb
Host smart-787fa103-18f2-4f5e-801a-eb3f2f00ea5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97586
9716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.975869716
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.397835584
Short name T432
Test name
Test status
Simulation time 56713793 ps
CPU time 3.69 seconds
Started Jan 14 02:59:11 PM PST 24
Finished Jan 14 02:59:16 PM PST 24
Peak memory 248704 kb
Host smart-2c40cb08-85f9-4d84-82c0-611535b939fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39783
5584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.397835584
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2063517414
Short name T593
Test name
Test status
Simulation time 108295784246 ps
CPU time 1971 seconds
Started Jan 14 02:59:14 PM PST 24
Finished Jan 14 03:32:07 PM PST 24
Peak memory 285116 kb
Host smart-78830a2c-60b4-47c4-9167-99190ce9e646
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063517414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2063517414
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1849744942
Short name T529
Test name
Test status
Simulation time 54668608251 ps
CPU time 3829.1 seconds
Started Jan 14 02:59:14 PM PST 24
Finished Jan 14 04:03:05 PM PST 24
Peak memory 305212 kb
Host smart-e886d8d5-b673-4f56-9660-5ec1df7cd6aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849744942 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1849744942
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.502270129
Short name T235
Test name
Test status
Simulation time 51393158 ps
CPU time 4.08 seconds
Started Jan 14 02:59:26 PM PST 24
Finished Jan 14 02:59:31 PM PST 24
Peak memory 248192 kb
Host smart-da3ec6bd-786b-4986-8c41-f902817e81dd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=502270129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.502270129
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3018226317
Short name T600
Test name
Test status
Simulation time 61780394337 ps
CPU time 1941.66 seconds
Started Jan 14 02:59:21 PM PST 24
Finished Jan 14 03:31:44 PM PST 24
Peak memory 273064 kb
Host smart-5f41ec16-c130-4145-93f4-6a882161b0cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018226317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3018226317
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2769824089
Short name T419
Test name
Test status
Simulation time 459712541 ps
CPU time 21.11 seconds
Started Jan 14 02:59:20 PM PST 24
Finished Jan 14 02:59:42 PM PST 24
Peak memory 240432 kb
Host smart-5eee1497-f0cc-40fa-9b05-66236c0912f9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2769824089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2769824089
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.605996609
Short name T295
Test name
Test status
Simulation time 26618191281 ps
CPU time 179.03 seconds
Started Jan 14 02:59:18 PM PST 24
Finished Jan 14 03:02:18 PM PST 24
Peak memory 256164 kb
Host smart-366818e2-7675-4a09-98e3-537d9d7841e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60599
6609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.605996609
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3978603421
Short name T35
Test name
Test status
Simulation time 969816419 ps
CPU time 43.31 seconds
Started Jan 14 02:59:13 PM PST 24
Finished Jan 14 02:59:57 PM PST 24
Peak memory 254872 kb
Host smart-f705e771-6b4f-4b43-b138-d2cd86eb6963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39786
03421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3978603421
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1477991974
Short name T331
Test name
Test status
Simulation time 36461474647 ps
CPU time 2197.77 seconds
Started Jan 14 02:59:16 PM PST 24
Finished Jan 14 03:35:55 PM PST 24
Peak memory 281508 kb
Host smart-2dfd5d1f-87d1-4e80-990c-3486b3a29c96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477991974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1477991974
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.4278098043
Short name T435
Test name
Test status
Simulation time 98072780476 ps
CPU time 1942.02 seconds
Started Jan 14 02:59:26 PM PST 24
Finished Jan 14 03:31:50 PM PST 24
Peak memory 272152 kb
Host smart-6367faba-a226-4877-bb42-2717f025abc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278098043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.4278098043
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3418138705
Short name T684
Test name
Test status
Simulation time 20109181789 ps
CPU time 281.39 seconds
Started Jan 14 02:59:14 PM PST 24
Finished Jan 14 03:03:57 PM PST 24
Peak memory 247292 kb
Host smart-07e7aa9e-2b0f-47fe-bf77-acbfa5935817
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418138705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3418138705
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2497646295
Short name T450
Test name
Test status
Simulation time 664189252 ps
CPU time 13.83 seconds
Started Jan 14 02:59:13 PM PST 24
Finished Jan 14 02:59:29 PM PST 24
Peak memory 256688 kb
Host smart-49474b86-96e0-4cca-b8aa-d7b27052e628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24976
46295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2497646295
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1122542768
Short name T39
Test name
Test status
Simulation time 146148704 ps
CPU time 8.53 seconds
Started Jan 14 02:59:18 PM PST 24
Finished Jan 14 02:59:27 PM PST 24
Peak memory 248292 kb
Host smart-cdf030df-31d2-46f5-bedf-d360c7fa077a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11225
42768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1122542768
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3774070833
Short name T277
Test name
Test status
Simulation time 933401303 ps
CPU time 59.27 seconds
Started Jan 14 02:59:20 PM PST 24
Finished Jan 14 03:00:20 PM PST 24
Peak memory 255268 kb
Host smart-83258eb6-d86a-4b09-8f62-eaee0879a774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37740
70833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3774070833
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2875432597
Short name T388
Test name
Test status
Simulation time 3876630394 ps
CPU time 31.21 seconds
Started Jan 14 02:59:19 PM PST 24
Finished Jan 14 02:59:52 PM PST 24
Peak memory 256884 kb
Host smart-28719451-032a-4fa8-87c6-0df03bfd9166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28754
32597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2875432597
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.701893611
Short name T653
Test name
Test status
Simulation time 26474877912 ps
CPU time 1892.3 seconds
Started Jan 14 02:59:18 PM PST 24
Finished Jan 14 03:30:52 PM PST 24
Peak memory 289628 kb
Host smart-81afb7c9-e71a-4cd7-a8ae-922584ee0810
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701893611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.701893611
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1832126332
Short name T138
Test name
Test status
Simulation time 36375569 ps
CPU time 3.28 seconds
Started Jan 14 02:59:24 PM PST 24
Finished Jan 14 02:59:28 PM PST 24
Peak memory 248840 kb
Host smart-27e2b66d-f1ee-43c6-97b3-e49a2a515252
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1832126332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1832126332
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.776136371
Short name T430
Test name
Test status
Simulation time 12400960440 ps
CPU time 1059.6 seconds
Started Jan 14 02:59:22 PM PST 24
Finished Jan 14 03:17:03 PM PST 24
Peak memory 288912 kb
Host smart-7c1f7de8-9a78-4c92-b359-d0dc82ca8c79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776136371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.776136371
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1660300843
Short name T704
Test name
Test status
Simulation time 699255628 ps
CPU time 30.96 seconds
Started Jan 14 02:59:21 PM PST 24
Finished Jan 14 02:59:54 PM PST 24
Peak memory 248592 kb
Host smart-baba4e12-d3d2-47c5-9d17-57c1a2caada4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1660300843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1660300843
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2258622116
Short name T414
Test name
Test status
Simulation time 9914927354 ps
CPU time 285.75 seconds
Started Jan 14 02:59:21 PM PST 24
Finished Jan 14 03:04:08 PM PST 24
Peak memory 256888 kb
Host smart-4a5468d8-67da-4ac2-ab3f-0d80d9fa392d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22586
22116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2258622116
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3027446691
Short name T487
Test name
Test status
Simulation time 2211538429 ps
CPU time 36.58 seconds
Started Jan 14 02:59:22 PM PST 24
Finished Jan 14 02:59:59 PM PST 24
Peak memory 256792 kb
Host smart-908294d7-2d22-45a3-82da-ebc022515b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30274
46691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3027446691
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1160571750
Short name T664
Test name
Test status
Simulation time 25558325941 ps
CPU time 1424.66 seconds
Started Jan 14 02:59:17 PM PST 24
Finished Jan 14 03:23:03 PM PST 24
Peak memory 272932 kb
Host smart-8d4a7003-5b3f-4c18-9800-95c9b31b1495
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160571750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1160571750
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1779939259
Short name T16
Test name
Test status
Simulation time 18154827191 ps
CPU time 941 seconds
Started Jan 14 02:59:21 PM PST 24
Finished Jan 14 03:15:03 PM PST 24
Peak memory 272120 kb
Host smart-63ae6448-3401-417f-a1a7-01957f31ae84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779939259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1779939259
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3612086632
Short name T489
Test name
Test status
Simulation time 332607462 ps
CPU time 28.05 seconds
Started Jan 14 02:59:26 PM PST 24
Finished Jan 14 02:59:55 PM PST 24
Peak memory 248680 kb
Host smart-9b947112-eee8-4b7b-8072-6c09eb8987ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36120
86632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3612086632
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2262318570
Short name T122
Test name
Test status
Simulation time 1032107843 ps
CPU time 56.52 seconds
Started Jan 14 02:59:24 PM PST 24
Finished Jan 14 03:00:22 PM PST 24
Peak memory 256052 kb
Host smart-1d451a99-e347-48b7-a37f-8e643fe28c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22623
18570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2262318570
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3693684940
Short name T612
Test name
Test status
Simulation time 198443574 ps
CPU time 14.36 seconds
Started Jan 14 02:59:20 PM PST 24
Finished Jan 14 02:59:35 PM PST 24
Peak memory 248616 kb
Host smart-bf298000-40db-4fdd-99f6-baba72efa449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36936
84940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3693684940
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.98097510
Short name T434
Test name
Test status
Simulation time 717115304 ps
CPU time 34.36 seconds
Started Jan 14 02:59:19 PM PST 24
Finished Jan 14 02:59:55 PM PST 24
Peak memory 248600 kb
Host smart-1bf6944c-7c08-47ea-930a-a2ced8c8d99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98097
510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.98097510
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3648073058
Short name T109
Test name
Test status
Simulation time 179015685973 ps
CPU time 2823.13 seconds
Started Jan 14 02:59:22 PM PST 24
Finished Jan 14 03:46:26 PM PST 24
Peak memory 285412 kb
Host smart-03a303a3-f87d-4146-86ad-1f2dcc474491
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648073058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3648073058
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1048122166
Short name T253
Test name
Test status
Simulation time 275268668097 ps
CPU time 4724.51 seconds
Started Jan 14 02:59:18 PM PST 24
Finished Jan 14 04:18:04 PM PST 24
Peak memory 305620 kb
Host smart-41a94f8c-342e-458c-9388-ea1d3f1e6cb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048122166 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1048122166
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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