Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	117642	1			T2	28		T36	1262		T17	1381
class_i[0x1]	51170	1			T2	2		T21	509		T6	8
class_i[0x2]	84474	1			T2	1585		T21	1		T6	3
class_i[0x3]	46698	1			T2	52		T21	1		T16	2931

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	74977	1			T2	66		T21	91		T16	743
alert[0x1]	72300	1			T2	66		T21	153		T6	1
alert[0x2]	80303	1			T2	1423		T21	127		T6	8
alert[0x3]	72404	1			T2	112		T21	140		T6	2

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

299722

1

T2

1667

T21

511

T6

11

esc_ping_fail

262

1

T8

4

T10

7

T11

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	74902	1			T2	66		T21	91		T16	743
esc_integrity_fail	alert[0x1]	72236	1			T2	66		T21	153		T6	1
esc_integrity_fail	alert[0x2]	80233	1			T2	1423		T21	127		T6	8
esc_integrity_fail	alert[0x3]	72351	1			T2	112		T21	140		T6	2
esc_ping_fail	alert[0x0]	75	1			T10	2		T11	1		T208	2
esc_ping_fail	alert[0x1]	64	1			T8	1		T10	3		T11	1
esc_ping_fail	alert[0x2]	70	1			T8	2		T10	1		T11	1
esc_ping_fail	alert[0x3]	53	1			T8	1		T10	1		T291	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	117561	1			T2	28		T36	1262		T17	1381
esc_integrity_fail	class_i[0x1]	51104	1			T2	2		T21	509		T6	8
esc_integrity_fail	class_i[0x2]	84418	1			T2	1585		T21	1		T6	3
esc_integrity_fail	class_i[0x3]	46639	1			T2	52		T21	1		T16	2931
esc_ping_fail	class_i[0x0]	81	1			T11	1		T292	9		T297	1
esc_ping_fail	class_i[0x1]	66	1			T8	4		T11	1		T208	2
esc_ping_fail	class_i[0x2]	56	1			T10	7		T208	1		T279	1
esc_ping_fail	class_i[0x3]	59	1			T11	1		T208	1		T291	1