Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	757565810	0	0	642
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	757565810	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	757565810	757389604	0	0
tb.dut.CheckAccuCntDw	0	0	642	642	0	0
tb.dut.CheckEscCntDw	0	0	642	642	0	0
tb.dut.CheckNAlerts	0	0	642	642	0	0
tb.dut.CheckNClasses	0	0	642	642	0	0
tb.dut.CheckNEscSev	0	0	642	642	0	0
tb.dut.CrashdumpKnownO_A	0	0	757565810	757389604	0	0
tb.dut.EdnKnownO_A	0	0	757565810	757389604	0	0
tb.dut.EscPKnownO_A	0	0	757565810	757389604	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	757565810	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	757565810	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	757565810	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	757565810	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	757565810	80	0	0
tb.dut.IrqAKnownO_A	0	0	757565810	757389604	0	0
tb.dut.IrqBKnownO_A	0	0	757565810	757389604	0	0
tb.dut.IrqCKnownO_A	0	0	757565810	757389604	0	0
tb.dut.IrqDKnownO_A	0	0	757565810	757389604	0	0
tb.dut.TlAReadyKnownO_A	0	0	757565810	757389604	0	0
tb.dut.TlDValidKnownO_A	0	0	757565810	757389604	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	788469729	5155585	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	788469729	28061	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	788469729	27913	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	788469729	28428	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	788469729	28007	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	788469729	28113	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	788469729	28395	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	788469729	27830	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	788469729	28987	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	788469729	27369	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	788469729	28335	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	788469729	27970	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	788469729	27199	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	788469729	27715	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	788469729	28819	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	788469729	29067	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	788469729	27738	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	788469729	27534	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	788469729	27249	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	788469729	27915	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	788469729	27287	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	788469729	28575	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	788469729	29185	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	788469729	28170	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	788469729	27784	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	788469729	27659	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	788469729	28854	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	788469729	28003	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	788469729	28385	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	788469729	28153	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	788469729	28590	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	788469729	28537	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	788469729	27524	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	788469729	28110	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	788469729	27560	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	788469729	27532	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	788469729	28070	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	788469729	27922	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	788469729	28043	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	788469729	28416	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	788469729	27610	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	788469729	28432	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	788469729	27603	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	788469729	28580	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	788469729	28838	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	788469729	28392	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	788469729	27725	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	788469729	28467	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	788469729	27689	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	788469729	28242	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	788469729	28511	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	788469729	27416	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	788469729	27764	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	788469729	28118	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	788469729	28853	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	788469729	27815	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	788469729	27662	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	788469729	27942	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	788469729	27517	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	788469729	28454	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	788469729	28386	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	788469729	28688	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	788469729	27809	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	788469729	27437	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	788469729	27881	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	788469729	28459	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	788469729	28078	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	788469729	28720	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	788469729	27779	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	788469729	27781	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	788469729	53469	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	788469729	28684	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	788469729	28551	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	788469729	28406	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	788469729	27718	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	788469729	27629	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	788469729	27905	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	788469729	28043	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	788469729	28364	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	757565810	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	757565810	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	757565810	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	757565810	3541	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	757565810	336756	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	757565810	351442374	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	757565810	339	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	757565810	1036	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	757565810	75	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	757565810	571	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	757331867	285611615	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	757565810	1170	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	757565810	1142	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	757565810	1114	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	757565810	1093	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	757565810	1336	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	757565810	146339	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	757565810	1186	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	757565810	75	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	757565810	1475	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	757565810	1235	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	642	642	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	757565810	757389604	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	757565810	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	757565810	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	757565810	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	757565810	2903	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	757565810	190862	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	757565810	428081339	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	757565810	309	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	757565810	555	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	757565810	28	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	757565810	255	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	757331867	343965398	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	757565810	646	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	757565810	635	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	757565810	626	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	757565810	613	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	757565810	1155	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	757565810	133189	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	757565810	1055	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	757565810	72	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	757565810	1444	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	757565810	1204	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	642	642	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	757565810	757389604	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	757565810	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	757565810	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	757565810	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	757565810	7153	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	757565810	220060	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	757565810	395396141	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	757565810	278	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	757565810	610	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	757565810	26	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	757565810	287	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	757331867	317619368	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	757565810	704	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	757565810	693	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	757565810	675	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	757565810	668	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	757565810	1286	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	757565810	138809	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	757565810	1180	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	757565810	80	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	757565810	1451	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	757565810	1211	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	642	642	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	757565810	757389604	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	757565810	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	757565810	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	757565810	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	757565810	4028	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	757565810	164905	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	757565810	463967684	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	757565810	287	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	757565810	535	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	757565810	27	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	757565810	256	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	757331867	382125760	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	757565810	633	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	757565810	623	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	757565810	610	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	757565810	603	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	757565810	940	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	757565810	112448	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	757565810	834	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	757565810	79	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	757565810	1462	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	757565810	1222	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	642	642	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	757565810	757389604	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	788469729	176458905	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	788469729	787753675	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	788469729	787753675	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	788469729	222094794	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	788469729	787753675	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	788469729	787753675	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	847	847	0	0
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