Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	210	1			T2	1		T5	1		T16	1
index[0x1]	200	1			T1	1		T2	1		T21	1
index[0x2]	197	1			T2	2		T21	1		T23	1
index[0x3]	237	1			T2	3		T6	1		T17	2

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	293	1			T2	1		T21	1		T16	2
lens_less_than_1000[1]	166	1			T1	1		T2	2		T5	1
lens_less_than_1000[2]	105	1			T2	1		T23	1		T17	2
lens_less_than_1000[3]	85	1			T17	1		T19	1		T20	1
lens_less_than_1000[4]	65	1			T2	2		T17	1		T19	1
lens_less_than_1000[5]	50	1			T21	1		T6	1		T20	2
lens_less_than_1000[6]	39	1			T17	1		T55	1		T256	1
lens_less_than_1000[7]	18	1			T20	1		T70	1		T38	1
lens_less_than_1000[8]	9	1			T58	1		T106	1		T244	1
lens_less_than_1000[9]	6	1			T58	1		T40	1		T106	1
len_2	8	1			T2	1		T53	1		T78	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x2]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	80	1			T16	1		T36	1		T17	1
index[0x0]	lens_less_than_1000[1]	41	1			T5	1		T53	1		T49	1
index[0x0]	lens_less_than_1000[2]	24	1			T2	1		T53	1		T76	1
index[0x0]	lens_less_than_1000[3]	22	1			T49	1		T97	1		T95	1
index[0x0]	lens_less_than_1000[4]	14	1			T19	1		T210	1		T211	1
index[0x0]	lens_less_than_1000[5]	9	1			T20	1		T229	1		T228	1
index[0x0]	lens_less_than_1000[6]	11	1			T83	1		T257	1		T90	3
index[0x0]	lens_less_than_1000[7]	3	1			T258	1		T259	1		T260	1
index[0x0]	lens_less_than_1000[8]	1	1			T261	1		-	-		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T262	1		-	-		-	-
index[0x0]	len_2	4	1			T244	1		T263	1		T235	1
index[0x1]	lens_less_than_1000[0]	67	1			T21	1		T16	1		T19	1
index[0x1]	lens_less_than_1000[1]	42	1			T1	1		T2	1		T17	1
index[0x1]	lens_less_than_1000[2]	20	1			T17	2		T110	3		T83	1
index[0x1]	lens_less_than_1000[3]	21	1			T38	1		T58	1		T59	2
index[0x1]	lens_less_than_1000[4]	16	1			T17	1		T38	1		T97	1
index[0x1]	lens_less_than_1000[5]	13	1			T20	1		T111	1		T264	1
index[0x1]	lens_less_than_1000[6]	13	1			T55	1		T100	1		T111	1
index[0x1]	lens_less_than_1000[7]	2	1			T250	1		T260	1		-	-
index[0x1]	lens_less_than_1000[8]	3	1			T254	1		T265	2		-	-
index[0x1]	lens_less_than_1000[9]	2	1			T40	1		T266	1		-	-
index[0x1]	len_2	1	1			T78	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	66	1			T2	1		T53	2		T19	1
index[0x2]	lens_less_than_1000[1]	42	1			T98	4		T267	1		T110	1
index[0x2]	lens_less_than_1000[2]	20	1			T23	1		T20	1		T69	1
index[0x2]	lens_less_than_1000[3]	16	1			T20	1		T117	1		T61	1
index[0x2]	lens_less_than_1000[4]	17	1			T2	1		T49	1		T50	1
index[0x2]	lens_less_than_1000[5]	20	1			T21	1		T268	1		T83	1
index[0x2]	lens_less_than_1000[6]	7	1			T256	1		T269	1		T270	1
index[0x2]	lens_less_than_1000[7]	5	1			T20	1		T271	1		T270	1
index[0x2]	lens_less_than_1000[8]	3	1			T106	1		T244	1		T265	1
index[0x2]	len_2	1	1			T53	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	80	1			T53	1		T19	2		T70	1
index[0x3]	lens_less_than_1000[1]	41	1			T2	1		T48	1		T98	2
index[0x3]	lens_less_than_1000[2]	41	1			T20	1		T75	1		T58	3
index[0x3]	lens_less_than_1000[3]	26	1			T17	1		T19	1		T8	1
index[0x3]	lens_less_than_1000[4]	18	1			T2	1		T109	1		T83	1
index[0x3]	lens_less_than_1000[5]	8	1			T6	1		T226	1		T228	1
index[0x3]	lens_less_than_1000[6]	8	1			T17	1		T110	1		T272	1
index[0x3]	lens_less_than_1000[7]	8	1			T70	1		T38	1		T226	1
index[0x3]	lens_less_than_1000[8]	2	1			T58	1		T273	1		-	-
index[0x3]	lens_less_than_1000[9]	3	1			T58	1		T106	1		T274	1
index[0x3]	len_2	2	1			T2	1		T111	1		-	-