Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	75	1			T2	1		T72	1		T55	1
class_index[0x1]	72	1			T2	1		T36	2		T72	2
class_index[0x2]	80	1			T2	1		T21	3		T17	2
class_index[0x3]	79	1			T25	1		T52	3		T20	4

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	120	1			T2	1		T21	1		T25	1
intr_timeout_cnt[1]	58	1			T73	1		T52	3		T83	1
intr_timeout_cnt[2]	40	1			T2	1		T75	2		T60	1
intr_timeout_cnt[3]	18	1			T53	1		T75	1		T38	1
intr_timeout_cnt[4]	14	1			T60	1		T229	1		T88	1
intr_timeout_cnt[5]	13	1			T75	1		T109	1		T110	1
intr_timeout_cnt[6]	11	1			T21	2		T38	2		T88	1
intr_timeout_cnt[7]	17	1			T75	1		T44	1		T230	1
intr_timeout_cnt[8]	11	1			T36	2		T59	1		T44	1
intr_timeout_cnt[9]	4	1			T2	1		T231	1		T232	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	41	1			T72	1		T55	1		T38	5
class_index[0x0]	intr_timeout_cnt[1]	16	1			T83	1		T111	1		T233	1
class_index[0x0]	intr_timeout_cnt[2]	1	1			T2	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[3]	1	1			T234	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[4]	4	1			T231	1		T235	1		T236	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T231	1		T237	1		T228	1
class_index[0x0]	intr_timeout_cnt[6]	3	1			T38	1		T88	1		T238	1
class_index[0x0]	intr_timeout_cnt[7]	4	1			T75	1		T44	1		T230	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T239	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	26	1			T72	2		T53	1		T81	1
class_index[0x1]	intr_timeout_cnt[1]	17	1			T73	1		T111	1		T113	1
class_index[0x1]	intr_timeout_cnt[2]	11	1			T100	1		T61	4		T240	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T241	1		T242	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	5	1			T60	1		T229	1		T243	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T244	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	8	1			T36	2		T59	1		T44	1
class_index[0x1]	intr_timeout_cnt[9]	2	1			T2	1		T232	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	29	1			T2	1		T21	1		T17	2
class_index[0x2]	intr_timeout_cnt[1]	9	1			T106	1		T92	1		T245	1
class_index[0x2]	intr_timeout_cnt[2]	18	1			T75	1		T60	1		T94	4
class_index[0x2]	intr_timeout_cnt[3]	7	1			T53	1		T75	1		T244	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T88	1		T104	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	6	1			T109	1		T110	1		T100	2
class_index[0x2]	intr_timeout_cnt[6]	5	1			T21	2		T246	1		T234	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T247	1		T235	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T229	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T248	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	24	1			T25	1		T20	4		T74	1
class_index[0x3]	intr_timeout_cnt[1]	16	1			T52	3		T113	1		T249	1
class_index[0x3]	intr_timeout_cnt[2]	10	1			T75	1		T117	1		T250	1
class_index[0x3]	intr_timeout_cnt[3]	8	1			T38	1		T118	1		T237	1
class_index[0x3]	intr_timeout_cnt[4]	3	1			T244	1		T251	1		T238	1
class_index[0x3]	intr_timeout_cnt[5]	3	1			T75	1		T244	1		T252	1
class_index[0x3]	intr_timeout_cnt[6]	2	1			T38	1		T252	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	11	1			T244	1		T253	1		T254	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T255	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T231	1		-	-		-	-