Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	404322	1			T27	1		T29	5		T30	5
all_values[1]	404322	1			T27	1		T29	5		T30	5
all_values[2]	404322	1			T27	1		T29	5		T30	5
all_values[3]	404322	1			T27	1		T29	5		T30	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

805454

1

T27

4

T29

13

T30

11

auto[1]

811834

1

T29

7

T30

9

T34

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

970952

1

T27

4

T29

14

T30

15

auto[1]

646336

1

T29

6

T30

5

T34

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	115735	1			T27	1		T29	4		T30	5
all_values[0]	auto[0]	auto[1]	85712	1			T29	1		T34	1		T185	4
all_values[0]	auto[1]	auto[0]	116974	1			T34	1		T120	2		T223	2
all_values[0]	auto[1]	auto[1]	85901	1			T120	2		T223	2		T224	1
all_values[1]	auto[0]	auto[0]	122906	1			T27	1		T29	3		T30	1
all_values[1]	auto[0]	auto[1]	79257	1			T29	1		T34	2		T185	1
all_values[1]	auto[1]	auto[0]	123455	1			T30	3		T34	1		T185	1
all_values[1]	auto[1]	auto[1]	78704	1			T29	1		T30	1		T34	1
all_values[2]	auto[0]	auto[0]	120785	1			T27	1		T29	1		T30	4
all_values[2]	auto[0]	auto[1]	80182	1			T333	1		T334	1		T335	4
all_values[2]	auto[1]	auto[0]	122650	1			T29	1		T34	2		T185	1
all_values[2]	auto[1]	auto[1]	80705	1			T29	3		T30	1		T34	3
all_values[3]	auto[0]	auto[0]	123261	1			T27	1		T29	3		T30	1
all_values[3]	auto[0]	auto[1]	77616	1			T34	1		T185	3		T120	1
all_values[3]	auto[1]	auto[0]	125186	1			T29	2		T30	1		T120	3
all_values[3]	auto[1]	auto[1]	78259	1			T30	3		T34	1		T185	1