Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	404322	1			T27	1		T29	5		T30	5
all_pins[1]	404322	1			T27	1		T29	5		T30	5
all_pins[2]	404322	1			T27	1		T29	5		T30	5
all_pins[3]	404322	1			T27	1		T29	5		T30	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1293719	1			T27	4		T29	16		T30	15
values[0x1]	323569	1			T29	4		T30	5		T34	5
transitions[0x0=>0x1]	216291	1			T29	4		T30	3		T34	4
transitions[0x1=>0x0]	216549	1			T29	4		T30	3		T34	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	318421	1			T27	1		T29	5		T30	5
all_pins[0]	values[0x1]	85901	1			T120	2		T223	2		T224	1
all_pins[0]	transitions[0x0=>0x1]	85108	1			T120	2		T223	2		T333	2
all_pins[0]	transitions[0x1=>0x0]	77724	1			T30	3		T34	1		T185	1
all_pins[1]	values[0x0]	325618	1			T27	1		T29	4		T30	4
all_pins[1]	values[0x1]	78704	1			T29	1		T30	1		T34	1
all_pins[1]	transitions[0x0=>0x1]	43496	1			T29	1		T30	1		T34	1
all_pins[1]	transitions[0x1=>0x0]	50693	1			T120	2		T223	2		T224	1
all_pins[2]	values[0x0]	323617	1			T27	1		T29	2		T30	4
all_pins[2]	values[0x1]	80705	1			T29	3		T30	1		T34	3
all_pins[2]	transitions[0x0=>0x1]	45157	1			T29	3		T34	2		T185	1
all_pins[2]	transitions[0x1=>0x0]	43156	1			T29	1		T185	2		T120	1
all_pins[3]	values[0x0]	326063	1			T27	1		T29	5		T30	2
all_pins[3]	values[0x1]	78259	1			T30	3		T34	1		T185	1
all_pins[3]	transitions[0x0=>0x1]	42530	1			T30	2		T34	1		T185	1
all_pins[3]	transitions[0x1=>0x0]	44976	1			T29	3		T34	3		T185	1