Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T29	4		T30	4		T34	4
all_values[1]	269	1			T29	4		T30	4		T34	4
all_values[2]	269	1			T29	4		T30	4		T34	4
all_values[3]	269	1			T29	4		T30	4		T34	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

578

1

T29

11

T30

9

T34

11

auto[1]

498

1

T29

5

T30

7

T34

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

420

1

T29

8

T30

7

T34

5

auto[1]

656

1

T29

8

T30

9

T34

11

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

635

1

T29

9

T30

10

T34

8

auto[1]

441

1

T29

7

T30

6

T34

8

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

58

1

T29

3

T30

3

T34

2

all_values[0]

auto[0]

auto[0]

auto[1]

29

1

T185

3

T120

1

T223

1

all_values[0]

auto[0]

auto[1]

auto[0]

49

1

T120

1

T334

1

T335

2

all_values[0]

auto[0]

auto[1]

auto[1]

28

1

T120

1

T223

1

T333

1

all_values[0]

auto[1]

auto[0]

auto[1]

43

1

T29

1

T30

1

T34

1

all_values[0]

auto[1]

auto[1]

auto[1]

62

1

T34

1

T223

1

T224

1

all_values[1]

auto[0]

auto[0]

auto[0]

58

1

T29

2

T30

1

T185

1

all_values[1]

auto[0]

auto[0]

auto[1]

27

1

T34

2

T120

1

T224

1

all_values[1]

auto[0]

auto[1]

auto[0]

43

1

T30

1

T335

1

T336

1

all_values[1]

auto[0]

auto[1]

auto[1]

28

1

T185

1

T223

1

T333

1

all_values[1]

auto[1]

auto[0]

auto[1]

75

1

T29

2

T34

1

T185

2

all_values[1]

auto[1]

auto[1]

auto[1]

38

1

T30

2

T34

1

T120

1

all_values[2]

auto[0]

auto[0]

auto[0]

62

1

T30

2

T34

1

T185

1

all_values[2]

auto[0]

auto[0]

auto[1]

28

1

T30

1

T333

1

T334

1

all_values[2]

auto[0]

auto[1]

auto[0]

40

1

T120

3

T224

2

T333

1

all_values[2]

auto[0]

auto[1]

auto[1]

29

1

T29

1

T34

1

T334

1

all_values[2]

auto[1]

auto[0]

auto[1]

54

1

T29

1

T333

1

T337

1

all_values[2]

auto[1]

auto[1]

auto[1]

56

1

T29

2

T30

1

T34

2

all_values[3]

auto[0]

auto[0]

auto[0]

61

1

T29

1

T34

2

T120

1

all_values[3]

auto[0]

auto[0]

auto[1]

19

1

T185

1

T120

1

T333

1

all_values[3]

auto[0]

auto[1]

auto[0]

49

1

T29

2

T120

1

T224

2

all_values[3]

auto[0]

auto[1]

auto[1]

27

1

T30

2

T334

2

T335

2

all_values[3]

auto[1]

auto[0]

auto[1]

64

1

T29

1

T30

1

T34

2

all_values[3]

auto[1]

auto[1]

auto[1]

49

1

T30

1

T185

2

T223

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal