Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	102112	1			T2	126		T5	1384		T6	201
accum_cnt_1000	275848	1			T2	451		T21	242		T5	1330
accum_cnt_100	31802	1			T2	259		T21	71		T5	76
accum_cnt_50	69322	1			T2	428		T3	43		T21	82
accum_cnt_10	191434	1			T1	4		T2	312		T3	21
accum_cnt_0	474563	1			T1	12		T2	1132		T3	204

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	298125	1			T1	4		T2	677		T3	67
class_index[0x1]	298125	1			T1	4		T2	677		T3	67
class_index[0x2]	298125	1			T1	4		T2	677		T3	67
class_index[0x3]	298123	1			T1	4		T2	677		T3	67

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	28192	1			T5	459		T6	106		T20	76
class_index[0x0]	accum_cnt_1000	75778	1			T2	262		T5	467		T6	645
class_index[0x0]	accum_cnt_100	7996	1			T2	91		T21	7		T5	26
class_index[0x0]	accum_cnt_50	14836	1			T2	105		T3	43		T21	15
class_index[0x0]	accum_cnt_10	50015	1			T1	2		T2	71		T3	21
class_index[0x0]	accum_cnt_0	102330	1			T1	2		T2	148		T3	3
class_index[0x1]	accum_cnt_2000	21968	1			T5	483		T6	95		T17	358
class_index[0x1]	accum_cnt_1000	65218	1			T2	12		T21	122		T5	446
class_index[0x1]	accum_cnt_100	7886	1			T2	22		T21	28		T5	26
class_index[0x1]	accum_cnt_50	22378	1			T2	182		T21	33		T5	21
class_index[0x1]	accum_cnt_10	47370	1			T1	2		T2	107		T21	19
class_index[0x1]	accum_cnt_0	123194	1			T1	2		T2	354		T3	67
class_index[0x2]	accum_cnt_2000	28595	1			T2	126		T16	250		T55	713
class_index[0x2]	accum_cnt_1000	75108	1			T2	86		T21	120		T16	534
class_index[0x2]	accum_cnt_100	9339	1			T2	73		T21	36		T16	28
class_index[0x2]	accum_cnt_50	19306	1			T2	75		T21	34		T16	16
class_index[0x2]	accum_cnt_10	43968	1			T2	20		T21	28		T6	817
class_index[0x2]	accum_cnt_0	110942	1			T1	4		T2	297		T3	67
class_index[0x3]	accum_cnt_2000	23357	1			T5	442		T17	78		T55	271
class_index[0x3]	accum_cnt_1000	59744	1			T2	91		T5	417		T17	720
class_index[0x3]	accum_cnt_100	6581	1			T2	73		T5	24		T17	79
class_index[0x3]	accum_cnt_50	12802	1			T2	66		T5	18		T25	4
class_index[0x3]	accum_cnt_10	50081	1			T2	114		T21	209		T5	12
class_index[0x3]	accum_cnt_0	138097	1			T1	4		T2	333		T3	67