Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	6168	1			T2	577		T21	29		T19	9
alert[0x1]	13570	1			T2	1		T21	57		T36	1
alert[0x2]	10584	1			T53	1		T20	30		T10	1
alert[0x3]	3507	1			T19	2		T8	1		T56	109
alert[0x4]	8714	1			T2	2		T52	1		T38	70
alert[0x5]	10717	1			T2	3		T19	7		T10	1
alert[0x6]	5193	1			T2	15		T55	5		T56	121
alert[0x7]	7876	1			T19	1		T208	1		T38	1093
alert[0x8]	3060	1			T2	8		T19	5		T56	6
alert[0x9]	12625	1			T2	6		T53	3		T58	14
alert[0xa]	12442	1			T2	36		T22	3		T17	10
alert[0xb]	2729	1			T36	5		T38	9		T58	38
alert[0xc]	5927	1			T20	10		T10	1		T208	1
alert[0xd]	15216	1			T17	1		T53	4		T20	4
alert[0xe]	6877	1			T53	1		T19	4		T20	12
alert[0xf]	9117	1			T17	11		T52	1		T19	3
alert[0x10]	3328	1			T8	1		T56	16		T10	1
alert[0x11]	3754	1			T2	1		T17	10		T53	2
alert[0x12]	5121	1			T36	2		T52	2		T56	6
alert[0x13]	4722	1			T21	1		T7	2		T38	128
alert[0x14]	3483	1			T17	1		T208	1		T38	18
alert[0x15]	11052	1			T21	4		T7	2		T36	2
alert[0x16]	5222	1			T2	132		T208	2		T38	131
alert[0x17]	10631	1			T2	3		T19	1		T8	1
alert[0x18]	10737	1			T2	10		T39	2		T97	1838
alert[0x19]	4787	1			T19	833		T38	1		T58	1
alert[0x1a]	4241	1			T19	6		T56	143		T38	10
alert[0x1b]	7034	1			T2	36		T36	13		T17	6
alert[0x1c]	12290	1			T2	3		T17	1		T53	22
alert[0x1d]	6828	1			T53	20		T38	11		T109	1
alert[0x1e]	5861	1			T56	2107		T10	1		T38	151
alert[0x1f]	4457	1			T38	8		T58	175		T267	18
alert[0x20]	6064	1			T2	4		T17	2		T8	1
alert[0x21]	5016	1			T2	22		T21	9		T10	1
alert[0x22]	5991	1			T8	1		T9	1		T59	3
alert[0x23]	7049	1			T2	34		T17	1		T20	9
alert[0x24]	4157	1			T21	4		T53	14		T19	17
alert[0x25]	7007	1			T2	6		T56	121		T208	2
alert[0x26]	6660	1			T2	1		T21	14		T36	2
alert[0x27]	8775	1			T20	17		T56	439		T208	1
alert[0x28]	11772	1			T2	2		T17	2		T8	1
alert[0x29]	7759	1			T2	210		T19	5		T56	374
alert[0x2a]	4541	1			T2	40		T21	34		T53	1
alert[0x2b]	6979	1			T21	11		T17	5		T19	51
alert[0x2c]	7373	1			T17	16		T19	20		T56	103
alert[0x2d]	3318	1			T19	3		T39	2		T37	1
alert[0x2e]	2913	1			T2	17		T19	49		T8	1
alert[0x2f]	12288	1			T2	48		T21	6		T17	94
alert[0x30]	8975	1			T21	148		T55	3		T56	767
alert[0x31]	7820	1			T53	2		T19	4		T55	5
alert[0x32]	12125	1			T17	13		T19	6		T56	12
alert[0x33]	6675	1			T2	277		T8	1		T56	11
alert[0x34]	6962	1			T2	12		T53	3		T10	1
alert[0x35]	3095	1			T21	3		T36	1		T10	2
alert[0x36]	10143	1			T17	2		T58	47		T48	58
alert[0x37]	13337	1			T2	6		T21	1		T56	49
alert[0x38]	3608	1			T17	1		T53	10		T19	6
alert[0x39]	6700	1			T17	8		T19	37		T56	373
alert[0x3a]	9142	1			T2	4		T53	1		T56	62
alert[0x3b]	3693	1			T2	8		T21	9		T36	1
alert[0x3c]	3001	1			T17	19		T8	1		T58	134
alert[0x3d]	6426	1			T2	100		T56	162		T48	10
alert[0x3e]	9814	1			T21	4		T55	4		T56	169
alert[0x3f]	7481	1			T36	7		T17	2		T10	2
alert[0x40]	11684	1			T17	21		T20	25		T39	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	175856	1			T2	1188		T36	1		T17	161
class_i[0x1]	95239	1			T2	421		T22	3		T7	4
class_i[0x2]	100171	1			T2	15		T36	3		T17	15
class_i[0x3]	104947	1			T21	334		T17	5		T53	14

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

475519

1

T2

1624

T21

334

T22

3

alert_ping_fail

694

1

T7

4

T8

10

T9

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	6157	1			T2	577		T21	29		T19	9
alert_integrity_fail	alert[0x1]	13560	1			T2	1		T21	57		T36	1
alert_integrity_fail	alert[0x2]	10574	1			T53	1		T20	30		T58	53
alert_integrity_fail	alert[0x3]	3495	1			T19	2		T56	109		T38	139
alert_integrity_fail	alert[0x4]	8706	1			T2	2		T52	1		T38	70
alert_integrity_fail	alert[0x5]	10701	1			T2	3		T19	7		T58	398
alert_integrity_fail	alert[0x6]	5173	1			T2	15		T55	5		T56	121
alert_integrity_fail	alert[0x7]	7865	1			T19	1		T38	1093		T58	1
alert_integrity_fail	alert[0x8]	3048	1			T2	8		T19	5		T56	6
alert_integrity_fail	alert[0x9]	12619	1			T2	6		T53	3		T58	14
alert_integrity_fail	alert[0xa]	12432	1			T2	36		T22	3		T17	10
alert_integrity_fail	alert[0xb]	2717	1			T36	5		T38	9		T58	38
alert_integrity_fail	alert[0xc]	5916	1			T20	10		T47	115		T48	54
alert_integrity_fail	alert[0xd]	15203	1			T17	1		T53	4		T20	4
alert_integrity_fail	alert[0xe]	6865	1			T53	1		T19	4		T20	12
alert_integrity_fail	alert[0xf]	9106	1			T17	11		T52	1		T19	3
alert_integrity_fail	alert[0x10]	3319	1			T56	16		T58	131		T48	59
alert_integrity_fail	alert[0x11]	3741	1			T2	1		T17	10		T53	2
alert_integrity_fail	alert[0x12]	5104	1			T36	2		T52	2		T56	6
alert_integrity_fail	alert[0x13]	4704	1			T21	1		T38	128		T58	37
alert_integrity_fail	alert[0x14]	3471	1			T17	1		T38	18		T58	19
alert_integrity_fail	alert[0x15]	11039	1			T21	4		T36	2		T53	1
alert_integrity_fail	alert[0x16]	5209	1			T2	132		T38	131		T58	8
alert_integrity_fail	alert[0x17]	10623	1			T2	3		T19	1		T55	4
alert_integrity_fail	alert[0x18]	10727	1			T2	10		T39	2		T97	1838
alert_integrity_fail	alert[0x19]	4778	1			T19	833		T38	1		T58	1
alert_integrity_fail	alert[0x1a]	4230	1			T19	6		T56	143		T38	10
alert_integrity_fail	alert[0x1b]	7027	1			T2	36		T36	13		T17	6
alert_integrity_fail	alert[0x1c]	12285	1			T2	3		T17	1		T53	22
alert_integrity_fail	alert[0x1d]	6821	1			T53	20		T38	11		T109	1
alert_integrity_fail	alert[0x1e]	5848	1			T56	2107		T38	151		T58	272
alert_integrity_fail	alert[0x1f]	4439	1			T38	8		T58	175		T267	18
alert_integrity_fail	alert[0x20]	6056	1			T2	4		T17	2		T267	518
alert_integrity_fail	alert[0x21]	5008	1			T2	22		T21	9		T38	40
alert_integrity_fail	alert[0x22]	5972	1			T59	3		T47	197		T48	25
alert_integrity_fail	alert[0x23]	7044	1			T2	34		T17	1		T20	9
alert_integrity_fail	alert[0x24]	4149	1			T21	4		T53	14		T19	17
alert_integrity_fail	alert[0x25]	6990	1			T2	6		T56	121		T47	31
alert_integrity_fail	alert[0x26]	6651	1			T2	1		T21	14		T36	2
alert_integrity_fail	alert[0x27]	8768	1			T20	17		T56	439		T58	155
alert_integrity_fail	alert[0x28]	11753	1			T2	2		T17	2		T56	37
alert_integrity_fail	alert[0x29]	7755	1			T2	210		T19	5		T56	374
alert_integrity_fail	alert[0x2a]	4534	1			T2	40		T21	34		T53	1
alert_integrity_fail	alert[0x2b]	6967	1			T21	11		T17	5		T19	51
alert_integrity_fail	alert[0x2c]	7364	1			T17	16		T19	20		T56	103
alert_integrity_fail	alert[0x2d]	3307	1			T19	3		T39	2		T37	1
alert_integrity_fail	alert[0x2e]	2905	1			T2	17		T19	49		T47	5
alert_integrity_fail	alert[0x2f]	12273	1			T2	48		T21	6		T17	94
alert_integrity_fail	alert[0x30]	8957	1			T21	148		T55	3		T56	767
alert_integrity_fail	alert[0x31]	7807	1			T53	2		T19	4		T55	5
alert_integrity_fail	alert[0x32]	12115	1			T17	13		T19	6		T56	12
alert_integrity_fail	alert[0x33]	6668	1			T2	277		T56	11		T48	7
alert_integrity_fail	alert[0x34]	6952	1			T2	12		T53	3		T48	37
alert_integrity_fail	alert[0x35]	3086	1			T21	3		T36	1		T38	4
alert_integrity_fail	alert[0x36]	10135	1			T17	2		T58	47		T48	58
alert_integrity_fail	alert[0x37]	13324	1			T2	6		T21	1		T56	49
alert_integrity_fail	alert[0x38]	3596	1			T17	1		T53	10		T19	6
alert_integrity_fail	alert[0x39]	6690	1			T17	8		T19	37		T56	373
alert_integrity_fail	alert[0x3a]	9132	1			T2	4		T53	1		T56	62
alert_integrity_fail	alert[0x3b]	3687	1			T2	8		T21	9		T36	1
alert_integrity_fail	alert[0x3c]	2995	1			T17	19		T58	134		T48	103
alert_integrity_fail	alert[0x3d]	6417	1			T2	100		T56	162		T48	10
alert_integrity_fail	alert[0x3e]	9804	1			T21	4		T55	4		T56	169
alert_integrity_fail	alert[0x3f]	7475	1			T36	7		T17	2		T58	46
alert_integrity_fail	alert[0x40]	11681	1			T17	21		T20	25		T39	1
alert_ping_fail	alert[0x0]	11	1			T279	1		T280	1		T281	1
alert_ping_fail	alert[0x1]	10	1			T282	1		T283	2		T284	1
alert_ping_fail	alert[0x2]	10	1			T10	1		T208	2		T280	1
alert_ping_fail	alert[0x3]	12	1			T8	1		T285	1		T286	1
alert_ping_fail	alert[0x4]	8	1			T287	1		T288	1		T289	1
alert_ping_fail	alert[0x5]	16	1			T10	1		T290	1		T102	1
alert_ping_fail	alert[0x6]	20	1			T291	1		T292	1		T293	1
alert_ping_fail	alert[0x7]	11	1			T208	1		T279	1		T294	1
alert_ping_fail	alert[0x8]	12	1			T10	1		T292	1		T280	1
alert_ping_fail	alert[0x9]	6	1			T285	1		T286	1		T295	1
alert_ping_fail	alert[0xa]	10	1			T292	1		T286	2		T284	1
alert_ping_fail	alert[0xb]	12	1			T291	1		T286	1		T288	2
alert_ping_fail	alert[0xc]	11	1			T10	1		T208	1		T296	1
alert_ping_fail	alert[0xd]	13	1			T292	1		T297	1		T280	1
alert_ping_fail	alert[0xe]	12	1			T290	1		T285	1		T298	2
alert_ping_fail	alert[0xf]	11	1			T10	1		T11	1		T292	1
alert_ping_fail	alert[0x10]	9	1			T8	1		T10	1		T285	1
alert_ping_fail	alert[0x11]	13	1			T11	2		T208	1		T296	1
alert_ping_fail	alert[0x12]	17	1			T279	1		T297	1		T299	1
alert_ping_fail	alert[0x13]	18	1			T7	2		T285	1		T298	1
alert_ping_fail	alert[0x14]	12	1			T208	1		T278	2		T294	1
alert_ping_fail	alert[0x15]	13	1			T7	2		T297	1		T298	1
alert_ping_fail	alert[0x16]	13	1			T208	2		T297	1		T300	1
alert_ping_fail	alert[0x17]	8	1			T8	1		T208	1		T300	1
alert_ping_fail	alert[0x18]	10	1			T291	1		T292	1		T289	1
alert_ping_fail	alert[0x19]	9	1			T298	1		T286	1		T284	1
alert_ping_fail	alert[0x1a]	11	1			T287	1		T301	1		T288	1
alert_ping_fail	alert[0x1b]	7	1			T280	1		T286	1		T302	1
alert_ping_fail	alert[0x1c]	5	1			T8	1		T10	1		T278	1
alert_ping_fail	alert[0x1d]	7	1			T286	1		T287	1		T302	1
alert_ping_fail	alert[0x1e]	13	1			T10	1		T279	1		T292	1
alert_ping_fail	alert[0x1f]	18	1			T279	1		T280	1		T303	1
alert_ping_fail	alert[0x20]	8	1			T8	1		T304	1		T287	1
alert_ping_fail	alert[0x21]	8	1			T10	1		T286	1		T282	1
alert_ping_fail	alert[0x22]	19	1			T8	1		T9	1		T291	1
alert_ping_fail	alert[0x23]	5	1			T282	1		T305	1		T306	1
alert_ping_fail	alert[0x24]	8	1			T10	1		T291	1		T292	1
alert_ping_fail	alert[0x25]	17	1			T208	2		T300	1		T283	1
alert_ping_fail	alert[0x26]	9	1			T291	1		T299	1		T280	1
alert_ping_fail	alert[0x27]	7	1			T208	1		T285	1		T283	1
alert_ping_fail	alert[0x28]	19	1			T8	1		T292	2		T293	1
alert_ping_fail	alert[0x29]	4	1			T307	1		T308	1		T309	1
alert_ping_fail	alert[0x2a]	7	1			T310	1		T283	1		T311	1
alert_ping_fail	alert[0x2b]	12	1			T208	1		T276	1		T278	1
alert_ping_fail	alert[0x2c]	9	1			T10	1		T208	1		T292	1
alert_ping_fail	alert[0x2d]	11	1			T291	1		T300	1		T312	1
alert_ping_fail	alert[0x2e]	8	1			T8	1		T282	1		T284	1
alert_ping_fail	alert[0x2f]	15	1			T11	1		T292	1		T285	2
alert_ping_fail	alert[0x30]	18	1			T10	3		T208	1		T291	1
alert_ping_fail	alert[0x31]	13	1			T10	1		T208	1		T285	1
alert_ping_fail	alert[0x32]	10	1			T282	1		T287	1		T284	1
alert_ping_fail	alert[0x33]	7	1			T8	1		T279	1		T292	1
alert_ping_fail	alert[0x34]	10	1			T10	1		T279	1		T287	1
alert_ping_fail	alert[0x35]	9	1			T10	2		T298	1		T284	1
alert_ping_fail	alert[0x36]	8	1			T292	1		T282	1		T313	1
alert_ping_fail	alert[0x37]	13	1			T10	1		T208	2		T285	1
alert_ping_fail	alert[0x38]	12	1			T291	1		T296	1		T283	1
alert_ping_fail	alert[0x39]	10	1			T298	1		T300	1		T283	1
alert_ping_fail	alert[0x3a]	10	1			T208	1		T281	1		T313	1
alert_ping_fail	alert[0x3b]	6	1			T279	1		T282	1		T289	1
alert_ping_fail	alert[0x3c]	6	1			T8	1		T313	1		T284	1
alert_ping_fail	alert[0x3d]	9	1			T291	1		T292	1		T298	2
alert_ping_fail	alert[0x3e]	10	1			T291	1		T281	1		T284	1
alert_ping_fail	alert[0x3f]	6	1			T10	2		T279	1		T297	1
alert_ping_fail	alert[0x40]	3	1			T311	1		T289	1		T314	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	175672	1			T2	1188		T36	1		T17	161
alert_integrity_fail	class_i[0x1]	95020	1			T2	421		T22	3		T36	30
alert_integrity_fail	class_i[0x2]	100036	1			T2	15		T36	3		T17	15
alert_integrity_fail	class_i[0x3]	104791	1			T21	334		T17	5		T53	14
alert_ping_fail	class_i[0x0]	184	1			T11	1		T291	11		T279	6
alert_ping_fail	class_i[0x1]	219	1			T7	4		T8	9		T9	1
alert_ping_fail	class_i[0x2]	135	1			T8	1		T10	20		T279	1
alert_ping_fail	class_i[0x3]	156	1			T10	1		T292	3		T285	7