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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.65 100.00 100.00 100.00 99.38 99.60


Total test records in report: 847
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T180 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.312658728 Jan 17 12:41:25 PM PST 24 Jan 17 12:42:33 PM PST 24 881750510 ps
T777 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.394599898 Jan 17 12:42:14 PM PST 24 Jan 17 12:43:12 PM PST 24 3969983984 ps
T778 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2259769258 Jan 17 12:42:08 PM PST 24 Jan 17 12:42:12 PM PST 24 13151751 ps
T779 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.4018380089 Jan 17 12:41:24 PM PST 24 Jan 17 12:41:29 PM PST 24 8544050 ps
T140 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.67006643 Jan 17 12:41:37 PM PST 24 Jan 17 12:47:44 PM PST 24 5535004037 ps
T780 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.4172241469 Jan 17 12:41:46 PM PST 24 Jan 17 12:41:53 PM PST 24 90864821 ps
T781 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2513119879 Jan 17 12:41:19 PM PST 24 Jan 17 12:41:27 PM PST 24 59992548 ps
T782 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.4015714717 Jan 17 12:42:12 PM PST 24 Jan 17 12:42:16 PM PST 24 11603256 ps
T783 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1329625728 Jan 17 12:42:10 PM PST 24 Jan 17 12:42:15 PM PST 24 13114397 ps
T784 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2270756025 Jan 17 12:41:26 PM PST 24 Jan 17 12:41:41 PM PST 24 339477363 ps
T785 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3259777754 Jan 17 12:41:22 PM PST 24 Jan 17 12:45:45 PM PST 24 53356697082 ps
T174 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2221519018 Jan 17 12:41:58 PM PST 24 Jan 17 12:42:03 PM PST 24 65361703 ps
T786 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2299051331 Jan 17 12:41:51 PM PST 24 Jan 17 12:41:56 PM PST 24 37997689 ps
T787 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.296038347 Jan 17 12:42:09 PM PST 24 Jan 17 12:42:20 PM PST 24 286832896 ps
T788 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.590263694 Jan 17 12:41:27 PM PST 24 Jan 17 12:42:06 PM PST 24 490992278 ps
T146 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2605859882 Jan 17 12:41:45 PM PST 24 Jan 17 12:48:09 PM PST 24 5502667325 ps
T789 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.263021366 Jan 17 12:41:54 PM PST 24 Jan 17 12:42:05 PM PST 24 550163558 ps
T790 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.711204429 Jan 17 12:41:32 PM PST 24 Jan 17 12:41:38 PM PST 24 115353913 ps
T791 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2408438915 Jan 17 12:41:33 PM PST 24 Jan 17 12:41:44 PM PST 24 810114737 ps
T792 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1009527496 Jan 17 12:41:58 PM PST 24 Jan 17 12:42:04 PM PST 24 50309983 ps
T793 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1380190341 Jan 17 12:41:51 PM PST 24 Jan 17 12:41:57 PM PST 24 371825693 ps
T158 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1614199504 Jan 17 12:41:50 PM PST 24 Jan 17 12:50:10 PM PST 24 15647573071 ps
T794 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1236611137 Jan 17 12:42:06 PM PST 24 Jan 17 12:42:08 PM PST 24 6462354 ps
T795 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.923780520 Jan 17 12:42:08 PM PST 24 Jan 17 12:42:13 PM PST 24 10823950 ps
T796 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3251410330 Jan 17 12:41:45 PM PST 24 Jan 17 12:41:56 PM PST 24 266702966 ps
T797 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2822674182 Jan 17 12:41:53 PM PST 24 Jan 17 12:41:58 PM PST 24 28643138 ps
T798 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2819398402 Jan 17 12:42:09 PM PST 24 Jan 17 12:42:14 PM PST 24 7500908 ps
T799 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.402920489 Jan 17 12:42:05 PM PST 24 Jan 17 12:42:07 PM PST 24 23185240 ps
T170 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3280055144 Jan 17 12:42:07 PM PST 24 Jan 17 12:42:13 PM PST 24 39445716 ps
T151 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1357464090 Jan 17 12:41:31 PM PST 24 Jan 17 12:58:06 PM PST 24 12773539490 ps
T800 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1898607037 Jan 17 12:41:41 PM PST 24 Jan 17 12:41:55 PM PST 24 59611250 ps
T144 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1932495174 Jan 17 12:41:50 PM PST 24 Jan 17 12:43:53 PM PST 24 1661123453 ps
T154 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3790576436 Jan 17 12:41:37 PM PST 24 Jan 17 12:47:15 PM PST 24 9963825830 ps
T168 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1053194644 Jan 17 12:41:36 PM PST 24 Jan 17 12:41:58 PM PST 24 157391387 ps
T801 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.56867686 Jan 17 12:41:55 PM PST 24 Jan 17 12:42:02 PM PST 24 32374957 ps
T802 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3286049894 Jan 17 12:42:09 PM PST 24 Jan 17 12:42:14 PM PST 24 8691812 ps
T803 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.4015584082 Jan 17 12:41:51 PM PST 24 Jan 17 12:41:54 PM PST 24 12430566 ps
T804 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3119769202 Jan 17 12:42:07 PM PST 24 Jan 17 12:42:11 PM PST 24 10420756 ps
T805 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.722936450 Jan 17 12:41:48 PM PST 24 Jan 17 12:42:02 PM PST 24 85679236 ps
T157 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3191311100 Jan 17 12:41:44 PM PST 24 Jan 17 12:46:40 PM PST 24 16115519771 ps
T806 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1706663274 Jan 17 12:41:52 PM PST 24 Jan 17 12:42:10 PM PST 24 905361046 ps
T807 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2888832846 Jan 17 12:41:51 PM PST 24 Jan 17 12:42:06 PM PST 24 121057638 ps
T808 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2535697267 Jan 17 12:41:36 PM PST 24 Jan 17 12:48:20 PM PST 24 31705932910 ps
T809 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2578566681 Jan 17 12:42:14 PM PST 24 Jan 17 12:42:31 PM PST 24 148877691 ps
T177 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.117459862 Jan 17 12:41:47 PM PST 24 Jan 17 12:42:33 PM PST 24 1352159306 ps
T810 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3263146839 Jan 17 12:41:46 PM PST 24 Jan 17 12:42:01 PM PST 24 169983890 ps
T811 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3560465296 Jan 17 12:41:25 PM PST 24 Jan 17 12:41:34 PM PST 24 126811157 ps
T812 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3743573246 Jan 17 12:41:54 PM PST 24 Jan 17 12:41:57 PM PST 24 9274512 ps
T162 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3199763735 Jan 17 12:41:54 PM PST 24 Jan 17 01:00:06 PM PST 24 15876085456 ps
T813 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1696343625 Jan 17 12:41:44 PM PST 24 Jan 17 12:41:58 PM PST 24 991501182 ps
T814 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.4026730073 Jan 17 12:42:11 PM PST 24 Jan 17 12:42:21 PM PST 24 184472989 ps
T815 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.661886869 Jan 17 12:41:51 PM PST 24 Jan 17 12:42:11 PM PST 24 1154902601 ps
T816 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1795918111 Jan 17 12:41:25 PM PST 24 Jan 17 12:41:33 PM PST 24 966230595 ps
T817 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.434822406 Jan 17 12:41:20 PM PST 24 Jan 17 12:41:23 PM PST 24 181403032 ps
T818 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2541740958 Jan 17 12:41:41 PM PST 24 Jan 17 12:41:53 PM PST 24 102946819 ps
T819 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1883737677 Jan 17 12:41:51 PM PST 24 Jan 17 12:41:53 PM PST 24 27905409 ps
T820 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2024457711 Jan 17 12:41:53 PM PST 24 Jan 17 12:43:38 PM PST 24 6019952075 ps
T821 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.344245788 Jan 17 12:42:10 PM PST 24 Jan 17 12:42:14 PM PST 24 10175932 ps
T338 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2444235106 Jan 17 12:41:41 PM PST 24 Jan 17 12:46:36 PM PST 24 2224774310 ps
T822 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.924257427 Jan 17 12:42:07 PM PST 24 Jan 17 12:42:20 PM PST 24 920387885 ps
T160 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3077202970 Jan 17 12:41:53 PM PST 24 Jan 17 12:43:17 PM PST 24 3197787981 ps
T823 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3327981780 Jan 17 12:41:29 PM PST 24 Jan 17 12:41:42 PM PST 24 363230188 ps
T149 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1722543990 Jan 17 12:41:37 PM PST 24 Jan 17 12:51:23 PM PST 24 4460740215 ps
T824 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1259517236 Jan 17 12:42:01 PM PST 24 Jan 17 12:42:03 PM PST 24 15411885 ps
T825 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1636076797 Jan 17 12:42:05 PM PST 24 Jan 17 12:42:10 PM PST 24 25231298 ps
T826 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2316045981 Jan 17 12:42:05 PM PST 24 Jan 17 12:42:10 PM PST 24 101278934 ps
T169 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2735574055 Jan 17 12:41:51 PM PST 24 Jan 17 12:41:55 PM PST 24 113523214 ps
T827 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.117722626 Jan 17 12:41:52 PM PST 24 Jan 17 12:41:54 PM PST 24 7091917 ps
T159 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.964229315 Jan 17 12:41:32 PM PST 24 Jan 17 12:49:34 PM PST 24 7555709952 ps
T828 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2779961432 Jan 17 12:41:49 PM PST 24 Jan 17 12:42:10 PM PST 24 676561906 ps
T829 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1654086344 Jan 17 12:41:46 PM PST 24 Jan 17 12:41:54 PM PST 24 33821279 ps
T155 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2292455631 Jan 17 12:41:20 PM PST 24 Jan 17 12:50:05 PM PST 24 8354821524 ps
T830 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2795310565 Jan 17 12:42:07 PM PST 24 Jan 17 12:42:11 PM PST 24 22765349 ps
T831 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.937541476 Jan 17 12:41:54 PM PST 24 Jan 17 12:42:05 PM PST 24 204846351 ps
T152 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.724461946 Jan 17 12:42:02 PM PST 24 Jan 17 12:45:04 PM PST 24 1547645594 ps
T832 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3060997510 Jan 17 12:41:27 PM PST 24 Jan 17 12:41:38 PM PST 24 480131444 ps
T833 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3040436186 Jan 17 12:41:56 PM PST 24 Jan 17 12:42:01 PM PST 24 41536812 ps
T834 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1309233722 Jan 17 12:41:44 PM PST 24 Jan 17 12:41:56 PM PST 24 144844037 ps
T835 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1839997445 Jan 17 12:42:11 PM PST 24 Jan 17 12:42:15 PM PST 24 21213933 ps
T836 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3628974682 Jan 17 12:42:04 PM PST 24 Jan 17 12:42:16 PM PST 24 336986632 ps
T172 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1089316981 Jan 17 12:41:53 PM PST 24 Jan 17 12:43:01 PM PST 24 1870872585 ps
T173 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1461257079 Jan 17 12:41:50 PM PST 24 Jan 17 12:41:56 PM PST 24 225334031 ps
T837 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1707948074 Jan 17 12:41:52 PM PST 24 Jan 17 12:41:55 PM PST 24 21533372 ps
T838 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3196191684 Jan 17 12:41:58 PM PST 24 Jan 17 12:42:22 PM PST 24 650288464 ps
T839 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4188153158 Jan 17 12:42:09 PM PST 24 Jan 17 12:42:27 PM PST 24 217794624 ps
T156 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3892406607 Jan 17 12:41:49 PM PST 24 Jan 17 12:59:39 PM PST 24 16185447887 ps
T171 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2121084375 Jan 17 12:41:37 PM PST 24 Jan 17 12:42:15 PM PST 24 464953666 ps
T840 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.711133692 Jan 17 12:41:35 PM PST 24 Jan 17 12:42:17 PM PST 24 2453805280 ps
T841 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1815198728 Jan 17 12:41:53 PM PST 24 Jan 17 12:41:55 PM PST 24 6296527 ps
T842 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.4210477686 Jan 17 12:41:56 PM PST 24 Jan 17 12:42:02 PM PST 24 102637742 ps
T843 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2588728160 Jan 17 12:41:21 PM PST 24 Jan 17 12:42:10 PM PST 24 3977132879 ps
T844 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1910573412 Jan 17 12:41:44 PM PST 24 Jan 17 12:41:56 PM PST 24 271999834 ps
T845 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3500396511 Jan 17 12:41:18 PM PST 24 Jan 17 12:41:26 PM PST 24 180884788 ps
T846 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.307055088 Jan 17 12:41:51 PM PST 24 Jan 17 12:42:15 PM PST 24 1932451629 ps
T161 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3941755001 Jan 17 12:41:55 PM PST 24 Jan 17 12:47:32 PM PST 24 4901556658 ps
T847 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1101359637 Jan 17 12:42:10 PM PST 24 Jan 17 12:42:15 PM PST 24 11968246 ps
T181 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2630520996 Jan 17 12:42:06 PM PST 24 Jan 17 12:42:09 PM PST 24 115512119 ps

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.22671611
Short name T15
Test name
Test status
Simulation time 85775485 ps
CPU time 13.47 seconds
Started Jan 17 12:41:40 PM PST 24
Finished Jan 17 12:41:54 PM PST 24
Peak memory 240316 kb
Host smart-967e06af-b699-4f24-b70c-a3a3cc58fe89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=22671611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outst
anding.22671611
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3391499795
Short name T2
Test name
Test status
Simulation time 52100415773 ps
CPU time 3387.36 seconds
Started Jan 17 02:49:34 PM PST 24
Finished Jan 17 03:46:07 PM PST 24
Peak memory 286216 kb
Host smart-6a97bfb2-7280-41cf-b6ef-d537b5e4713c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391499795 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3391499795
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1033458109
Short name T33
Test name
Test status
Simulation time 305862857 ps
CPU time 23.46 seconds
Started Jan 17 12:41:22 PM PST 24
Finished Jan 17 12:41:46 PM PST 24
Peak memory 244816 kb
Host smart-9005d223-74ef-47bb-b551-4a45bdae5589
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1033458109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1033458109
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.26477450
Short name T13
Test name
Test status
Simulation time 1254802636 ps
CPU time 26.09 seconds
Started Jan 17 02:48:50 PM PST 24
Finished Jan 17 02:49:16 PM PST 24
Peak memory 269988 kb
Host smart-8cec03da-ac27-4ab9-b711-7efd0637a2be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=26477450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.26477450
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1102805925
Short name T47
Test name
Test status
Simulation time 31085614950 ps
CPU time 2075.87 seconds
Started Jan 17 02:56:50 PM PST 24
Finished Jan 17 03:31:27 PM PST 24
Peak memory 281580 kb
Host smart-8dd386e1-069b-4023-a1dd-3d4d4e65c664
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102805925 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1102805925
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3173689564
Short name T4
Test name
Test status
Simulation time 239296677 ps
CPU time 8.43 seconds
Started Jan 17 02:52:09 PM PST 24
Finished Jan 17 02:52:19 PM PST 24
Peak memory 240468 kb
Host smart-5497da31-74a0-4026-b6fd-cbcf6738e2b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3173689564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3173689564
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3636089518
Short name T125
Test name
Test status
Simulation time 17614579180 ps
CPU time 1087.44 seconds
Started Jan 17 12:42:14 PM PST 24
Finished Jan 17 01:00:32 PM PST 24
Peak memory 265432 kb
Host smart-67c91e58-63e2-4a3b-a056-1849c88269e6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636089518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3636089518
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1500831267
Short name T7
Test name
Test status
Simulation time 40765552977 ps
CPU time 2255.43 seconds
Started Jan 17 02:53:56 PM PST 24
Finished Jan 17 03:31:33 PM PST 24
Peak memory 281508 kb
Host smart-17f5f12d-a9a9-49bc-8f4a-0a38c4c5b25e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500831267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1500831267
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3116670714
Short name T136
Test name
Test status
Simulation time 3295013672 ps
CPU time 173.05 seconds
Started Jan 17 12:41:53 PM PST 24
Finished Jan 17 12:44:48 PM PST 24
Peak memory 270424 kb
Host smart-17e6166b-688b-46c4-b5eb-ec73281a9e0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3116670714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3116670714
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1759365602
Short name T19
Test name
Test status
Simulation time 43773896261 ps
CPU time 1506.43 seconds
Started Jan 17 02:59:06 PM PST 24
Finished Jan 17 03:24:15 PM PST 24
Peak memory 286052 kb
Host smart-e3333ac1-ed69-4f16-80b0-f8be2e356ccf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759365602 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1759365602
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.776378666
Short name T333
Test name
Test status
Simulation time 13950304 ps
CPU time 1.57 seconds
Started Jan 17 12:42:03 PM PST 24
Finished Jan 17 12:42:05 PM PST 24
Peak memory 235548 kb
Host smart-d163a1e0-5ca8-4e66-8cd6-871a019044e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=776378666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.776378666
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1140586357
Short name T126
Test name
Test status
Simulation time 16965927045 ps
CPU time 304.6 seconds
Started Jan 17 12:42:07 PM PST 24
Finished Jan 17 12:47:14 PM PST 24
Peak memory 273360 kb
Host smart-7bb1a541-8053-44d9-a004-770a8e52fb4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1140586357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1140586357
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.650190493
Short name T133
Test name
Test status
Simulation time 19487823236 ps
CPU time 578.03 seconds
Started Jan 17 12:41:43 PM PST 24
Finished Jan 17 12:51:27 PM PST 24
Peak memory 265260 kb
Host smart-a0e507a9-a822-4af3-b6bf-c7ec918375ce
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650190493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.650190493
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2555736654
Short name T290
Test name
Test status
Simulation time 33180462937 ps
CPU time 2195.3 seconds
Started Jan 17 02:53:19 PM PST 24
Finished Jan 17 03:29:57 PM PST 24
Peak memory 286300 kb
Host smart-1a0b288d-71e0-41f3-90ae-dfdf3e6e949a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555736654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2555736654
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.3319745140
Short name T58
Test name
Test status
Simulation time 212004155255 ps
CPU time 6378.77 seconds
Started Jan 17 02:54:29 PM PST 24
Finished Jan 17 04:40:50 PM PST 24
Peak memory 354680 kb
Host smart-eb177775-4b7b-49a9-98d1-371f709e185d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319745140 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.3319745140
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2764146233
Short name T292
Test name
Test status
Simulation time 9781847370 ps
CPU time 390.13 seconds
Started Jan 17 02:53:57 PM PST 24
Finished Jan 17 03:00:27 PM PST 24
Peak memory 248692 kb
Host smart-8755f21e-3373-41b1-8100-0ed34d0c717d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764146233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2764146233
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3161413612
Short name T137
Test name
Test status
Simulation time 16364142288 ps
CPU time 1148.99 seconds
Started Jan 17 12:41:28 PM PST 24
Finished Jan 17 01:00:39 PM PST 24
Peak memory 265312 kb
Host smart-fd13762f-6519-4b63-bea2-b948589396f6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161413612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3161413612
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.386254305
Short name T278
Test name
Test status
Simulation time 202957614242 ps
CPU time 2956.97 seconds
Started Jan 17 02:56:21 PM PST 24
Finished Jan 17 03:45:39 PM PST 24
Peak memory 289088 kb
Host smart-52739b52-b87a-454e-ae28-59694591beb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386254305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.386254305
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.4037237305
Short name T38
Test name
Test status
Simulation time 412866773601 ps
CPU time 6617.83 seconds
Started Jan 17 02:54:19 PM PST 24
Finished Jan 17 04:44:38 PM PST 24
Peak memory 371848 kb
Host smart-9fda75b7-f551-4a1d-9a51-c16c7ee8140a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037237305 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.4037237305
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3790576436
Short name T154
Test name
Test status
Simulation time 9963825830 ps
CPU time 335.69 seconds
Started Jan 17 12:41:37 PM PST 24
Finished Jan 17 12:47:15 PM PST 24
Peak memory 270508 kb
Host smart-a3d77ab6-0007-4dda-87be-4393bc773855
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3790576436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3790576436
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4263977440
Short name T135
Test name
Test status
Simulation time 17935250965 ps
CPU time 689.19 seconds
Started Jan 17 12:41:47 PM PST 24
Finished Jan 17 12:53:18 PM PST 24
Peak memory 265404 kb
Host smart-eebe6bd2-cb42-44dd-804b-3f0cc8e0bd7f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263977440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.4263977440
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3168115548
Short name T288
Test name
Test status
Simulation time 14794749469 ps
CPU time 613.48 seconds
Started Jan 17 02:51:02 PM PST 24
Finished Jan 17 03:01:17 PM PST 24
Peak memory 247604 kb
Host smart-180736d3-b8f3-44a2-863d-6952077ffee7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168115548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3168115548
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3484069204
Short name T316
Test name
Test status
Simulation time 67383712730 ps
CPU time 2285.38 seconds
Started Jan 17 02:54:30 PM PST 24
Finished Jan 17 03:32:36 PM PST 24
Peak memory 273176 kb
Host smart-7f720735-22d2-492b-ae18-1a1c3e11610e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484069204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3484069204
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.4268463975
Short name T97
Test name
Test status
Simulation time 625529880326 ps
CPU time 1958.02 seconds
Started Jan 17 02:55:47 PM PST 24
Finished Jan 17 03:28:26 PM PST 24
Peak memory 281548 kb
Host smart-7f584aa4-19a2-418b-a960-57bea3535683
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268463975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.4268463975
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2336908798
Short name T167
Test name
Test status
Simulation time 1414125434 ps
CPU time 78.16 seconds
Started Jan 17 12:41:46 PM PST 24
Finished Jan 17 12:43:07 PM PST 24
Peak memory 240608 kb
Host smart-5f527ef5-c49a-4253-95fd-071b1cebdc43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2336908798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2336908798
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2072419585
Short name T244
Test name
Test status
Simulation time 35928240386 ps
CPU time 488 seconds
Started Jan 17 02:48:42 PM PST 24
Finished Jan 17 02:56:54 PM PST 24
Peak memory 256920 kb
Host smart-ec4fc980-3747-4a37-8465-64daf470a719
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072419585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2072419585
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1730465260
Short name T111
Test name
Test status
Simulation time 183115443868 ps
CPU time 2952.16 seconds
Started Jan 17 02:50:08 PM PST 24
Finished Jan 17 03:39:21 PM PST 24
Peak memory 288132 kb
Host smart-c62c719c-b696-4c04-877b-081a27849f40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730465260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1730465260
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2279759340
Short name T208
Test name
Test status
Simulation time 13066582671 ps
CPU time 532.11 seconds
Started Jan 17 02:52:20 PM PST 24
Finished Jan 17 03:01:12 PM PST 24
Peak memory 248704 kb
Host smart-b97fbf77-e10b-41f4-a9d0-ac5956c869ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279759340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2279759340
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2160613894
Short name T145
Test name
Test status
Simulation time 37758375897 ps
CPU time 543.45 seconds
Started Jan 17 12:41:55 PM PST 24
Finished Jan 17 12:51:00 PM PST 24
Peak memory 265092 kb
Host smart-68fd3db2-dea7-4cf9-b4f7-00568b40133a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160613894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2160613894
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.4010846103
Short name T286
Test name
Test status
Simulation time 74858133961 ps
CPU time 515.67 seconds
Started Jan 17 02:48:36 PM PST 24
Finished Jan 17 02:57:13 PM PST 24
Peak memory 247608 kb
Host smart-c5d0238f-6ab2-4123-b519-5de33b647100
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010846103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.4010846103
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2595191265
Short name T17
Test name
Test status
Simulation time 158613277198 ps
CPU time 4313.95 seconds
Started Jan 17 02:50:11 PM PST 24
Finished Jan 17 04:02:06 PM PST 24
Peak memory 354424 kb
Host smart-4ca09621-9c8e-4882-a5a4-86ef7c9c6f7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595191265 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2595191265
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3882010255
Short name T9
Test name
Test status
Simulation time 648911365045 ps
CPU time 1875.38 seconds
Started Jan 17 02:48:50 PM PST 24
Finished Jan 17 03:20:06 PM PST 24
Peak memory 272572 kb
Host smart-ba796b52-407d-408c-8aa8-17b18c8a9cc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882010255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3882010255
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1300320484
Short name T250
Test name
Test status
Simulation time 302538059359 ps
CPU time 4389.63 seconds
Started Jan 17 02:47:59 PM PST 24
Finished Jan 17 04:01:09 PM PST 24
Peak memory 306056 kb
Host smart-e398fab3-a9c2-465e-9e63-53742235c21e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300320484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1300320484
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2797342316
Short name T305
Test name
Test status
Simulation time 29662019626 ps
CPU time 512.6 seconds
Started Jan 17 02:50:16 PM PST 24
Finished Jan 17 02:58:49 PM PST 24
Peak memory 247616 kb
Host smart-45be44d2-1894-4847-992e-6409d994a1dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797342316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2797342316
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.438215644
Short name T262
Test name
Test status
Simulation time 786336510776 ps
CPU time 5974.37 seconds
Started Jan 17 02:54:45 PM PST 24
Finished Jan 17 04:34:20 PM PST 24
Peak memory 322512 kb
Host smart-7d21d88e-7d89-4ef4-aa10-8740fcfa4961
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438215644 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.438215644
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1318048976
Short name T30
Test name
Test status
Simulation time 7028883 ps
CPU time 1.4 seconds
Started Jan 17 12:42:11 PM PST 24
Finished Jan 17 12:42:15 PM PST 24
Peak memory 235568 kb
Host smart-dbd31f5a-b735-4fd4-b08a-84a5067505d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1318048976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1318048976
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3191311100
Short name T157
Test name
Test status
Simulation time 16115519771 ps
CPU time 290.46 seconds
Started Jan 17 12:41:44 PM PST 24
Finished Jan 17 12:46:40 PM PST 24
Peak memory 266484 kb
Host smart-6d2f1d35-a56c-49e2-b7c1-58375b12ba51
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3191311100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3191311100
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.353119555
Short name T310
Test name
Test status
Simulation time 51430146103 ps
CPU time 2913.25 seconds
Started Jan 17 02:48:35 PM PST 24
Finished Jan 17 03:37:09 PM PST 24
Peak memory 289680 kb
Host smart-b05cf420-ece4-400b-9f27-8baf568bc939
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353119555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.353119555
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2179411867
Short name T143
Test name
Test status
Simulation time 5917635865 ps
CPU time 603.06 seconds
Started Jan 17 12:41:55 PM PST 24
Finished Jan 17 12:51:59 PM PST 24
Peak memory 265320 kb
Host smart-d4396f89-9cdb-47d9-9dbc-57b429f99566
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179411867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2179411867
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.365781677
Short name T228
Test name
Test status
Simulation time 95226006423 ps
CPU time 5839.34 seconds
Started Jan 17 02:51:29 PM PST 24
Finished Jan 17 04:28:53 PM PST 24
Peak memory 318124 kb
Host smart-10941cfb-1487-4e58-926e-a4e663fe8ef9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365781677 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.365781677
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.897592938
Short name T309
Test name
Test status
Simulation time 46802784335 ps
CPU time 505.8 seconds
Started Jan 17 02:59:04 PM PST 24
Finished Jan 17 03:07:34 PM PST 24
Peak memory 247284 kb
Host smart-56c761b1-3f99-44e3-b748-12c8a0bc5bd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897592938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.897592938
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1031930415
Short name T21
Test name
Test status
Simulation time 66914859705 ps
CPU time 4410.44 seconds
Started Jan 17 02:48:07 PM PST 24
Finished Jan 17 04:01:40 PM PST 24
Peak memory 285808 kb
Host smart-54441638-0b39-4d8d-a3de-ff22cb0f487b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031930415 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1031930415
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.585561011
Short name T303
Test name
Test status
Simulation time 104342154288 ps
CPU time 1409.35 seconds
Started Jan 17 02:54:45 PM PST 24
Finished Jan 17 03:18:15 PM PST 24
Peak memory 265280 kb
Host smart-2631110d-3e4f-46f4-b3cc-fa2f0a16f54d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585561011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.585561011
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.875114968
Short name T115
Test name
Test status
Simulation time 589660142439 ps
CPU time 7321.23 seconds
Started Jan 17 02:49:19 PM PST 24
Finished Jan 17 04:51:22 PM PST 24
Peak memory 321992 kb
Host smart-0468b6d4-7abb-462d-a4e8-e93a1dee9017
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875114968 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.875114968
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.614831063
Short name T258
Test name
Test status
Simulation time 83502427849 ps
CPU time 8704.89 seconds
Started Jan 17 02:55:36 PM PST 24
Finished Jan 17 05:20:42 PM PST 24
Peak memory 354800 kb
Host smart-76b5f2e5-d56d-4fcd-bca0-9e9aeb580800
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614831063 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.614831063
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3941755001
Short name T161
Test name
Test status
Simulation time 4901556658 ps
CPU time 336.34 seconds
Started Jan 17 12:41:55 PM PST 24
Finished Jan 17 12:47:32 PM PST 24
Peak memory 271784 kb
Host smart-eaf87bea-18a0-46d0-9f0a-30132cb10b22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3941755001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3941755001
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.747660328
Short name T191
Test name
Test status
Simulation time 381848534 ps
CPU time 3.86 seconds
Started Jan 17 02:48:09 PM PST 24
Finished Jan 17 02:48:15 PM PST 24
Peak memory 248796 kb
Host smart-c53174a6-b666-4114-9c82-a88cc6f88348
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=747660328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.747660328
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.76986632
Short name T203
Test name
Test status
Simulation time 54660386 ps
CPU time 4.03 seconds
Started Jan 17 02:48:21 PM PST 24
Finished Jan 17 02:48:26 PM PST 24
Peak memory 257084 kb
Host smart-cc5e907d-18fc-492b-9c49-6c986d3af397
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=76986632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.76986632
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1670102638
Short name T188
Test name
Test status
Simulation time 64471356 ps
CPU time 2.91 seconds
Started Jan 17 02:50:42 PM PST 24
Finished Jan 17 02:50:46 PM PST 24
Peak memory 248828 kb
Host smart-35cfc942-4bea-4310-97aa-d795d7d8a8ea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1670102638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1670102638
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3858841731
Short name T195
Test name
Test status
Simulation time 17302862 ps
CPU time 2.7 seconds
Started Jan 17 02:51:02 PM PST 24
Finished Jan 17 02:51:06 PM PST 24
Peak memory 248912 kb
Host smart-154bd275-bc29-4c96-81b1-74ea390dc98e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3858841731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3858841731
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1357464090
Short name T151
Test name
Test status
Simulation time 12773539490 ps
CPU time 994.09 seconds
Started Jan 17 12:41:31 PM PST 24
Finished Jan 17 12:58:06 PM PST 24
Peak memory 272480 kb
Host smart-16563a07-1d1b-4d88-a6fc-05978c57fd55
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357464090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1357464090
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2274650550
Short name T120
Test name
Test status
Simulation time 7807697 ps
CPU time 1.51 seconds
Started Jan 17 12:41:46 PM PST 24
Finished Jan 17 12:41:51 PM PST 24
Peak memory 235428 kb
Host smart-a4caf827-b2ae-4fc9-96f2-39ddb5b06027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2274650550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2274650550
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.248999407
Short name T8
Test name
Test status
Simulation time 27297503263 ps
CPU time 269.07 seconds
Started Jan 17 02:51:41 PM PST 24
Finished Jan 17 02:56:10 PM PST 24
Peak memory 246628 kb
Host smart-a1b74fcd-e8e3-4f39-ac2e-5c0252dc5f33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248999407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.248999407
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2188386034
Short name T661
Test name
Test status
Simulation time 246656740777 ps
CPU time 6141.3 seconds
Started Jan 17 02:52:54 PM PST 24
Finished Jan 17 04:35:18 PM PST 24
Peak memory 387052 kb
Host smart-f4db0b4b-d540-4076-b47a-1f64c2ba560f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188386034 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2188386034
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3318825115
Short name T231
Test name
Test status
Simulation time 22620452220 ps
CPU time 1545.71 seconds
Started Jan 17 02:57:37 PM PST 24
Finished Jan 17 03:23:23 PM PST 24
Peak memory 289464 kb
Host smart-fc180972-ec92-41d9-9bb4-a1fa7932a68b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318825115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3318825115
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.348847566
Short name T129
Test name
Test status
Simulation time 3167343344 ps
CPU time 173.94 seconds
Started Jan 17 12:41:52 PM PST 24
Finished Jan 17 12:44:47 PM PST 24
Peak memory 269640 kb
Host smart-0e478389-f318-43c2-929a-71979bf3de97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=348847566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.348847566
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3551426050
Short name T104
Test name
Test status
Simulation time 5313960002 ps
CPU time 19.28 seconds
Started Jan 17 02:47:51 PM PST 24
Finished Jan 17 02:48:12 PM PST 24
Peak memory 253440 kb
Host smart-5967f48b-a28b-41fc-946c-f764acf61dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35514
26050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3551426050
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2221519018
Short name T174
Test name
Test status
Simulation time 65361703 ps
CPU time 3.25 seconds
Started Jan 17 12:41:58 PM PST 24
Finished Jan 17 12:42:03 PM PST 24
Peak memory 235548 kb
Host smart-23608dd9-a32f-4c91-b679-151000925d14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2221519018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2221519018
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.738131837
Short name T127
Test name
Test status
Simulation time 6576655582 ps
CPU time 179.01 seconds
Started Jan 17 12:41:58 PM PST 24
Finished Jan 17 12:44:59 PM PST 24
Peak memory 271664 kb
Host smart-b46a3615-5bdd-4c28-ba0f-9fd3861cb475
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=738131837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.738131837
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2192752475
Short name T774
Test name
Test status
Simulation time 22293668 ps
CPU time 1.43 seconds
Started Jan 17 12:41:28 PM PST 24
Finished Jan 17 12:41:31 PM PST 24
Peak memory 235676 kb
Host smart-39cf9e8d-81ac-4e61-91b7-52cdc3c07207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2192752475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2192752475
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3401407430
Short name T78
Test name
Test status
Simulation time 841317352 ps
CPU time 48.8 seconds
Started Jan 17 02:50:17 PM PST 24
Finished Jan 17 02:51:06 PM PST 24
Peak memory 254244 kb
Host smart-8a48435d-e312-4b22-8f38-5626b748bf43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34014
07430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3401407430
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3257065473
Short name T550
Test name
Test status
Simulation time 633394180 ps
CPU time 33.64 seconds
Started Jan 17 02:50:32 PM PST 24
Finished Jan 17 02:51:09 PM PST 24
Peak memory 255536 kb
Host smart-64624f0e-83ae-4edc-a9b0-e3b5280ab03b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32570
65473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3257065473
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2742741692
Short name T564
Test name
Test status
Simulation time 34303967535 ps
CPU time 235.83 seconds
Started Jan 17 02:51:02 PM PST 24
Finished Jan 17 02:54:59 PM PST 24
Peak memory 256876 kb
Host smart-e920a145-83bf-4eb6-8d35-a18db6d18148
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742741692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2742741692
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2256021549
Short name T40
Test name
Test status
Simulation time 13174158512 ps
CPU time 923.31 seconds
Started Jan 17 02:51:58 PM PST 24
Finished Jan 17 03:07:28 PM PST 24
Peak memory 273104 kb
Host smart-d669e160-73b6-4aa1-941c-664c6b0e6ba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256021549 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2256021549
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1969225080
Short name T110
Test name
Test status
Simulation time 28634668687 ps
CPU time 1771.61 seconds
Started Jan 17 02:48:44 PM PST 24
Finished Jan 17 03:18:18 PM PST 24
Peak memory 281632 kb
Host smart-e4dda99e-36e2-4b1b-b4c4-ac03e6f7d4f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969225080 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1969225080
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.4279952296
Short name T255
Test name
Test status
Simulation time 12112159655 ps
CPU time 38.45 seconds
Started Jan 17 02:52:18 PM PST 24
Finished Jan 17 02:52:57 PM PST 24
Peak memory 255496 kb
Host smart-79f4d234-b478-49c0-85ee-2df80d4e64c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42799
52296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.4279952296
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2965550659
Short name T311
Test name
Test status
Simulation time 16886415471 ps
CPU time 220.82 seconds
Started Jan 17 02:52:58 PM PST 24
Finished Jan 17 02:56:41 PM PST 24
Peak memory 247532 kb
Host smart-4f49a105-39a2-4c9f-8e93-1cb61473b76e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965550659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2965550659
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2162677240
Short name T331
Test name
Test status
Simulation time 98343339693 ps
CPU time 2862.62 seconds
Started Jan 17 02:53:24 PM PST 24
Finished Jan 17 03:41:08 PM PST 24
Peak memory 284836 kb
Host smart-a1426c97-ac61-4e4d-830c-41fb8a896d37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162677240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2162677240
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.2109835014
Short name T241
Test name
Test status
Simulation time 360231500322 ps
CPU time 9796.65 seconds
Started Jan 17 02:54:02 PM PST 24
Finished Jan 17 05:37:21 PM PST 24
Peak memory 412236 kb
Host smart-0d72fe33-a383-45c9-8603-2a9d3e8e3491
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109835014 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.2109835014
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3338746213
Short name T53
Test name
Test status
Simulation time 25084736865 ps
CPU time 1170.39 seconds
Started Jan 17 02:54:28 PM PST 24
Finished Jan 17 03:13:59 PM PST 24
Peak memory 288872 kb
Host smart-f935a05f-5af7-46cd-a88f-d66ace75cf34
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338746213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3338746213
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.122924555
Short name T265
Test name
Test status
Simulation time 377754745048 ps
CPU time 5081.75 seconds
Started Jan 17 02:55:07 PM PST 24
Finished Jan 17 04:19:51 PM PST 24
Peak memory 305600 kb
Host smart-4997ccd0-f6b4-4d46-a16d-41d284d6ef76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122924555 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.122924555
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3428507745
Short name T239
Test name
Test status
Simulation time 34444562601 ps
CPU time 1544.56 seconds
Started Jan 17 02:56:20 PM PST 24
Finished Jan 17 03:22:05 PM PST 24
Peak memory 289540 kb
Host smart-97bb2cb5-931b-444a-a995-6be5a0f510c8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428507745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3428507745
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3920593442
Short name T247
Test name
Test status
Simulation time 82066078247 ps
CPU time 873.43 seconds
Started Jan 17 02:56:51 PM PST 24
Finished Jan 17 03:11:25 PM PST 24
Peak memory 284964 kb
Host smart-7c5c806d-f4b6-4080-87b6-c6d35446ed5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920593442 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3920593442
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.4154203012
Short name T234
Test name
Test status
Simulation time 197156581251 ps
CPU time 3134.05 seconds
Started Jan 17 02:49:05 PM PST 24
Finished Jan 17 03:41:24 PM PST 24
Peak memory 289740 kb
Host smart-b353cf9b-a653-40ed-a01a-741e450da070
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154203012 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.4154203012
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2956104067
Short name T229
Test name
Test status
Simulation time 399457259 ps
CPU time 26.1 seconds
Started Jan 17 02:58:33 PM PST 24
Finished Jan 17 02:59:01 PM PST 24
Peak memory 254840 kb
Host smart-db2b8a52-2469-415a-abbd-5c9931bea3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29561
04067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2956104067
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2748374340
Short name T248
Test name
Test status
Simulation time 412774939527 ps
CPU time 2604.22 seconds
Started Jan 17 02:58:48 PM PST 24
Finished Jan 17 03:42:14 PM PST 24
Peak memory 297768 kb
Host smart-8da5a47b-b730-4a08-ba7d-1fd0806f6aa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748374340 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2748374340
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1471896696
Short name T261
Test name
Test status
Simulation time 954205137 ps
CPU time 21.12 seconds
Started Jan 17 02:49:34 PM PST 24
Finished Jan 17 02:50:00 PM PST 24
Peak memory 255144 kb
Host smart-67099511-c980-43a0-ab7e-e95db2fb7cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14718
96696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1471896696
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1722543990
Short name T149
Test name
Test status
Simulation time 4460740215 ps
CPU time 583.07 seconds
Started Jan 17 12:41:37 PM PST 24
Finished Jan 17 12:51:23 PM PST 24
Peak memory 265288 kb
Host smart-d45f90a4-11c7-4c5d-948a-bfb1cf8bb783
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722543990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1722543990
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3388352004
Short name T122
Test name
Test status
Simulation time 209430350 ps
CPU time 9.97 seconds
Started Jan 17 12:41:55 PM PST 24
Finished Jan 17 12:42:06 PM PST 24
Peak memory 236452 kb
Host smart-c1c17036-b360-4244-bf4c-8bb3cc8f142b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3388352004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3388352004
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3280055144
Short name T170
Test name
Test status
Simulation time 39445716 ps
CPU time 3.26 seconds
Started Jan 17 12:42:07 PM PST 24
Finished Jan 17 12:42:13 PM PST 24
Peak memory 237268 kb
Host smart-d880fa47-67f4-405c-94f6-6e7f82d600f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3280055144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3280055144
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.312658728
Short name T180
Test name
Test status
Simulation time 881750510 ps
CPU time 65.08 seconds
Started Jan 17 12:41:25 PM PST 24
Finished Jan 17 12:42:33 PM PST 24
Peak memory 236408 kb
Host smart-acd64ae7-fd37-473a-aad2-911dbb7eea16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=312658728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.312658728
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.582911526
Short name T132
Test name
Test status
Simulation time 1917537683 ps
CPU time 212.26 seconds
Started Jan 17 12:41:44 PM PST 24
Finished Jan 17 12:45:21 PM PST 24
Peak memory 269632 kb
Host smart-6f5ee998-077b-45a3-b24b-2d1d5ec11cec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=582911526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.582911526
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2605859882
Short name T146
Test name
Test status
Simulation time 5502667325 ps
CPU time 380.24 seconds
Started Jan 17 12:41:45 PM PST 24
Finished Jan 17 12:48:09 PM PST 24
Peak memory 271524 kb
Host smart-9376b924-2947-4518-8e17-91908a08d80b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2605859882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2605859882
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1461257079
Short name T173
Test name
Test status
Simulation time 225334031 ps
CPU time 4.37 seconds
Started Jan 17 12:41:50 PM PST 24
Finished Jan 17 12:41:56 PM PST 24
Peak memory 236352 kb
Host smart-f2bf98f7-15a4-4742-a2a8-bf654f4cbdcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1461257079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1461257079
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1614199504
Short name T158
Test name
Test status
Simulation time 15647573071 ps
CPU time 498.21 seconds
Started Jan 17 12:41:50 PM PST 24
Finished Jan 17 12:50:10 PM PST 24
Peak memory 269196 kb
Host smart-e5c82563-487f-4e2b-abcc-73f76eb287c8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614199504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1614199504
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2630520996
Short name T181
Test name
Test status
Simulation time 115512119 ps
CPU time 2.81 seconds
Started Jan 17 12:42:06 PM PST 24
Finished Jan 17 12:42:09 PM PST 24
Peak memory 236376 kb
Host smart-76ea8659-2e70-4451-9756-b5f1faaaea3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2630520996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2630520996
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2121084375
Short name T171
Test name
Test status
Simulation time 464953666 ps
CPU time 35.41 seconds
Started Jan 17 12:41:37 PM PST 24
Finished Jan 17 12:42:15 PM PST 24
Peak memory 236628 kb
Host smart-7b099fee-5eab-47dc-a367-b0eaef47714f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2121084375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2121084375
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.964229315
Short name T159
Test name
Test status
Simulation time 7555709952 ps
CPU time 480.95 seconds
Started Jan 17 12:41:32 PM PST 24
Finished Jan 17 12:49:34 PM PST 24
Peak memory 265352 kb
Host smart-9a55decc-2e20-4b15-bf77-2e7f70acea37
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964229315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.964229315
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.806630393
Short name T175
Test name
Test status
Simulation time 325313821 ps
CPU time 45.85 seconds
Started Jan 17 12:41:32 PM PST 24
Finished Jan 17 12:42:19 PM PST 24
Peak memory 240608 kb
Host smart-dc4dde82-ab5e-4031-9aa0-5bfbf24f1476
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=806630393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.806630393
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.117459862
Short name T177
Test name
Test status
Simulation time 1352159306 ps
CPU time 43.65 seconds
Started Jan 17 12:41:47 PM PST 24
Finished Jan 17 12:42:33 PM PST 24
Peak memory 239256 kb
Host smart-6bd22465-baa6-483a-a8ba-9c59a3fc03b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=117459862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.117459862
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1089316981
Short name T172
Test name
Test status
Simulation time 1870872585 ps
CPU time 66.56 seconds
Started Jan 17 12:41:53 PM PST 24
Finished Jan 17 12:43:01 PM PST 24
Peak memory 236148 kb
Host smart-1ac5d7b5-459e-4752-be12-305d92f32a40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1089316981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1089316981
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2673987138
Short name T176
Test name
Test status
Simulation time 62578936 ps
CPU time 4.49 seconds
Started Jan 17 12:41:55 PM PST 24
Finished Jan 17 12:42:00 PM PST 24
Peak memory 236856 kb
Host smart-49929710-d8f6-4af5-b3ba-89cecb192f13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2673987138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2673987138
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.4106609699
Short name T178
Test name
Test status
Simulation time 3156793996 ps
CPU time 35.46 seconds
Started Jan 17 12:41:54 PM PST 24
Finished Jan 17 12:42:31 PM PST 24
Peak memory 239400 kb
Host smart-978f7d04-dec5-4565-89f0-6cf4ec434cea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4106609699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.4106609699
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.924350908
Short name T179
Test name
Test status
Simulation time 91954802 ps
CPU time 2.43 seconds
Started Jan 17 12:42:08 PM PST 24
Finished Jan 17 12:42:15 PM PST 24
Peak memory 235480 kb
Host smart-ea869ed2-590a-4e5d-9e47-878da23f4781
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=924350908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.924350908
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2735574055
Short name T169
Test name
Test status
Simulation time 113523214 ps
CPU time 2.76 seconds
Started Jan 17 12:41:51 PM PST 24
Finished Jan 17 12:41:55 PM PST 24
Peak memory 235460 kb
Host smart-c94bd4dd-db0b-4a47-aa42-b4b348eecf11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2735574055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2735574055
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.606917440
Short name T35
Test name
Test status
Simulation time 22753903 ps
CPU time 2.45 seconds
Started Jan 17 12:41:40 PM PST 24
Finished Jan 17 12:41:49 PM PST 24
Peak memory 236452 kb
Host smart-01c570a8-7f9f-42d6-bf89-0b83d3abeac7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=606917440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.606917440
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1053194644
Short name T168
Test name
Test status
Simulation time 157391387 ps
CPU time 18.18 seconds
Started Jan 17 12:41:36 PM PST 24
Finished Jan 17 12:41:58 PM PST 24
Peak memory 240324 kb
Host smart-69fc53c9-0514-4e59-9f94-5ebc7bbd17ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1053194644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1053194644
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3941464168
Short name T735
Test name
Test status
Simulation time 1793009783 ps
CPU time 114.23 seconds
Started Jan 17 12:41:29 PM PST 24
Finished Jan 17 12:43:24 PM PST 24
Peak memory 236568 kb
Host smart-a63bbb4a-53ef-4806-af5d-8013cef42848
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3941464168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3941464168
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3259777754
Short name T785
Test name
Test status
Simulation time 53356697082 ps
CPU time 261.76 seconds
Started Jan 17 12:41:22 PM PST 24
Finished Jan 17 12:45:45 PM PST 24
Peak memory 236368 kb
Host smart-79eefb4d-d8d6-4047-a796-05b65911983b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3259777754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3259777754
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3907742822
Short name T182
Test name
Test status
Simulation time 661281515 ps
CPU time 9.11 seconds
Started Jan 17 12:41:21 PM PST 24
Finished Jan 17 12:41:31 PM PST 24
Peak memory 240252 kb
Host smart-d3075b3e-cd61-48d2-b12d-0c5910ad63df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3907742822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3907742822
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.155311191
Short name T739
Test name
Test status
Simulation time 33319054 ps
CPU time 4.21 seconds
Started Jan 17 12:41:21 PM PST 24
Finished Jan 17 12:41:27 PM PST 24
Peak memory 240272 kb
Host smart-a91c9c28-5161-4997-ae75-461ebc02934d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155311191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.155311191
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3560465296
Short name T811
Test name
Test status
Simulation time 126811157 ps
CPU time 5.35 seconds
Started Jan 17 12:41:25 PM PST 24
Finished Jan 17 12:41:34 PM PST 24
Peak memory 240300 kb
Host smart-53426424-b135-4927-a6ce-771d3cb5f1a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3560465296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3560465296
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.4018380089
Short name T779
Test name
Test status
Simulation time 8544050 ps
CPU time 1.58 seconds
Started Jan 17 12:41:24 PM PST 24
Finished Jan 17 12:41:29 PM PST 24
Peak memory 236312 kb
Host smart-c19878fa-c4a0-4fcd-a39b-885f8ca23dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4018380089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.4018380089
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2588728160
Short name T843
Test name
Test status
Simulation time 3977132879 ps
CPU time 47.97 seconds
Started Jan 17 12:41:21 PM PST 24
Finished Jan 17 12:42:10 PM PST 24
Peak memory 248532 kb
Host smart-3e051194-5352-4b07-b552-403cbb39269a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2588728160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2588728160
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.17606232
Short name T141
Test name
Test status
Simulation time 2622891495 ps
CPU time 171.15 seconds
Started Jan 17 12:41:21 PM PST 24
Finished Jan 17 12:44:13 PM PST 24
Peak memory 256428 kb
Host smart-61e3089a-792f-4d7c-92cd-3f270ad47567
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=17606232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors
.17606232
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2513119879
Short name T781
Test name
Test status
Simulation time 59992548 ps
CPU time 7.61 seconds
Started Jan 17 12:41:19 PM PST 24
Finished Jan 17 12:41:27 PM PST 24
Peak memory 247292 kb
Host smart-557e70e1-1a6e-4b4b-80f4-fc61eb465d9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2513119879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2513119879
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.434822406
Short name T817
Test name
Test status
Simulation time 181403032 ps
CPU time 2.5 seconds
Started Jan 17 12:41:20 PM PST 24
Finished Jan 17 12:41:23 PM PST 24
Peak memory 237376 kb
Host smart-d06c547d-6487-40ac-bc5e-272374f96ff0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=434822406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.434822406
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1600537974
Short name T744
Test name
Test status
Simulation time 571793152 ps
CPU time 73.2 seconds
Started Jan 17 12:41:30 PM PST 24
Finished Jan 17 12:42:45 PM PST 24
Peak memory 236336 kb
Host smart-c6d30e48-6963-4ee5-b0a0-a0fcfb45a58e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1600537974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1600537974
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.606847136
Short name T762
Test name
Test status
Simulation time 5838177895 ps
CPU time 371.18 seconds
Started Jan 17 12:41:30 PM PST 24
Finished Jan 17 12:47:42 PM PST 24
Peak memory 236396 kb
Host smart-57373633-d56c-4d65-a1a8-61f2ab86659c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=606847136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.606847136
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1795918111
Short name T816
Test name
Test status
Simulation time 966230595 ps
CPU time 5.29 seconds
Started Jan 17 12:41:25 PM PST 24
Finished Jan 17 12:41:33 PM PST 24
Peak memory 240328 kb
Host smart-43a23b3b-2ab4-48a4-8e13-d44c02f44edf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1795918111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1795918111
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1661292412
Short name T166
Test name
Test status
Simulation time 67505247 ps
CPU time 3.84 seconds
Started Jan 17 12:41:24 PM PST 24
Finished Jan 17 12:41:32 PM PST 24
Peak memory 255832 kb
Host smart-7c6b07cb-7f13-4203-8ea8-a00ce813bfa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661292412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1661292412
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3060997510
Short name T832
Test name
Test status
Simulation time 480131444 ps
CPU time 9.89 seconds
Started Jan 17 12:41:27 PM PST 24
Finished Jan 17 12:41:38 PM PST 24
Peak memory 236308 kb
Host smart-079f0935-41fd-4c43-9454-87392a6af591
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3060997510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3060997510
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3327981780
Short name T823
Test name
Test status
Simulation time 363230188 ps
CPU time 12.21 seconds
Started Jan 17 12:41:29 PM PST 24
Finished Jan 17 12:41:42 PM PST 24
Peak memory 240268 kb
Host smart-df70120b-6502-44a5-92b4-c18b566dadec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3327981780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3327981780
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.798418852
Short name T139
Test name
Test status
Simulation time 1487502569 ps
CPU time 89.17 seconds
Started Jan 17 12:41:25 PM PST 24
Finished Jan 17 12:42:57 PM PST 24
Peak memory 256992 kb
Host smart-f4cf29f8-6a1c-49d5-b67b-8f9e04f2b5b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=798418852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.798418852
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2292455631
Short name T155
Test name
Test status
Simulation time 8354821524 ps
CPU time 523.96 seconds
Started Jan 17 12:41:20 PM PST 24
Finished Jan 17 12:50:05 PM PST 24
Peak memory 267324 kb
Host smart-c17c8b18-1ec4-4c21-bac9-19db1094be01
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292455631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2292455631
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2270756025
Short name T784
Test name
Test status
Simulation time 339477363 ps
CPU time 12.39 seconds
Started Jan 17 12:41:26 PM PST 24
Finished Jan 17 12:41:41 PM PST 24
Peak memory 247776 kb
Host smart-024517ea-bcbe-459c-ad8d-36dbbe981b4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2270756025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2270756025
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1910573412
Short name T844
Test name
Test status
Simulation time 271999834 ps
CPU time 7.48 seconds
Started Jan 17 12:41:44 PM PST 24
Finished Jan 17 12:41:56 PM PST 24
Peak memory 243264 kb
Host smart-87c2d524-e367-48fc-b916-080c743173c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910573412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1910573412
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1654086344
Short name T829
Test name
Test status
Simulation time 33821279 ps
CPU time 5.42 seconds
Started Jan 17 12:41:46 PM PST 24
Finished Jan 17 12:41:54 PM PST 24
Peak memory 235472 kb
Host smart-3a2c36b4-d803-4188-a08f-f653e3640833
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1654086344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1654086344
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1883737677
Short name T819
Test name
Test status
Simulation time 27905409 ps
CPU time 1.37 seconds
Started Jan 17 12:41:51 PM PST 24
Finished Jan 17 12:41:53 PM PST 24
Peak memory 235528 kb
Host smart-ebebe6ea-0f01-412c-9adc-4b977c68e80d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1883737677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1883737677
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2779961432
Short name T828
Test name
Test status
Simulation time 676561906 ps
CPU time 19.15 seconds
Started Jan 17 12:41:49 PM PST 24
Finished Jan 17 12:42:10 PM PST 24
Peak memory 240108 kb
Host smart-1eeec04a-ebc8-4848-b6cc-9338b5d070a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2779961432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2779961432
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3263146839
Short name T810
Test name
Test status
Simulation time 169983890 ps
CPU time 11.46 seconds
Started Jan 17 12:41:46 PM PST 24
Finished Jan 17 12:42:01 PM PST 24
Peak memory 252736 kb
Host smart-524fdf1a-38f0-4208-93a5-474b5e9319c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3263146839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3263146839
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1380190341
Short name T793
Test name
Test status
Simulation time 371825693 ps
CPU time 5.17 seconds
Started Jan 17 12:41:51 PM PST 24
Finished Jan 17 12:41:57 PM PST 24
Peak memory 251652 kb
Host smart-80e21f18-30fc-4f63-b0c4-9924d3e11d18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380190341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1380190341
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.4172241469
Short name T780
Test name
Test status
Simulation time 90864821 ps
CPU time 4.21 seconds
Started Jan 17 12:41:46 PM PST 24
Finished Jan 17 12:41:53 PM PST 24
Peak memory 235516 kb
Host smart-91cf4eb8-0cef-48fc-a4a5-a153573853ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4172241469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.4172241469
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.4015584082
Short name T803
Test name
Test status
Simulation time 12430566 ps
CPU time 1.78 seconds
Started Jan 17 12:41:51 PM PST 24
Finished Jan 17 12:41:54 PM PST 24
Peak memory 236460 kb
Host smart-768db1fb-8a48-49e1-b960-7b43b45ccf69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4015584082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.4015584082
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3994586711
Short name T31
Test name
Test status
Simulation time 273269166 ps
CPU time 21.71 seconds
Started Jan 17 12:41:47 PM PST 24
Finished Jan 17 12:42:11 PM PST 24
Peak memory 244584 kb
Host smart-c49f369d-2568-4a08-9142-1a067b77fb9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3994586711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3994586711
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.4291788269
Short name T131
Test name
Test status
Simulation time 164631052787 ps
CPU time 1161.13 seconds
Started Jan 17 12:41:45 PM PST 24
Finished Jan 17 01:01:10 PM PST 24
Peak memory 265288 kb
Host smart-7b3ad356-6b31-4700-baac-6b362c0e5488
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291788269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.4291788269
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1647750656
Short name T164
Test name
Test status
Simulation time 730758035 ps
CPU time 23.43 seconds
Started Jan 17 12:41:53 PM PST 24
Finished Jan 17 12:42:18 PM PST 24
Peak memory 254728 kb
Host smart-d98e5c45-06f2-412f-806d-f7b6d7a5177a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1647750656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1647750656
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2822674182
Short name T797
Test name
Test status
Simulation time 28643138 ps
CPU time 3.38 seconds
Started Jan 17 12:41:53 PM PST 24
Finished Jan 17 12:41:58 PM PST 24
Peak memory 239292 kb
Host smart-84c22920-152b-4196-b40f-5469f7773d2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822674182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2822674182
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1902448134
Short name T763
Test name
Test status
Simulation time 116164600 ps
CPU time 3.61 seconds
Started Jan 17 12:41:51 PM PST 24
Finished Jan 17 12:41:56 PM PST 24
Peak memory 236440 kb
Host smart-4c13e22a-c924-451c-a5c5-cf7bbb3210f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1902448134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1902448134
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1245189147
Short name T736
Test name
Test status
Simulation time 132436417 ps
CPU time 12.84 seconds
Started Jan 17 12:41:50 PM PST 24
Finished Jan 17 12:42:05 PM PST 24
Peak memory 245540 kb
Host smart-7efb005f-7075-41eb-afaf-5fbdecc70aca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1245189147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1245189147
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1932495174
Short name T144
Test name
Test status
Simulation time 1661123453 ps
CPU time 121.41 seconds
Started Jan 17 12:41:50 PM PST 24
Finished Jan 17 12:43:53 PM PST 24
Peak memory 256280 kb
Host smart-0b95f80f-2c5e-4bd1-a161-1e45a24d4042
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1932495174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1932495174
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.251836208
Short name T142
Test name
Test status
Simulation time 18571403684 ps
CPU time 1199.68 seconds
Started Jan 17 12:41:49 PM PST 24
Finished Jan 17 01:01:51 PM PST 24
Peak memory 265188 kb
Host smart-481bec9a-10b4-4050-ba33-75bd6d628b76
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251836208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.251836208
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.701782998
Short name T773
Test name
Test status
Simulation time 78447729 ps
CPU time 3.54 seconds
Started Jan 17 12:41:53 PM PST 24
Finished Jan 17 12:41:58 PM PST 24
Peak memory 239548 kb
Host smart-10e6561d-8f80-4b51-9368-260396220fdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=701782998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.701782998
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1636076797
Short name T825
Test name
Test status
Simulation time 25231298 ps
CPU time 4.29 seconds
Started Jan 17 12:42:05 PM PST 24
Finished Jan 17 12:42:10 PM PST 24
Peak memory 256772 kb
Host smart-25f048dc-475e-4fa8-93e0-b1d772255b52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636076797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1636076797
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1725589023
Short name T756
Test name
Test status
Simulation time 44496035 ps
CPU time 5.91 seconds
Started Jan 17 12:41:55 PM PST 24
Finished Jan 17 12:42:02 PM PST 24
Peak memory 236320 kb
Host smart-a1ccdb2c-1749-4ac0-a360-26cf2b3c2d22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1725589023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1725589023
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3175765126
Short name T336
Test name
Test status
Simulation time 10878561 ps
CPU time 1.39 seconds
Started Jan 17 12:41:58 PM PST 24
Finished Jan 17 12:42:00 PM PST 24
Peak memory 236424 kb
Host smart-3866e3d3-f7ce-4b9e-8f75-0e16bf33591a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3175765126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3175765126
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3313898691
Short name T28
Test name
Test status
Simulation time 95233312 ps
CPU time 13.3 seconds
Started Jan 17 12:41:55 PM PST 24
Finished Jan 17 12:42:10 PM PST 24
Peak memory 244380 kb
Host smart-220aa06c-f0e8-4543-b6a4-a58ec75c785d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3313898691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3313898691
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2849480087
Short name T138
Test name
Test status
Simulation time 24585426227 ps
CPU time 199.27 seconds
Started Jan 17 12:41:53 PM PST 24
Finished Jan 17 12:45:13 PM PST 24
Peak memory 265000 kb
Host smart-3272c4e7-b351-4459-b536-96315fc79d47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2849480087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2849480087
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1464029790
Short name T732
Test name
Test status
Simulation time 955865133 ps
CPU time 12.14 seconds
Started Jan 17 12:41:51 PM PST 24
Finished Jan 17 12:42:04 PM PST 24
Peak memory 247840 kb
Host smart-7507b7ec-8ea5-4624-bd71-be9756be6eba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1464029790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1464029790
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3031155067
Short name T121
Test name
Test status
Simulation time 22905085 ps
CPU time 4.3 seconds
Started Jan 17 12:41:57 PM PST 24
Finished Jan 17 12:42:03 PM PST 24
Peak memory 240928 kb
Host smart-e8f37c06-eb49-4480-937a-8e3f19095ac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031155067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3031155067
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3040436186
Short name T833
Test name
Test status
Simulation time 41536812 ps
CPU time 3.69 seconds
Started Jan 17 12:41:56 PM PST 24
Finished Jan 17 12:42:01 PM PST 24
Peak memory 236304 kb
Host smart-3468e0c6-27db-4d29-9320-e95c6fed42f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3040436186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3040436186
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3743573246
Short name T812
Test name
Test status
Simulation time 9274512 ps
CPU time 1.37 seconds
Started Jan 17 12:41:54 PM PST 24
Finished Jan 17 12:41:57 PM PST 24
Peak memory 235456 kb
Host smart-211c7d5b-9f7a-4275-9859-51b1e93bf56f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3743573246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3743573246
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3196191684
Short name T838
Test name
Test status
Simulation time 650288464 ps
CPU time 23.2 seconds
Started Jan 17 12:41:58 PM PST 24
Finished Jan 17 12:42:22 PM PST 24
Peak memory 240196 kb
Host smart-14e0389a-58bb-4406-a373-6544b570f2b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3196191684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3196191684
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1894748635
Short name T123
Test name
Test status
Simulation time 49750831675 ps
CPU time 973.88 seconds
Started Jan 17 12:41:58 PM PST 24
Finished Jan 17 12:58:13 PM PST 24
Peak memory 265548 kb
Host smart-7b08c6e9-bff4-4686-b52f-43014d771a4b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894748635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1894748635
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.263021366
Short name T789
Test name
Test status
Simulation time 550163558 ps
CPU time 9.79 seconds
Started Jan 17 12:41:54 PM PST 24
Finished Jan 17 12:42:05 PM PST 24
Peak memory 252896 kb
Host smart-eef18c24-c2f8-4787-8e7e-f4cfe955c605
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=263021366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.263021366
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1976179766
Short name T746
Test name
Test status
Simulation time 27108742 ps
CPU time 4.42 seconds
Started Jan 17 12:41:56 PM PST 24
Finished Jan 17 12:42:01 PM PST 24
Peak memory 256656 kb
Host smart-65d6b10d-fe04-46e9-95da-802fc51294c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976179766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1976179766
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1009527496
Short name T792
Test name
Test status
Simulation time 50309983 ps
CPU time 4.74 seconds
Started Jan 17 12:41:58 PM PST 24
Finished Jan 17 12:42:04 PM PST 24
Peak memory 240052 kb
Host smart-db64d28d-c3ec-4ab9-9987-7a2f20bdd5b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1009527496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1009527496
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1707948074
Short name T837
Test name
Test status
Simulation time 21533372 ps
CPU time 1.38 seconds
Started Jan 17 12:41:52 PM PST 24
Finished Jan 17 12:41:55 PM PST 24
Peak memory 236396 kb
Host smart-0617694b-2e22-4c17-b92b-888edc57a279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1707948074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1707948074
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3628974682
Short name T836
Test name
Test status
Simulation time 336986632 ps
CPU time 11.7 seconds
Started Jan 17 12:42:04 PM PST 24
Finished Jan 17 12:42:16 PM PST 24
Peak memory 240332 kb
Host smart-81d029f6-5ed7-4ffd-a612-15af14e648a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3628974682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3628974682
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1985971055
Short name T737
Test name
Test status
Simulation time 262267886 ps
CPU time 8.96 seconds
Started Jan 17 12:41:58 PM PST 24
Finished Jan 17 12:42:08 PM PST 24
Peak memory 252864 kb
Host smart-2024ff02-0b78-4a01-89cd-4cb98cc6bad0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1985971055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1985971055
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.56867686
Short name T801
Test name
Test status
Simulation time 32374957 ps
CPU time 6 seconds
Started Jan 17 12:41:55 PM PST 24
Finished Jan 17 12:42:02 PM PST 24
Peak memory 252568 kb
Host smart-af006de3-d16f-42c7-8699-60213aabeab7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56867686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.alert_handler_csr_mem_rw_with_rand_reset.56867686
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.937541476
Short name T831
Test name
Test status
Simulation time 204846351 ps
CPU time 10.26 seconds
Started Jan 17 12:41:54 PM PST 24
Finished Jan 17 12:42:05 PM PST 24
Peak memory 236328 kb
Host smart-667cea7b-cd34-42ca-b9e8-763bf19b723d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=937541476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.937541476
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1259517236
Short name T824
Test name
Test status
Simulation time 15411885 ps
CPU time 1.34 seconds
Started Jan 17 12:42:01 PM PST 24
Finished Jan 17 12:42:03 PM PST 24
Peak memory 235512 kb
Host smart-5d4fa40b-bc65-4de2-8576-5060f70279cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1259517236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1259517236
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.846131763
Short name T150
Test name
Test status
Simulation time 180724049 ps
CPU time 24.68 seconds
Started Jan 17 12:41:54 PM PST 24
Finished Jan 17 12:42:20 PM PST 24
Peak memory 244480 kb
Host smart-8197b594-8c60-48e8-9f07-28b0271e5dcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=846131763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.846131763
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3199763735
Short name T162
Test name
Test status
Simulation time 15876085456 ps
CPU time 1089.82 seconds
Started Jan 17 12:41:54 PM PST 24
Finished Jan 17 01:00:06 PM PST 24
Peak memory 265448 kb
Host smart-ab1d5bb3-58c8-41bf-822b-fed7c79cef7c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199763735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3199763735
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.4210477686
Short name T842
Test name
Test status
Simulation time 102637742 ps
CPU time 4.65 seconds
Started Jan 17 12:41:56 PM PST 24
Finished Jan 17 12:42:02 PM PST 24
Peak memory 248108 kb
Host smart-098eb0e8-35a4-4cef-abcf-0e693b89bfff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4210477686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.4210477686
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3257707565
Short name T165
Test name
Test status
Simulation time 33546340 ps
CPU time 3.95 seconds
Started Jan 17 12:42:10 PM PST 24
Finished Jan 17 12:42:18 PM PST 24
Peak memory 238428 kb
Host smart-b7dc00b0-c03b-46d0-a905-f9858888842d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257707565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3257707565
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2316045981
Short name T826
Test name
Test status
Simulation time 101278934 ps
CPU time 5.29 seconds
Started Jan 17 12:42:05 PM PST 24
Finished Jan 17 12:42:10 PM PST 24
Peak memory 236352 kb
Host smart-9c2c43eb-193c-46c1-ac34-6ce86115ad61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2316045981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2316045981
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2648008650
Short name T766
Test name
Test status
Simulation time 12911201 ps
CPU time 1.49 seconds
Started Jan 17 12:42:01 PM PST 24
Finished Jan 17 12:42:04 PM PST 24
Peak memory 235568 kb
Host smart-f5760339-4bc9-4418-acb1-91c274fad4e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2648008650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2648008650
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.924257427
Short name T822
Test name
Test status
Simulation time 920387885 ps
CPU time 12.25 seconds
Started Jan 17 12:42:07 PM PST 24
Finished Jan 17 12:42:20 PM PST 24
Peak memory 244568 kb
Host smart-42ca4e97-48d5-46b0-b021-eb00bfce9f70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=924257427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.924257427
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1459481969
Short name T147
Test name
Test status
Simulation time 4599265233 ps
CPU time 178.12 seconds
Started Jan 17 12:41:55 PM PST 24
Finished Jan 17 12:44:54 PM PST 24
Peak memory 257268 kb
Host smart-4632b240-d470-48ae-a98d-1cc11799853e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1459481969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1459481969
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2888832846
Short name T807
Test name
Test status
Simulation time 121057638 ps
CPU time 13.68 seconds
Started Jan 17 12:41:51 PM PST 24
Finished Jan 17 12:42:06 PM PST 24
Peak memory 248008 kb
Host smart-0f6b2fb7-fc7a-4f0f-9e04-b3940a594a53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2888832846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2888832846
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.609929698
Short name T742
Test name
Test status
Simulation time 96232204 ps
CPU time 6.26 seconds
Started Jan 17 12:42:06 PM PST 24
Finished Jan 17 12:42:13 PM PST 24
Peak memory 248504 kb
Host smart-1e70461b-21b2-4dc7-821a-67d5eb654798
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609929698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.609929698
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.837533525
Short name T775
Test name
Test status
Simulation time 119105908 ps
CPU time 6 seconds
Started Jan 17 12:42:04 PM PST 24
Finished Jan 17 12:42:10 PM PST 24
Peak memory 236452 kb
Host smart-06bd399f-7eb7-4455-88b8-8ff2c2971058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=837533525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.837533525
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2259769258
Short name T778
Test name
Test status
Simulation time 13151751 ps
CPU time 1.45 seconds
Started Jan 17 12:42:08 PM PST 24
Finished Jan 17 12:42:12 PM PST 24
Peak memory 236396 kb
Host smart-114aa2a1-f15a-4441-a8b3-030d0c99a3d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2259769258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2259769258
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3763302027
Short name T186
Test name
Test status
Simulation time 696151260 ps
CPU time 25.71 seconds
Started Jan 17 12:42:11 PM PST 24
Finished Jan 17 12:42:39 PM PST 24
Peak memory 248604 kb
Host smart-0fe7d408-b6e9-44bd-a429-729d3fe05836
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3763302027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3763302027
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2578566681
Short name T809
Test name
Test status
Simulation time 148877691 ps
CPU time 6.38 seconds
Started Jan 17 12:42:14 PM PST 24
Finished Jan 17 12:42:31 PM PST 24
Peak memory 240436 kb
Host smart-61a1ca50-dbe1-4033-99fb-d2303b72d12d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2578566681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2578566681
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.296038347
Short name T787
Test name
Test status
Simulation time 286832896 ps
CPU time 6.97 seconds
Started Jan 17 12:42:09 PM PST 24
Finished Jan 17 12:42:20 PM PST 24
Peak memory 253656 kb
Host smart-09621952-1314-4698-9a10-46f60972e7ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296038347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.296038347
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.4026730073
Short name T814
Test name
Test status
Simulation time 184472989 ps
CPU time 7.52 seconds
Started Jan 17 12:42:11 PM PST 24
Finished Jan 17 12:42:21 PM PST 24
Peak memory 235972 kb
Host smart-27e76477-8b62-4417-89d7-f89c9d64bb93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4026730073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.4026730073
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1236611137
Short name T794
Test name
Test status
Simulation time 6462354 ps
CPU time 1.48 seconds
Started Jan 17 12:42:06 PM PST 24
Finished Jan 17 12:42:08 PM PST 24
Peak memory 234500 kb
Host smart-8aab856c-9d2c-4a1a-a340-89ea6eb4bae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1236611137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1236611137
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.394599898
Short name T777
Test name
Test status
Simulation time 3969983984 ps
CPU time 48.35 seconds
Started Jan 17 12:42:14 PM PST 24
Finished Jan 17 12:43:12 PM PST 24
Peak memory 244560 kb
Host smart-9c3104af-5cf6-4323-974b-411592ffffb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=394599898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.394599898
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.724461946
Short name T152
Test name
Test status
Simulation time 1547645594 ps
CPU time 180.43 seconds
Started Jan 17 12:42:02 PM PST 24
Finished Jan 17 12:45:04 PM PST 24
Peak memory 265132 kb
Host smart-7c3007fa-8d65-492d-839e-4eda396934a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=724461946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.724461946
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.666027671
Short name T128
Test name
Test status
Simulation time 29775464242 ps
CPU time 943.42 seconds
Started Jan 17 12:42:08 PM PST 24
Finished Jan 17 12:57:55 PM PST 24
Peak memory 272600 kb
Host smart-61defac8-8ba4-426e-929a-22698cf5894c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666027671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.666027671
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4188153158
Short name T839
Test name
Test status
Simulation time 217794624 ps
CPU time 14.05 seconds
Started Jan 17 12:42:09 PM PST 24
Finished Jan 17 12:42:27 PM PST 24
Peak memory 248568 kb
Host smart-06d57bad-ed39-4075-9f6a-eff810d7d6d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4188153158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4188153158
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3548030256
Short name T745
Test name
Test status
Simulation time 6711410727 ps
CPU time 105.84 seconds
Started Jan 17 12:41:43 PM PST 24
Finished Jan 17 12:43:35 PM PST 24
Peak memory 240036 kb
Host smart-82deef40-4e40-452c-a4de-61d9ae873a94
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3548030256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3548030256
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3176286112
Short name T184
Test name
Test status
Simulation time 8938830100 ps
CPU time 484.89 seconds
Started Jan 17 12:41:36 PM PST 24
Finished Jan 17 12:49:43 PM PST 24
Peak memory 236332 kb
Host smart-daf7a6f9-1ff0-4bf0-be75-62971897beae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3176286112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3176286112
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1067089302
Short name T738
Test name
Test status
Simulation time 137043833 ps
CPU time 6.03 seconds
Started Jan 17 12:41:43 PM PST 24
Finished Jan 17 12:41:55 PM PST 24
Peak memory 240024 kb
Host smart-fa94bcf6-fbe5-481e-82b5-133659884cc8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1067089302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1067089302
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.99887316
Short name T222
Test name
Test status
Simulation time 47070840 ps
CPU time 2.98 seconds
Started Jan 17 12:41:33 PM PST 24
Finished Jan 17 12:41:36 PM PST 24
Peak memory 238596 kb
Host smart-feb6e1e5-1a79-4e4b-bc3c-c52a59746c41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99887316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.alert_handler_csr_mem_rw_with_rand_reset.99887316
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2541740958
Short name T818
Test name
Test status
Simulation time 102946819 ps
CPU time 3.76 seconds
Started Jan 17 12:41:41 PM PST 24
Finished Jan 17 12:41:53 PM PST 24
Peak memory 236252 kb
Host smart-938ef40e-4197-4a65-b181-cdd67d68c5b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2541740958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2541740958
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.869540226
Short name T185
Test name
Test status
Simulation time 7096711 ps
CPU time 1.34 seconds
Started Jan 17 12:41:41 PM PST 24
Finished Jan 17 12:41:50 PM PST 24
Peak memory 234512 kb
Host smart-504dd9a5-4c7b-4718-acdd-dace76935c9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=869540226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.869540226
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.590263694
Short name T788
Test name
Test status
Simulation time 490992278 ps
CPU time 37.32 seconds
Started Jan 17 12:41:27 PM PST 24
Finished Jan 17 12:42:06 PM PST 24
Peak memory 244532 kb
Host smart-76f539bb-81ac-4c9b-82f7-d3a92849b08b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=590263694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.590263694
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3273435791
Short name T130
Test name
Test status
Simulation time 2237392067 ps
CPU time 160.69 seconds
Started Jan 17 12:41:23 PM PST 24
Finished Jan 17 12:44:08 PM PST 24
Peak memory 265224 kb
Host smart-36b7b0d8-b9e1-4e6e-b839-1ab920bf3f07
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3273435791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3273435791
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3500396511
Short name T845
Test name
Test status
Simulation time 180884788 ps
CPU time 7.42 seconds
Started Jan 17 12:41:18 PM PST 24
Finished Jan 17 12:41:26 PM PST 24
Peak memory 251796 kb
Host smart-77225e7b-463e-4497-8fee-3632def0fdab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3500396511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3500396511
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3286049894
Short name T802
Test name
Test status
Simulation time 8691812 ps
CPU time 1.56 seconds
Started Jan 17 12:42:09 PM PST 24
Finished Jan 17 12:42:14 PM PST 24
Peak memory 235656 kb
Host smart-d33b90d7-c944-4a5e-8247-da622d4c657b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3286049894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3286049894
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.372151679
Short name T761
Test name
Test status
Simulation time 15326417 ps
CPU time 1.29 seconds
Started Jan 17 12:42:12 PM PST 24
Finished Jan 17 12:42:15 PM PST 24
Peak memory 236352 kb
Host smart-9e90f647-0d4b-4c9f-92a7-16f9faa605c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=372151679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.372151679
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1329625728
Short name T783
Test name
Test status
Simulation time 13114397 ps
CPU time 1.41 seconds
Started Jan 17 12:42:10 PM PST 24
Finished Jan 17 12:42:15 PM PST 24
Peak memory 236388 kb
Host smart-49cf88e5-2e83-4577-9e34-3b38458aef31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1329625728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1329625728
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.788997518
Short name T223
Test name
Test status
Simulation time 7574076 ps
CPU time 1.67 seconds
Started Jan 17 12:42:10 PM PST 24
Finished Jan 17 12:42:16 PM PST 24
Peak memory 236376 kb
Host smart-ae6077eb-9a56-4ec9-b261-ddac62fb0814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=788997518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.788997518
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2795310565
Short name T830
Test name
Test status
Simulation time 22765349 ps
CPU time 1.51 seconds
Started Jan 17 12:42:07 PM PST 24
Finished Jan 17 12:42:11 PM PST 24
Peak memory 235592 kb
Host smart-41d76d02-15f1-4542-a074-21eb6683c869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2795310565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2795310565
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.633150798
Short name T757
Test name
Test status
Simulation time 11682346 ps
CPU time 1.36 seconds
Started Jan 17 12:42:14 PM PST 24
Finished Jan 17 12:42:25 PM PST 24
Peak memory 234524 kb
Host smart-81a6b2d9-1791-4ae6-a817-140432f00706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=633150798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.633150798
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2134617534
Short name T334
Test name
Test status
Simulation time 11473957 ps
CPU time 1.32 seconds
Started Jan 17 12:42:11 PM PST 24
Finished Jan 17 12:42:15 PM PST 24
Peak memory 235528 kb
Host smart-cba687fb-0b3b-44a2-b50b-e4c94dedaf8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2134617534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2134617534
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1101359637
Short name T847
Test name
Test status
Simulation time 11968246 ps
CPU time 1.39 seconds
Started Jan 17 12:42:10 PM PST 24
Finished Jan 17 12:42:15 PM PST 24
Peak memory 235272 kb
Host smart-5ba51249-aa80-4583-a7d8-3db95caea767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1101359637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1101359637
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3119769202
Short name T804
Test name
Test status
Simulation time 10420756 ps
CPU time 1.59 seconds
Started Jan 17 12:42:07 PM PST 24
Finished Jan 17 12:42:11 PM PST 24
Peak memory 235548 kb
Host smart-86e2d1eb-45e9-44dd-ab4b-78c5b3c5617b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3119769202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3119769202
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.968127792
Short name T747
Test name
Test status
Simulation time 12308964 ps
CPU time 1.65 seconds
Started Jan 17 12:42:11 PM PST 24
Finished Jan 17 12:42:15 PM PST 24
Peak memory 236476 kb
Host smart-2353a564-bcb1-4fb0-9244-a82e6d709ffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=968127792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.968127792
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2132133197
Short name T760
Test name
Test status
Simulation time 7016156722 ps
CPU time 65.41 seconds
Started Jan 17 12:41:33 PM PST 24
Finished Jan 17 12:42:39 PM PST 24
Peak memory 236724 kb
Host smart-1b711465-24a8-4ec9-9c43-7d504c11c2b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2132133197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2132133197
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2535697267
Short name T808
Test name
Test status
Simulation time 31705932910 ps
CPU time 400.57 seconds
Started Jan 17 12:41:36 PM PST 24
Finished Jan 17 12:48:20 PM PST 24
Peak memory 236496 kb
Host smart-cf2eeda1-b1cc-4d28-b43a-8171d6ab0973
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2535697267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2535697267
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1898607037
Short name T800
Test name
Test status
Simulation time 59611250 ps
CPU time 5.91 seconds
Started Jan 17 12:41:41 PM PST 24
Finished Jan 17 12:41:55 PM PST 24
Peak memory 240288 kb
Host smart-fcc8c2e6-a067-4d3e-8511-4be41e2031b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1898607037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1898607037
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.4043002273
Short name T767
Test name
Test status
Simulation time 36452390 ps
CPU time 6.61 seconds
Started Jan 17 12:41:52 PM PST 24
Finished Jan 17 12:41:59 PM PST 24
Peak memory 242496 kb
Host smart-07cd6cd0-4815-497a-8237-1f4932c66659
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043002273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.4043002273
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3392859165
Short name T153
Test name
Test status
Simulation time 62712073 ps
CPU time 3.47 seconds
Started Jan 17 12:41:31 PM PST 24
Finished Jan 17 12:41:36 PM PST 24
Peak memory 236324 kb
Host smart-254885f9-1e78-411e-a151-7e9729dcaa54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3392859165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3392859165
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.579756751
Short name T776
Test name
Test status
Simulation time 18265375 ps
CPU time 1.43 seconds
Started Jan 17 12:41:30 PM PST 24
Finished Jan 17 12:41:33 PM PST 24
Peak memory 236312 kb
Host smart-b339bc57-26a6-45bd-a0cd-f48a02960d34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=579756751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.579756751
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.110910288
Short name T183
Test name
Test status
Simulation time 1526901152 ps
CPU time 20.92 seconds
Started Jan 17 12:41:43 PM PST 24
Finished Jan 17 12:42:10 PM PST 24
Peak memory 243472 kb
Host smart-d98aac09-e514-4413-a86e-880b383187ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=110910288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.110910288
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3077202970
Short name T160
Test name
Test status
Simulation time 3197787981 ps
CPU time 83.67 seconds
Started Jan 17 12:41:53 PM PST 24
Finished Jan 17 12:43:17 PM PST 24
Peak memory 256424 kb
Host smart-e6e8cf0e-b706-4b29-9a94-40966e10a4ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3077202970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3077202970
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.957094671
Short name T769
Test name
Test status
Simulation time 411895008 ps
CPU time 14.94 seconds
Started Jan 17 12:41:30 PM PST 24
Finished Jan 17 12:41:46 PM PST 24
Peak memory 248668 kb
Host smart-d7f7d5c0-a611-4034-9a91-bf184f3de1c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=957094671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.957094671
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1740885833
Short name T753
Test name
Test status
Simulation time 11473587 ps
CPU time 1.27 seconds
Started Jan 17 12:42:07 PM PST 24
Finished Jan 17 12:42:11 PM PST 24
Peak memory 235400 kb
Host smart-f62a46cd-0bd1-41d3-ad0f-239840cfd162
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1740885833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1740885833
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2379072726
Short name T750
Test name
Test status
Simulation time 7843699 ps
CPU time 1.51 seconds
Started Jan 17 12:42:13 PM PST 24
Finished Jan 17 12:42:22 PM PST 24
Peak memory 235588 kb
Host smart-4982952c-6518-4d8d-afeb-68d70c806970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2379072726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2379072726
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1839997445
Short name T835
Test name
Test status
Simulation time 21213933 ps
CPU time 1.32 seconds
Started Jan 17 12:42:11 PM PST 24
Finished Jan 17 12:42:15 PM PST 24
Peak memory 234552 kb
Host smart-298e94e9-a1b0-4802-88c8-72b6865d8377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1839997445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1839997445
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3976617090
Short name T768
Test name
Test status
Simulation time 6811203 ps
CPU time 1.39 seconds
Started Jan 17 12:42:15 PM PST 24
Finished Jan 17 12:42:26 PM PST 24
Peak memory 235620 kb
Host smart-3ba1b3f3-cbc4-4b2c-8187-75a1d0a0b709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3976617090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3976617090
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.923780520
Short name T795
Test name
Test status
Simulation time 10823950 ps
CPU time 1.29 seconds
Started Jan 17 12:42:08 PM PST 24
Finished Jan 17 12:42:13 PM PST 24
Peak memory 236476 kb
Host smart-7dbf854b-af59-4827-a199-1af1b10264b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=923780520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.923780520
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.402920489
Short name T799
Test name
Test status
Simulation time 23185240 ps
CPU time 1.95 seconds
Started Jan 17 12:42:05 PM PST 24
Finished Jan 17 12:42:07 PM PST 24
Peak memory 235476 kb
Host smart-7a93eccb-7f33-4a8e-a64e-ddde675ca832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=402920489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.402920489
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2819398402
Short name T798
Test name
Test status
Simulation time 7500908 ps
CPU time 1.54 seconds
Started Jan 17 12:42:09 PM PST 24
Finished Jan 17 12:42:14 PM PST 24
Peak memory 236368 kb
Host smart-fa778dcb-99a9-4b35-8803-5241045b3eea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2819398402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2819398402
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.787782109
Short name T734
Test name
Test status
Simulation time 14645392 ps
CPU time 1.49 seconds
Started Jan 17 12:42:12 PM PST 24
Finished Jan 17 12:42:15 PM PST 24
Peak memory 235456 kb
Host smart-0ccc14a6-4125-46ff-ba43-6a0a1284522e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=787782109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.787782109
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1068813766
Short name T119
Test name
Test status
Simulation time 3905604676 ps
CPU time 240.65 seconds
Started Jan 17 12:41:32 PM PST 24
Finished Jan 17 12:45:33 PM PST 24
Peak memory 240296 kb
Host smart-8ba02de4-0030-4fef-b98c-d3545a4163e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1068813766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1068813766
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3415813079
Short name T759
Test name
Test status
Simulation time 1638675795 ps
CPU time 199.79 seconds
Started Jan 17 12:41:43 PM PST 24
Finished Jan 17 12:45:09 PM PST 24
Peak memory 236284 kb
Host smart-2a009729-d8ce-4d13-8146-21eacafee914
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3415813079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3415813079
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1521682796
Short name T765
Test name
Test status
Simulation time 69296001 ps
CPU time 3.7 seconds
Started Jan 17 12:41:43 PM PST 24
Finished Jan 17 12:41:53 PM PST 24
Peak memory 240216 kb
Host smart-a41c901e-a935-4adc-95c3-31cc94123fac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1521682796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1521682796
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2299051331
Short name T786
Test name
Test status
Simulation time 37997689 ps
CPU time 4.13 seconds
Started Jan 17 12:41:51 PM PST 24
Finished Jan 17 12:41:56 PM PST 24
Peak memory 240348 kb
Host smart-e6ed473e-6ae5-4dc2-a05d-25fea704dfbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299051331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2299051331
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.711204429
Short name T790
Test name
Test status
Simulation time 115353913 ps
CPU time 5.36 seconds
Started Jan 17 12:41:32 PM PST 24
Finished Jan 17 12:41:38 PM PST 24
Peak memory 240404 kb
Host smart-5612d4c7-f7fe-413a-a84a-80a173cd3fc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=711204429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.711204429
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1445518172
Short name T34
Test name
Test status
Simulation time 6454869 ps
CPU time 1.53 seconds
Started Jan 17 12:41:43 PM PST 24
Finished Jan 17 12:41:51 PM PST 24
Peak memory 234524 kb
Host smart-d08f0514-321b-4414-a960-b035e2680041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1445518172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1445518172
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.152426390
Short name T733
Test name
Test status
Simulation time 2025510350 ps
CPU time 36.94 seconds
Started Jan 17 12:41:37 PM PST 24
Finished Jan 17 12:42:17 PM PST 24
Peak memory 244552 kb
Host smart-cd9ea46d-69e7-4c3a-b5f0-37db895ecd94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=152426390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.152426390
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1462330585
Short name T134
Test name
Test status
Simulation time 10262739867 ps
CPU time 166.1 seconds
Started Jan 17 12:41:35 PM PST 24
Finished Jan 17 12:44:25 PM PST 24
Peak memory 257144 kb
Host smart-8a005100-240e-4915-a82a-5340659c99c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1462330585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1462330585
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2313540614
Short name T163
Test name
Test status
Simulation time 125872041 ps
CPU time 17.64 seconds
Started Jan 17 12:41:30 PM PST 24
Finished Jan 17 12:41:49 PM PST 24
Peak memory 248684 kb
Host smart-59cb88f8-6489-4a9a-a59b-cb0cf37311aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2313540614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2313540614
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3812170225
Short name T337
Test name
Test status
Simulation time 6824106 ps
CPU time 1.48 seconds
Started Jan 17 12:42:10 PM PST 24
Finished Jan 17 12:42:15 PM PST 24
Peak memory 234260 kb
Host smart-652d06fd-6445-4f08-b91f-90ca23e82fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3812170225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3812170225
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.344245788
Short name T821
Test name
Test status
Simulation time 10175932 ps
CPU time 1.29 seconds
Started Jan 17 12:42:10 PM PST 24
Finished Jan 17 12:42:14 PM PST 24
Peak memory 234408 kb
Host smart-5f9441b5-2011-4d4f-9328-d6ea73e5a7d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=344245788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.344245788
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.4015714717
Short name T782
Test name
Test status
Simulation time 11603256 ps
CPU time 1.43 seconds
Started Jan 17 12:42:12 PM PST 24
Finished Jan 17 12:42:16 PM PST 24
Peak memory 235420 kb
Host smart-0ba9bca1-7fec-439d-8d02-f95b301ac448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4015714717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.4015714717
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2840894640
Short name T224
Test name
Test status
Simulation time 21046345 ps
CPU time 1.33 seconds
Started Jan 17 12:42:12 PM PST 24
Finished Jan 17 12:42:16 PM PST 24
Peak memory 236292 kb
Host smart-e0e163b8-aa57-4268-881d-d15695e7e8d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2840894640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2840894640
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3849469802
Short name T749
Test name
Test status
Simulation time 28605033 ps
CPU time 1.51 seconds
Started Jan 17 12:42:11 PM PST 24
Finished Jan 17 12:42:15 PM PST 24
Peak memory 235556 kb
Host smart-974d98e0-08ac-47a3-89dd-f690ca9e9680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3849469802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3849469802
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.482384669
Short name T758
Test name
Test status
Simulation time 18776797 ps
CPU time 1.39 seconds
Started Jan 17 12:42:14 PM PST 24
Finished Jan 17 12:42:25 PM PST 24
Peak memory 236340 kb
Host smart-fde758a6-822f-445e-9878-2d648c3f0a8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=482384669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.482384669
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3321537385
Short name T225
Test name
Test status
Simulation time 14920779 ps
CPU time 1.41 seconds
Started Jan 17 12:42:16 PM PST 24
Finished Jan 17 12:42:27 PM PST 24
Peak memory 235772 kb
Host smart-85019b16-dd92-467b-bd10-83ba3cf21c96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3321537385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3321537385
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2059729531
Short name T743
Test name
Test status
Simulation time 32891516 ps
CPU time 1.33 seconds
Started Jan 17 12:42:08 PM PST 24
Finished Jan 17 12:42:11 PM PST 24
Peak memory 235388 kb
Host smart-76a522a8-68f8-43bc-84ce-2dbadcff0684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2059729531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2059729531
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3188737849
Short name T772
Test name
Test status
Simulation time 8602895 ps
CPU time 1.39 seconds
Started Jan 17 12:42:08 PM PST 24
Finished Jan 17 12:42:12 PM PST 24
Peak memory 235532 kb
Host smart-09ce2fbf-e2c4-4f14-bb68-bb36c155d58d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3188737849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3188737849
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2544734241
Short name T740
Test name
Test status
Simulation time 13009365 ps
CPU time 1.29 seconds
Started Jan 17 12:42:16 PM PST 24
Finished Jan 17 12:42:27 PM PST 24
Peak memory 235776 kb
Host smart-a6949732-50c7-42e6-9c08-f140daba1ca3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2544734241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2544734241
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1737713151
Short name T32
Test name
Test status
Simulation time 220075785 ps
CPU time 6.22 seconds
Started Jan 17 12:41:35 PM PST 24
Finished Jan 17 12:41:43 PM PST 24
Peak memory 252060 kb
Host smart-c9c00f8f-f23d-49ae-8fcd-ab55ff147bb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737713151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1737713151
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.597161933
Short name T770
Test name
Test status
Simulation time 766408651 ps
CPU time 4.77 seconds
Started Jan 17 12:41:42 PM PST 24
Finished Jan 17 12:41:54 PM PST 24
Peak memory 235340 kb
Host smart-2776d472-c5b3-48af-8c5f-0fad7aa6263a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=597161933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.597161933
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4096490825
Short name T751
Test name
Test status
Simulation time 11587362 ps
CPU time 1.31 seconds
Started Jan 17 12:41:34 PM PST 24
Finished Jan 17 12:41:38 PM PST 24
Peak memory 236348 kb
Host smart-9f99f9ed-f07d-46cd-a250-c922d441b751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4096490825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.4096490825
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.67006643
Short name T140
Test name
Test status
Simulation time 5535004037 ps
CPU time 363.95 seconds
Started Jan 17 12:41:37 PM PST 24
Finished Jan 17 12:47:44 PM PST 24
Peak memory 265256 kb
Host smart-66b4acf5-76c2-4d2c-a551-7454261920fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=67006643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors
.67006643
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2444235106
Short name T338
Test name
Test status
Simulation time 2224774310 ps
CPU time 286.47 seconds
Started Jan 17 12:41:41 PM PST 24
Finished Jan 17 12:46:36 PM PST 24
Peak memory 265320 kb
Host smart-372c8703-5e19-441c-ad20-d8de69b4ae78
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444235106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2444235106
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3002050420
Short name T27
Test name
Test status
Simulation time 166688841 ps
CPU time 6.18 seconds
Started Jan 17 12:41:34 PM PST 24
Finished Jan 17 12:41:41 PM PST 24
Peak memory 248548 kb
Host smart-36637025-70b9-4c42-95d1-61ccc3d0f380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3002050420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3002050420
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.327031693
Short name T754
Test name
Test status
Simulation time 37526949 ps
CPU time 3.95 seconds
Started Jan 17 12:41:41 PM PST 24
Finished Jan 17 12:41:52 PM PST 24
Peak memory 248668 kb
Host smart-e4161598-948d-4051-a2d1-b7ca64b65151
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327031693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.alert_handler_csr_mem_rw_with_rand_reset.327031693
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3909811171
Short name T755
Test name
Test status
Simulation time 210752259 ps
CPU time 4.01 seconds
Started Jan 17 12:41:36 PM PST 24
Finished Jan 17 12:41:42 PM PST 24
Peak memory 235488 kb
Host smart-74250eaf-9c05-46eb-b898-a3adb5564112
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3909811171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3909811171
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2568529190
Short name T335
Test name
Test status
Simulation time 19882868 ps
CPU time 1.28 seconds
Started Jan 17 12:41:36 PM PST 24
Finished Jan 17 12:41:41 PM PST 24
Peak memory 236384 kb
Host smart-114b516b-37e2-4065-9c24-6751b7dfb8f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2568529190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2568529190
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.307055088
Short name T846
Test name
Test status
Simulation time 1932451629 ps
CPU time 22.99 seconds
Started Jan 17 12:41:51 PM PST 24
Finished Jan 17 12:42:15 PM PST 24
Peak memory 244532 kb
Host smart-4d388286-ba1c-4da8-87d9-f45a7ff02ef1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=307055088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.307055088
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1052537162
Short name T124
Test name
Test status
Simulation time 40198640409 ps
CPU time 497.78 seconds
Started Jan 17 12:41:37 PM PST 24
Finished Jan 17 12:49:57 PM PST 24
Peak memory 265312 kb
Host smart-fd04381e-8234-4210-862a-1771dfd7b09f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052537162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1052537162
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1696343625
Short name T813
Test name
Test status
Simulation time 991501182 ps
CPU time 9.17 seconds
Started Jan 17 12:41:44 PM PST 24
Finished Jan 17 12:41:58 PM PST 24
Peak memory 248572 kb
Host smart-ea900700-4e5f-495d-8c6f-08d735f7c404
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1696343625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1696343625
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1309233722
Short name T834
Test name
Test status
Simulation time 144844037 ps
CPU time 7.18 seconds
Started Jan 17 12:41:44 PM PST 24
Finished Jan 17 12:41:56 PM PST 24
Peak memory 251404 kb
Host smart-1e9158b9-250d-4c77-8a58-f738dae40892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309233722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1309233722
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3814402362
Short name T339
Test name
Test status
Simulation time 114255908 ps
CPU time 8.31 seconds
Started Jan 17 12:41:43 PM PST 24
Finished Jan 17 12:41:57 PM PST 24
Peak memory 235496 kb
Host smart-fb77c611-a645-4051-a662-80824ade4490
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3814402362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3814402362
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1815198728
Short name T841
Test name
Test status
Simulation time 6296527 ps
CPU time 1.35 seconds
Started Jan 17 12:41:53 PM PST 24
Finished Jan 17 12:41:55 PM PST 24
Peak memory 234464 kb
Host smart-9b257161-dac5-4f4d-94e3-49b2ee4fad56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1815198728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1815198728
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.661886869
Short name T815
Test name
Test status
Simulation time 1154902601 ps
CPU time 18.7 seconds
Started Jan 17 12:41:51 PM PST 24
Finished Jan 17 12:42:11 PM PST 24
Peak memory 243660 kb
Host smart-0d825df0-ecdc-4799-9695-4282ca5ce265
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=661886869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.661886869
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2408438915
Short name T791
Test name
Test status
Simulation time 810114737 ps
CPU time 9.53 seconds
Started Jan 17 12:41:33 PM PST 24
Finished Jan 17 12:41:44 PM PST 24
Peak memory 251208 kb
Host smart-da33f54d-0540-4a83-825f-7daa824f7b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2408438915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2408438915
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.711133692
Short name T840
Test name
Test status
Simulation time 2453805280 ps
CPU time 39.13 seconds
Started Jan 17 12:41:35 PM PST 24
Finished Jan 17 12:42:17 PM PST 24
Peak memory 236532 kb
Host smart-b356b375-6743-44b9-a590-eaafdfe89442
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=711133692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.711133692
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3251410330
Short name T796
Test name
Test status
Simulation time 266702966 ps
CPU time 6.61 seconds
Started Jan 17 12:41:45 PM PST 24
Finished Jan 17 12:41:56 PM PST 24
Peak memory 250600 kb
Host smart-b55e04ac-1944-4a99-ab18-84aa7aafec5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251410330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3251410330
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2773089249
Short name T748
Test name
Test status
Simulation time 65611739 ps
CPU time 3.69 seconds
Started Jan 17 12:41:41 PM PST 24
Finished Jan 17 12:41:53 PM PST 24
Peak memory 238364 kb
Host smart-70134e5e-eabc-4480-8f55-fa85de31990e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2773089249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2773089249
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.356777565
Short name T29
Test name
Test status
Simulation time 7086621 ps
CPU time 1.37 seconds
Started Jan 17 12:41:43 PM PST 24
Finished Jan 17 12:41:50 PM PST 24
Peak memory 236388 kb
Host smart-b578c728-b405-41d9-9d22-f30470bbd6c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=356777565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.356777565
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.722936450
Short name T805
Test name
Test status
Simulation time 85679236 ps
CPU time 11.85 seconds
Started Jan 17 12:41:48 PM PST 24
Finished Jan 17 12:42:02 PM PST 24
Peak memory 244820 kb
Host smart-a77d2b47-0757-415e-9bfa-3a12e3c75ff1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=722936450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.722936450
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2024457711
Short name T820
Test name
Test status
Simulation time 6019952075 ps
CPU time 104.26 seconds
Started Jan 17 12:41:53 PM PST 24
Finished Jan 17 12:43:38 PM PST 24
Peak memory 265224 kb
Host smart-7f778261-4cac-4688-a53c-10277b7f7625
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2024457711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2024457711
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2129381606
Short name T148
Test name
Test status
Simulation time 56960056604 ps
CPU time 980.71 seconds
Started Jan 17 12:41:39 PM PST 24
Finished Jan 17 12:58:02 PM PST 24
Peak memory 272528 kb
Host smart-96acc6c5-b994-4296-a4eb-98cb31033b89
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129381606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2129381606
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2555722008
Short name T771
Test name
Test status
Simulation time 124617636 ps
CPU time 4.9 seconds
Started Jan 17 12:41:41 PM PST 24
Finished Jan 17 12:41:54 PM PST 24
Peak memory 250716 kb
Host smart-4565b5be-3ad6-41f8-9ffa-51d6dae31600
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2555722008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2555722008
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.48268036
Short name T752
Test name
Test status
Simulation time 61768477 ps
CPU time 7.27 seconds
Started Jan 17 12:41:48 PM PST 24
Finished Jan 17 12:41:57 PM PST 24
Peak memory 251840 kb
Host smart-1c3d7aed-05ce-420e-b4a8-cc9c45f18e0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48268036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.alert_handler_csr_mem_rw_with_rand_reset.48268036
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3838036976
Short name T764
Test name
Test status
Simulation time 77971894 ps
CPU time 4.72 seconds
Started Jan 17 12:41:47 PM PST 24
Finished Jan 17 12:41:54 PM PST 24
Peak memory 235516 kb
Host smart-adc538d4-bc8b-45d8-8102-1916ac70c344
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3838036976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3838036976
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.117722626
Short name T827
Test name
Test status
Simulation time 7091917 ps
CPU time 1.51 seconds
Started Jan 17 12:41:52 PM PST 24
Finished Jan 17 12:41:54 PM PST 24
Peak memory 236296 kb
Host smart-8e1d1fb4-acd2-4fc0-b2d9-bbba2b355647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=117722626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.117722626
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2564411657
Short name T741
Test name
Test status
Simulation time 247387227 ps
CPU time 17.72 seconds
Started Jan 17 12:41:48 PM PST 24
Finished Jan 17 12:42:08 PM PST 24
Peak memory 240268 kb
Host smart-5f677a5d-4b0f-4650-a25a-381cb9ec9be2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2564411657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2564411657
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3892406607
Short name T156
Test name
Test status
Simulation time 16185447887 ps
CPU time 1067.06 seconds
Started Jan 17 12:41:49 PM PST 24
Finished Jan 17 12:59:39 PM PST 24
Peak memory 265328 kb
Host smart-84e59cb8-d23e-47e6-b5fd-35798b2923a7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892406607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3892406607
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1706663274
Short name T806
Test name
Test status
Simulation time 905361046 ps
CPU time 16.62 seconds
Started Jan 17 12:41:52 PM PST 24
Finished Jan 17 12:42:10 PM PST 24
Peak memory 254808 kb
Host smart-a7e56d91-5b73-4686-97fa-8ae5705ed182
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1706663274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1706663274
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1442884328
Short name T699
Test name
Test status
Simulation time 86534824692 ps
CPU time 1331.98 seconds
Started Jan 17 02:47:51 PM PST 24
Finished Jan 17 03:10:05 PM PST 24
Peak memory 272712 kb
Host smart-6a6c56cd-b855-4eb9-a5e0-1e04dc88825a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442884328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1442884328
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.4021373267
Short name T212
Test name
Test status
Simulation time 1263982029 ps
CPU time 16.06 seconds
Started Jan 17 02:48:04 PM PST 24
Finished Jan 17 02:48:21 PM PST 24
Peak memory 240392 kb
Host smart-256c9215-60d4-4482-bc2b-0e931a6d1f93
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4021373267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.4021373267
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2758355459
Short name T217
Test name
Test status
Simulation time 13551635335 ps
CPU time 119.31 seconds
Started Jan 17 02:47:51 PM PST 24
Finished Jan 17 02:49:52 PM PST 24
Peak memory 255188 kb
Host smart-4cec1bfc-1a43-4780-a0f7-a588b1c35a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27583
55459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2758355459
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2577555621
Short name T500
Test name
Test status
Simulation time 1875796415 ps
CPU time 10.64 seconds
Started Jan 17 02:47:50 PM PST 24
Finished Jan 17 02:48:03 PM PST 24
Peak memory 248092 kb
Host smart-877010ea-347f-4be1-840a-65608943b54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25775
55621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2577555621
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.942133744
Short name T638
Test name
Test status
Simulation time 44627814367 ps
CPU time 2545.24 seconds
Started Jan 17 02:47:51 PM PST 24
Finished Jan 17 03:30:18 PM PST 24
Peak memory 288784 kb
Host smart-dc63918f-f8aa-4357-b657-3a8a640eaea8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942133744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.942133744
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3060731718
Short name T619
Test name
Test status
Simulation time 17627610937 ps
CPU time 1501.74 seconds
Started Jan 17 02:48:04 PM PST 24
Finished Jan 17 03:13:07 PM PST 24
Peak memory 288592 kb
Host smart-4fc6eb5d-05da-4348-8bce-70c0eb4c51f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060731718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3060731718
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.447508388
Short name T690
Test name
Test status
Simulation time 6185136245 ps
CPU time 259.9 seconds
Started Jan 17 02:47:52 PM PST 24
Finished Jan 17 02:52:12 PM PST 24
Peak memory 246604 kb
Host smart-a8470849-16e0-477b-bb90-9bbe071300dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447508388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.447508388
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3878113736
Short name T489
Test name
Test status
Simulation time 179515829 ps
CPU time 18.89 seconds
Started Jan 17 02:47:50 PM PST 24
Finished Jan 17 02:48:11 PM PST 24
Peak memory 248668 kb
Host smart-039772ab-7f8f-4bcd-af8c-d7f92316769c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38781
13736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3878113736
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1384879006
Short name T433
Test name
Test status
Simulation time 98108978 ps
CPU time 4.68 seconds
Started Jan 17 02:47:52 PM PST 24
Finished Jan 17 02:47:57 PM PST 24
Peak memory 238724 kb
Host smart-0393659a-cf29-4ddf-9531-38f64a2ebd7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13848
79006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1384879006
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.4230840259
Short name T14
Test name
Test status
Simulation time 223108947 ps
CPU time 13.92 seconds
Started Jan 17 02:48:06 PM PST 24
Finished Jan 17 02:48:21 PM PST 24
Peak memory 278656 kb
Host smart-2f6b7dae-9b62-4bb7-915a-2b760c5deb5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4230840259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.4230840259
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2595804896
Short name T480
Test name
Test status
Simulation time 1756653941 ps
CPU time 56.15 seconds
Started Jan 17 02:47:54 PM PST 24
Finished Jan 17 02:48:51 PM PST 24
Peak memory 248920 kb
Host smart-c5f03808-b8a3-495c-bb8a-577d3c24a387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25958
04896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2595804896
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.4084431697
Short name T240
Test name
Test status
Simulation time 87867520125 ps
CPU time 2544.73 seconds
Started Jan 17 02:48:15 PM PST 24
Finished Jan 17 03:30:43 PM PST 24
Peak memory 287420 kb
Host smart-29473165-a62d-493b-b15b-7a8efe592cc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084431697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.4084431697
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3067838207
Short name T707
Test name
Test status
Simulation time 1248032502 ps
CPU time 9.24 seconds
Started Jan 17 02:48:17 PM PST 24
Finished Jan 17 02:48:27 PM PST 24
Peak memory 240460 kb
Host smart-4d52f270-dec9-461a-bcf9-fb0fa2a810e9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3067838207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3067838207
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2600139133
Short name T364
Test name
Test status
Simulation time 3840056309 ps
CPU time 263.5 seconds
Started Jan 17 02:48:08 PM PST 24
Finished Jan 17 02:52:33 PM PST 24
Peak memory 255952 kb
Host smart-aa112a6f-a22f-4b3c-9654-f6e03568ebab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26001
39133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2600139133
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3959628454
Short name T25
Test name
Test status
Simulation time 990034484 ps
CPU time 11.66 seconds
Started Jan 17 02:48:06 PM PST 24
Finished Jan 17 02:48:20 PM PST 24
Peak memory 248616 kb
Host smart-32ed8f80-28aa-474f-b913-f923c78e4994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39596
28454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3959628454
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3311545232
Short name T631
Test name
Test status
Simulation time 145814510283 ps
CPU time 2364.18 seconds
Started Jan 17 02:48:17 PM PST 24
Finished Jan 17 03:27:42 PM PST 24
Peak memory 285168 kb
Host smart-d4c21b9f-6c71-42e1-a571-33873e416fad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311545232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3311545232
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.977043458
Short name T599
Test name
Test status
Simulation time 11256251381 ps
CPU time 1085.36 seconds
Started Jan 17 02:48:17 PM PST 24
Finished Jan 17 03:06:23 PM PST 24
Peak memory 272280 kb
Host smart-9f20bee8-c8f9-47d0-82a7-e9ea6137badb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977043458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.977043458
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.382168648
Short name T552
Test name
Test status
Simulation time 51821752284 ps
CPU time 149.29 seconds
Started Jan 17 02:48:14 PM PST 24
Finished Jan 17 02:50:47 PM PST 24
Peak memory 247172 kb
Host smart-32fe15d3-ab54-402f-91d9-1036fb13a3d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382168648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.382168648
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2073702343
Short name T430
Test name
Test status
Simulation time 5168386884 ps
CPU time 78.69 seconds
Started Jan 17 02:48:08 PM PST 24
Finished Jan 17 02:49:29 PM PST 24
Peak memory 248728 kb
Host smart-4caec3be-1e56-4f4e-8083-4a4762a849b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20737
02343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2073702343
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1657967589
Short name T98
Test name
Test status
Simulation time 1543091948 ps
CPU time 50.89 seconds
Started Jan 17 02:48:07 PM PST 24
Finished Jan 17 02:48:59 PM PST 24
Peak memory 254948 kb
Host smart-68a19a8c-2029-4d35-a4b0-81f2e43da225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16579
67589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1657967589
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2474476651
Short name T12
Test name
Test status
Simulation time 1966900872 ps
CPU time 27.7 seconds
Started Jan 17 02:48:22 PM PST 24
Finished Jan 17 02:48:50 PM PST 24
Peak memory 273344 kb
Host smart-1e64a1f4-9ba9-4c9b-8dc8-56be31594c5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2474476651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2474476651
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3358133326
Short name T463
Test name
Test status
Simulation time 286899897 ps
CPU time 35.94 seconds
Started Jan 17 02:48:17 PM PST 24
Finished Jan 17 02:48:54 PM PST 24
Peak memory 247152 kb
Host smart-2e0f0e1b-e742-40c2-b797-05d1e43b7dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33581
33326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3358133326
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1633766389
Short name T385
Test name
Test status
Simulation time 806476085 ps
CPU time 44.27 seconds
Started Jan 17 02:48:07 PM PST 24
Finished Jan 17 02:48:53 PM PST 24
Peak memory 248600 kb
Host smart-807c5ad7-def9-493a-83ba-7f9bef7f016e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16337
66389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1633766389
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.4134087309
Short name T117
Test name
Test status
Simulation time 14567381419 ps
CPU time 1092.25 seconds
Started Jan 17 02:48:15 PM PST 24
Finished Jan 17 03:06:30 PM PST 24
Peak memory 273228 kb
Host smart-ece8fc5e-cce8-4fcc-b1f9-b783d07db950
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134087309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.4134087309
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3070666514
Short name T61
Test name
Test status
Simulation time 85329319258 ps
CPU time 1786.93 seconds
Started Jan 17 02:48:29 PM PST 24
Finished Jan 17 03:18:16 PM PST 24
Peak memory 287212 kb
Host smart-f0cd5603-2271-4d24-8db4-ae0bc00e3804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070666514 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3070666514
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3716531167
Short name T204
Test name
Test status
Simulation time 40382005 ps
CPU time 3.74 seconds
Started Jan 17 02:50:26 PM PST 24
Finished Jan 17 02:50:31 PM PST 24
Peak memory 248828 kb
Host smart-5a681515-fc83-4502-be31-c90f8674f668
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3716531167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3716531167
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3562447178
Short name T451
Test name
Test status
Simulation time 18365269805 ps
CPU time 1620.04 seconds
Started Jan 17 02:50:18 PM PST 24
Finished Jan 17 03:17:18 PM PST 24
Peak memory 289308 kb
Host smart-c6e92ac7-2937-4f36-9926-7ed102a80353
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562447178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3562447178
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3778815785
Short name T444
Test name
Test status
Simulation time 939937716 ps
CPU time 11.95 seconds
Started Jan 17 02:50:26 PM PST 24
Finished Jan 17 02:50:39 PM PST 24
Peak memory 240476 kb
Host smart-25c6e6e1-d673-4301-9aa0-d71f7475de96
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3778815785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3778815785
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3768291240
Short name T711
Test name
Test status
Simulation time 1861154130 ps
CPU time 105.09 seconds
Started Jan 17 02:50:15 PM PST 24
Finished Jan 17 02:52:01 PM PST 24
Peak memory 256132 kb
Host smart-bf0062c1-897f-4d73-8780-c9cea30fd4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37682
91240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3768291240
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3980728443
Short name T383
Test name
Test status
Simulation time 1275399335 ps
CPU time 71.16 seconds
Started Jan 17 02:50:18 PM PST 24
Finished Jan 17 02:51:29 PM PST 24
Peak memory 255488 kb
Host smart-ded5c5fc-e472-491a-a6ed-1a2e5216add6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39807
28443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3980728443
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2150546766
Short name T685
Test name
Test status
Simulation time 57566776474 ps
CPU time 1421.86 seconds
Started Jan 17 02:50:17 PM PST 24
Finished Jan 17 03:14:00 PM PST 24
Peak memory 289084 kb
Host smart-4d269945-e1f7-4933-854f-b29abce9d262
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150546766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2150546766
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.813755182
Short name T515
Test name
Test status
Simulation time 29442144659 ps
CPU time 1347.95 seconds
Started Jan 17 02:50:27 PM PST 24
Finished Jan 17 03:12:56 PM PST 24
Peak memory 289312 kb
Host smart-06611520-d324-4f6e-86a6-e22fc1f926e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813755182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.813755182
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.4294153286
Short name T210
Test name
Test status
Simulation time 3944796282 ps
CPU time 64.36 seconds
Started Jan 17 02:50:16 PM PST 24
Finished Jan 17 02:51:21 PM PST 24
Peak memory 248668 kb
Host smart-c5bbdfbb-b843-45b9-bd81-0707086f5a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42941
53286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.4294153286
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2985893916
Short name T232
Test name
Test status
Simulation time 630033594 ps
CPU time 10.87 seconds
Started Jan 17 02:50:18 PM PST 24
Finished Jan 17 02:50:30 PM PST 24
Peak memory 248684 kb
Host smart-088b5309-69eb-4faa-b51a-e4877c729c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29858
93916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2985893916
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.4232537348
Short name T687
Test name
Test status
Simulation time 201762837 ps
CPU time 14.03 seconds
Started Jan 17 02:50:08 PM PST 24
Finished Jan 17 02:50:22 PM PST 24
Peak memory 248668 kb
Host smart-6e4acc40-5944-43b4-ba3e-acfb6f3fd545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42325
37348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.4232537348
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.371239194
Short name T553
Test name
Test status
Simulation time 7760120991 ps
CPU time 688.21 seconds
Started Jan 17 02:50:26 PM PST 24
Finished Jan 17 03:01:56 PM PST 24
Peak memory 265088 kb
Host smart-753f9db5-8fad-4c01-b7bc-c97a7e8f5000
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371239194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.371239194
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1154349233
Short name T75
Test name
Test status
Simulation time 161270329969 ps
CPU time 1983.55 seconds
Started Jan 17 02:50:25 PM PST 24
Finished Jan 17 03:23:29 PM PST 24
Peak memory 281576 kb
Host smart-24a42607-b951-45d2-838b-d8bd2539909e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154349233 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1154349233
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.4293080554
Short name T673
Test name
Test status
Simulation time 40362701649 ps
CPU time 2077.51 seconds
Started Jan 17 02:50:33 PM PST 24
Finished Jan 17 03:25:13 PM PST 24
Peak memory 285064 kb
Host smart-e3358216-fc64-4cf6-811b-b55b49bd663b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293080554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.4293080554
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.4093602884
Short name T651
Test name
Test status
Simulation time 446593675 ps
CPU time 20.84 seconds
Started Jan 17 02:50:40 PM PST 24
Finished Jan 17 02:51:02 PM PST 24
Peak memory 240484 kb
Host smart-78540c77-e955-4063-9dfe-5cd532f558b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4093602884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.4093602884
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3871374170
Short name T528
Test name
Test status
Simulation time 765132183 ps
CPU time 53.66 seconds
Started Jan 17 02:50:32 PM PST 24
Finished Jan 17 02:51:29 PM PST 24
Peak memory 247876 kb
Host smart-e850be5f-7cc9-4437-81f0-252f363b5d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38713
74170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3871374170
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3544604640
Short name T389
Test name
Test status
Simulation time 1761202824 ps
CPU time 43.59 seconds
Started Jan 17 02:50:33 PM PST 24
Finished Jan 17 02:51:19 PM PST 24
Peak memory 254172 kb
Host smart-d0048eff-e3ee-4d40-981a-c44d2d338858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35446
04640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3544604640
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3474895842
Short name T615
Test name
Test status
Simulation time 34717798184 ps
CPU time 699.99 seconds
Started Jan 17 02:50:32 PM PST 24
Finished Jan 17 03:02:15 PM PST 24
Peak memory 265120 kb
Host smart-f9cab52a-883a-4171-8f0a-6c746fe421b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474895842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3474895842
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1137322831
Short name T367
Test name
Test status
Simulation time 23759594328 ps
CPU time 971.92 seconds
Started Jan 17 02:50:33 PM PST 24
Finished Jan 17 03:06:47 PM PST 24
Peak memory 283412 kb
Host smart-f40f3950-dbd0-44b4-9d22-c0778b668b9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137322831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1137322831
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1658429287
Short name T298
Test name
Test status
Simulation time 27441653858 ps
CPU time 302.31 seconds
Started Jan 17 02:50:32 PM PST 24
Finished Jan 17 02:55:37 PM PST 24
Peak memory 247300 kb
Host smart-daa129a7-b95a-4eb5-8511-51839dab055b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658429287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1658429287
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.755962977
Short name T435
Test name
Test status
Simulation time 584624547 ps
CPU time 15 seconds
Started Jan 17 02:50:33 PM PST 24
Finished Jan 17 02:50:50 PM PST 24
Peak memory 248684 kb
Host smart-2d10c500-29e5-459f-aa88-748179be631e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75596
2977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.755962977
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2484162162
Short name T84
Test name
Test status
Simulation time 767394664 ps
CPU time 28.54 seconds
Started Jan 17 02:50:32 PM PST 24
Finished Jan 17 02:51:04 PM PST 24
Peak memory 248396 kb
Host smart-71f0fa43-52d7-400a-98d7-45a9c2567dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24841
62162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2484162162
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2643858660
Short name T659
Test name
Test status
Simulation time 1785093335 ps
CPU time 28.29 seconds
Started Jan 17 02:50:32 PM PST 24
Finished Jan 17 02:51:03 PM PST 24
Peak memory 248676 kb
Host smart-42ea152c-5295-4615-8355-3183f2a7f0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26438
58660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2643858660
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2856516924
Short name T541
Test name
Test status
Simulation time 245768894002 ps
CPU time 1964.46 seconds
Started Jan 17 02:50:39 PM PST 24
Finished Jan 17 03:23:25 PM PST 24
Peak memory 289496 kb
Host smart-0f591dbd-8a65-40d9-ab83-ffa151325ca1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856516924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2856516924
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.18526236
Short name T118
Test name
Test status
Simulation time 48216755059 ps
CPU time 1849.96 seconds
Started Jan 17 02:50:40 PM PST 24
Finished Jan 17 03:21:31 PM PST 24
Peak memory 288952 kb
Host smart-b1e837a5-6dd3-45a5-9963-67357e9e20f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18526236 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.18526236
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2575927541
Short name T192
Test name
Test status
Simulation time 785257776 ps
CPU time 4.34 seconds
Started Jan 17 02:50:47 PM PST 24
Finished Jan 17 02:50:54 PM PST 24
Peak memory 248908 kb
Host smart-6c9b23d0-31b4-46e1-b0c9-4f6ccfb76a15
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2575927541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2575927541
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.712146817
Short name T611
Test name
Test status
Simulation time 74165471708 ps
CPU time 1516.14 seconds
Started Jan 17 02:50:48 PM PST 24
Finished Jan 17 03:16:06 PM PST 24
Peak memory 272312 kb
Host smart-5db6262b-8545-4706-a601-b2be15660dbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712146817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.712146817
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2365169623
Short name T381
Test name
Test status
Simulation time 1337035969 ps
CPU time 12.63 seconds
Started Jan 17 02:50:47 PM PST 24
Finished Jan 17 02:51:01 PM PST 24
Peak memory 240420 kb
Host smart-782d6d3c-4133-4dbe-aee1-5f107ebbde61
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2365169623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2365169623
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2787885803
Short name T112
Test name
Test status
Simulation time 220621475 ps
CPU time 12.25 seconds
Started Jan 17 02:50:49 PM PST 24
Finished Jan 17 02:51:03 PM PST 24
Peak memory 248248 kb
Host smart-fd3e38eb-8a08-43e9-a01f-21114523347e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27878
85803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2787885803
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3724758991
Short name T71
Test name
Test status
Simulation time 2896946204 ps
CPU time 43.9 seconds
Started Jan 17 02:50:47 PM PST 24
Finished Jan 17 02:51:33 PM PST 24
Peak memory 254608 kb
Host smart-30d47bef-4f0a-4337-8471-1566d57b8c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37247
58991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3724758991
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1800656048
Short name T332
Test name
Test status
Simulation time 14219264172 ps
CPU time 1388.02 seconds
Started Jan 17 02:50:48 PM PST 24
Finished Jan 17 03:13:58 PM PST 24
Peak memory 288936 kb
Host smart-4f43d6f9-28b9-4d01-a47e-6a7d16fe13b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800656048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1800656048
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2887039061
Short name T548
Test name
Test status
Simulation time 11476155233 ps
CPU time 1080.05 seconds
Started Jan 17 02:50:46 PM PST 24
Finished Jan 17 03:08:47 PM PST 24
Peak memory 272288 kb
Host smart-44146050-a0c9-4dcc-8cf1-328850b7903a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887039061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2887039061
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.938608817
Short name T297
Test name
Test status
Simulation time 18629975707 ps
CPU time 205.68 seconds
Started Jan 17 02:50:50 PM PST 24
Finished Jan 17 02:54:17 PM PST 24
Peak memory 247288 kb
Host smart-4a9d8187-ff64-4bfa-bd93-c8f0387bfa02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938608817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.938608817
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1942093349
Short name T420
Test name
Test status
Simulation time 808492177 ps
CPU time 24.37 seconds
Started Jan 17 02:50:40 PM PST 24
Finished Jan 17 02:51:05 PM PST 24
Peak memory 248656 kb
Host smart-562fabcc-4adf-4c28-aef5-139c82233edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19420
93349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1942093349
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1073577831
Short name T103
Test name
Test status
Simulation time 1318926673 ps
CPU time 50.83 seconds
Started Jan 17 02:50:41 PM PST 24
Finished Jan 17 02:51:32 PM PST 24
Peak memory 255464 kb
Host smart-eb80b7f7-38c3-49f2-9dc9-e7c76245b2d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10735
77831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1073577831
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2689534063
Short name T402
Test name
Test status
Simulation time 966255888 ps
CPU time 57.04 seconds
Started Jan 17 02:50:50 PM PST 24
Finished Jan 17 02:51:49 PM PST 24
Peak memory 255176 kb
Host smart-2339b27f-a74a-4d16-b9ab-f4cef693b03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26895
34063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2689534063
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2410310891
Short name T616
Test name
Test status
Simulation time 4156607539 ps
CPU time 64.5 seconds
Started Jan 17 02:50:41 PM PST 24
Finished Jan 17 02:51:46 PM PST 24
Peak memory 248732 kb
Host smart-e78a872f-3098-4f27-9f43-5a6fdb9833ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24103
10891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2410310891
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.47426955
Short name T3
Test name
Test status
Simulation time 3661367787 ps
CPU time 78.16 seconds
Started Jan 17 02:50:47 PM PST 24
Finished Jan 17 02:52:06 PM PST 24
Peak memory 256868 kb
Host smart-fb5a3bba-0834-4426-a99a-aafa336c1cde
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47426955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_hand
ler_stress_all.47426955
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3994175011
Short name T63
Test name
Test status
Simulation time 30617452098 ps
CPU time 2060.74 seconds
Started Jan 17 02:50:56 PM PST 24
Finished Jan 17 03:25:19 PM PST 24
Peak memory 288480 kb
Host smart-004738f7-757d-4d3e-8e49-2b7609a2cdfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994175011 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3994175011
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.4010917473
Short name T621
Test name
Test status
Simulation time 13373403014 ps
CPU time 1247.12 seconds
Started Jan 17 02:50:56 PM PST 24
Finished Jan 17 03:11:45 PM PST 24
Peak memory 285676 kb
Host smart-cf3f68cd-263b-44c4-a712-5bebeef6eeba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010917473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.4010917473
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3257697609
Short name T361
Test name
Test status
Simulation time 780521227 ps
CPU time 35.14 seconds
Started Jan 17 02:51:02 PM PST 24
Finished Jan 17 02:51:38 PM PST 24
Peak memory 240472 kb
Host smart-78cff67e-62ee-49c8-b15e-8984a3026df2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3257697609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3257697609
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3172378934
Short name T714
Test name
Test status
Simulation time 1018086312 ps
CPU time 65.66 seconds
Started Jan 17 02:50:56 PM PST 24
Finished Jan 17 02:52:04 PM PST 24
Peak memory 247908 kb
Host smart-66960228-5cd5-4a31-bcbe-ee28a283cc1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31723
78934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3172378934
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.241583515
Short name T349
Test name
Test status
Simulation time 154323542 ps
CPU time 12.52 seconds
Started Jan 17 02:50:58 PM PST 24
Finished Jan 17 02:51:11 PM PST 24
Peak memory 253344 kb
Host smart-449a99c3-9054-43d9-8827-6a7095b9f881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24158
3515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.241583515
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.60415452
Short name T277
Test name
Test status
Simulation time 39288299409 ps
CPU time 1487.92 seconds
Started Jan 17 02:51:02 PM PST 24
Finished Jan 17 03:15:51 PM PST 24
Peak memory 289000 kb
Host smart-c649f4a7-db19-40d2-a3d1-2f8820d4e194
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60415452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.60415452
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2028079496
Short name T487
Test name
Test status
Simulation time 53866703150 ps
CPU time 1654.63 seconds
Started Jan 17 02:51:03 PM PST 24
Finished Jan 17 03:18:39 PM PST 24
Peak memory 272948 kb
Host smart-11e6533a-427f-4336-9325-261ab81d8755
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028079496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2028079496
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2944663878
Short name T377
Test name
Test status
Simulation time 65515114 ps
CPU time 5.26 seconds
Started Jan 17 02:50:57 PM PST 24
Finished Jan 17 02:51:03 PM PST 24
Peak memory 240384 kb
Host smart-1db199d3-68aa-4086-8031-0a67b34d1707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29446
63878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2944663878
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2012271330
Short name T50
Test name
Test status
Simulation time 390813805 ps
CPU time 27.02 seconds
Started Jan 17 02:50:56 PM PST 24
Finished Jan 17 02:51:25 PM PST 24
Peak memory 247160 kb
Host smart-35e089cb-cb16-417f-a540-21a2c3ca6217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20122
71330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2012271330
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.4170928421
Short name T36
Test name
Test status
Simulation time 772746597 ps
CPU time 43.33 seconds
Started Jan 17 02:50:57 PM PST 24
Finished Jan 17 02:51:41 PM PST 24
Peak memory 254832 kb
Host smart-f9c19cf8-7c5c-4910-b420-1dc3b03d4969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41709
28421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.4170928421
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3602800802
Short name T680
Test name
Test status
Simulation time 2089728622 ps
CPU time 34.07 seconds
Started Jan 17 02:50:55 PM PST 24
Finished Jan 17 02:51:32 PM PST 24
Peak memory 248592 kb
Host smart-4b693aeb-7893-415f-8e44-899ab99795fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36028
00802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3602800802
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1297001162
Short name T590
Test name
Test status
Simulation time 21178951237 ps
CPU time 2194.87 seconds
Started Jan 17 02:51:04 PM PST 24
Finished Jan 17 03:27:40 PM PST 24
Peak memory 306016 kb
Host smart-e9d10d77-3c2c-46a8-8e59-cdbe5efccde0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297001162 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1297001162
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3009144191
Short name T201
Test name
Test status
Simulation time 54724339 ps
CPU time 4.14 seconds
Started Jan 17 02:51:22 PM PST 24
Finished Jan 17 02:51:28 PM PST 24
Peak memory 248664 kb
Host smart-2a9441b6-f7d3-4993-b933-063a46cef8b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3009144191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3009144191
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.486017986
Short name T582
Test name
Test status
Simulation time 93724118151 ps
CPU time 1427.37 seconds
Started Jan 17 02:51:14 PM PST 24
Finished Jan 17 03:15:02 PM PST 24
Peak memory 268204 kb
Host smart-c74037e0-98a2-4f7d-9c64-0828a002432e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486017986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.486017986
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2142186136
Short name T345
Test name
Test status
Simulation time 732250260 ps
CPU time 33.39 seconds
Started Jan 17 02:51:15 PM PST 24
Finished Jan 17 02:51:48 PM PST 24
Peak memory 240720 kb
Host smart-801f3b8b-98aa-4127-a6e5-22d12d806de5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2142186136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2142186136
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2666167547
Short name T449
Test name
Test status
Simulation time 643518767 ps
CPU time 41.27 seconds
Started Jan 17 02:51:15 PM PST 24
Finished Jan 17 02:51:57 PM PST 24
Peak memory 248896 kb
Host smart-9e8c4d04-83ff-42fa-97f3-b05fc4ab350e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26661
67547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2666167547
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3955055994
Short name T436
Test name
Test status
Simulation time 515165428 ps
CPU time 11.65 seconds
Started Jan 17 02:51:16 PM PST 24
Finished Jan 17 02:51:29 PM PST 24
Peak memory 248264 kb
Host smart-64cd0fe6-8d67-4ea5-97a2-e8d8f0f4562c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39550
55994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3955055994
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2599965919
Short name T315
Test name
Test status
Simulation time 46698361745 ps
CPU time 2655.36 seconds
Started Jan 17 02:51:18 PM PST 24
Finished Jan 17 03:35:34 PM PST 24
Peak memory 289236 kb
Host smart-de09f3e4-55b9-4a42-ac7b-f7d57a08aaeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599965919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2599965919
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.633764646
Short name T468
Test name
Test status
Simulation time 108203419509 ps
CPU time 1622.75 seconds
Started Jan 17 02:51:17 PM PST 24
Finished Jan 17 03:18:21 PM PST 24
Peak memory 289196 kb
Host smart-e1f5449a-5dea-4f80-9952-dbcc4a8a7e63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633764646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.633764646
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1380387069
Short name T672
Test name
Test status
Simulation time 32619831593 ps
CPU time 371.89 seconds
Started Jan 17 02:51:15 PM PST 24
Finished Jan 17 02:57:28 PM PST 24
Peak memory 247620 kb
Host smart-432edb7a-2a3d-42ea-bcc8-f9fbd7ad6b87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380387069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1380387069
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2658320054
Short name T647
Test name
Test status
Simulation time 1661422687 ps
CPU time 25.99 seconds
Started Jan 17 02:51:02 PM PST 24
Finished Jan 17 02:51:29 PM PST 24
Peak memory 248688 kb
Host smart-767646ab-3267-408a-8d98-614505f290cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26583
20054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2658320054
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2727787426
Short name T411
Test name
Test status
Simulation time 1007692698 ps
CPU time 16.67 seconds
Started Jan 17 02:51:03 PM PST 24
Finished Jan 17 02:51:20 PM PST 24
Peak memory 254348 kb
Host smart-274ea3f0-da20-45a9-a93b-bf331de7bf1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27277
87426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2727787426
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2137896722
Short name T450
Test name
Test status
Simulation time 857150257 ps
CPU time 54.08 seconds
Started Jan 17 02:51:16 PM PST 24
Finished Jan 17 02:52:10 PM PST 24
Peak memory 255636 kb
Host smart-3c89047a-ffc2-408f-b950-d96ac14e728c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21378
96722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2137896722
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.68351870
Short name T695
Test name
Test status
Simulation time 611697966 ps
CPU time 11.58 seconds
Started Jan 17 02:51:01 PM PST 24
Finished Jan 17 02:51:14 PM PST 24
Peak memory 253344 kb
Host smart-6d2aae4d-1cce-4b9b-a919-2247e2b0ac54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68351
870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.68351870
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.28320632
Short name T363
Test name
Test status
Simulation time 194356512414 ps
CPU time 2583.87 seconds
Started Jan 17 02:51:15 PM PST 24
Finished Jan 17 03:34:20 PM PST 24
Peak memory 288756 kb
Host smart-197d1352-fe49-407a-ac08-5bb997904981
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28320632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_hand
ler_stress_all.28320632
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3299448007
Short name T251
Test name
Test status
Simulation time 24548102506 ps
CPU time 2468.39 seconds
Started Jan 17 02:51:16 PM PST 24
Finished Jan 17 03:32:25 PM PST 24
Peak memory 289820 kb
Host smart-70bbf759-b22f-49f7-a9c0-47452db7be17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299448007 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3299448007
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2387814403
Short name T198
Test name
Test status
Simulation time 26377430 ps
CPU time 2.69 seconds
Started Jan 17 02:51:31 PM PST 24
Finished Jan 17 02:51:36 PM PST 24
Peak memory 248556 kb
Host smart-7ccf2977-435f-47d2-b9d6-25ece7746740
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2387814403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2387814403
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2580336208
Short name T465
Test name
Test status
Simulation time 8971114456 ps
CPU time 954.34 seconds
Started Jan 17 02:51:23 PM PST 24
Finished Jan 17 03:07:18 PM PST 24
Peak memory 268216 kb
Host smart-46018b54-f570-4051-aa82-eea8199656dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580336208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2580336208
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3332925304
Short name T662
Test name
Test status
Simulation time 382824327 ps
CPU time 8.84 seconds
Started Jan 17 02:51:32 PM PST 24
Finished Jan 17 02:51:42 PM PST 24
Peak memory 240724 kb
Host smart-a5bf5825-bbd9-41d6-a95d-054c26d52a7f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3332925304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3332925304
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3997911330
Short name T209
Test name
Test status
Simulation time 33025209946 ps
CPU time 222.27 seconds
Started Jan 17 02:51:25 PM PST 24
Finished Jan 17 02:55:16 PM PST 24
Peak memory 255852 kb
Host smart-6b0d85f3-ba0f-4722-b7cd-b6023e3b87dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39979
11330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3997911330
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2137947273
Short name T534
Test name
Test status
Simulation time 152002368 ps
CPU time 14.72 seconds
Started Jan 17 02:51:17 PM PST 24
Finished Jan 17 02:51:32 PM PST 24
Peak memory 254276 kb
Host smart-a40f84c7-0608-4c51-bd06-c7602ce1afff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21379
47273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2137947273
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2435566693
Short name T561
Test name
Test status
Simulation time 101402919348 ps
CPU time 1609.84 seconds
Started Jan 17 02:51:34 PM PST 24
Finished Jan 17 03:18:25 PM PST 24
Peak memory 265124 kb
Host smart-8aecc7f2-5a19-4c1d-a2f6-ce83ef1874d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435566693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2435566693
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1547686487
Short name T597
Test name
Test status
Simulation time 12689875636 ps
CPU time 1346.8 seconds
Started Jan 17 02:51:29 PM PST 24
Finished Jan 17 03:14:00 PM PST 24
Peak memory 284788 kb
Host smart-2ff890ff-e0f4-4f84-9821-531400f64289
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547686487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1547686487
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3919732263
Short name T598
Test name
Test status
Simulation time 11137596696 ps
CPU time 235.02 seconds
Started Jan 17 02:51:27 PM PST 24
Finished Jan 17 02:55:28 PM PST 24
Peak memory 247548 kb
Host smart-d64ac9e7-c445-4130-b2e4-e6befb267ac5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919732263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3919732263
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3379908245
Short name T697
Test name
Test status
Simulation time 660041967 ps
CPU time 12.74 seconds
Started Jan 17 02:51:16 PM PST 24
Finished Jan 17 02:51:29 PM PST 24
Peak memory 248572 kb
Host smart-e2a221ec-9e89-40d5-8ed8-9a1b7d38a005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33799
08245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3379908245
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2821013263
Short name T369
Test name
Test status
Simulation time 293290028 ps
CPU time 8.64 seconds
Started Jan 17 02:51:17 PM PST 24
Finished Jan 17 02:51:26 PM PST 24
Peak memory 246912 kb
Host smart-83fd5b6c-3982-4268-91c5-22fd6a626e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28210
13263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2821013263
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2216752333
Short name T245
Test name
Test status
Simulation time 3278486877 ps
CPU time 50.32 seconds
Started Jan 17 02:51:23 PM PST 24
Finished Jan 17 02:52:14 PM PST 24
Peak memory 248728 kb
Host smart-524285d4-3837-415d-aae3-853d42d82a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22167
52333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2216752333
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2060907910
Short name T508
Test name
Test status
Simulation time 258736543 ps
CPU time 16.57 seconds
Started Jan 17 02:51:16 PM PST 24
Finished Jan 17 02:51:33 PM PST 24
Peak memory 248512 kb
Host smart-66147dbb-91c6-4bb9-a0df-0eb6545a8d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20609
07910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2060907910
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2201472604
Short name T94
Test name
Test status
Simulation time 61336441142 ps
CPU time 2201.91 seconds
Started Jan 17 02:51:31 PM PST 24
Finished Jan 17 03:28:16 PM PST 24
Peak memory 286252 kb
Host smart-9257680a-5b02-408c-86fc-1674246742c8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201472604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2201472604
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2505746102
Short name T196
Test name
Test status
Simulation time 109605057 ps
CPU time 3.43 seconds
Started Jan 17 02:51:48 PM PST 24
Finished Jan 17 02:51:55 PM PST 24
Peak memory 248920 kb
Host smart-48d73d8d-8ad1-4554-b826-2f9f6156a38e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2505746102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2505746102
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.4050755255
Short name T464
Test name
Test status
Simulation time 14888853766 ps
CPU time 1362.29 seconds
Started Jan 17 02:51:41 PM PST 24
Finished Jan 17 03:14:23 PM PST 24
Peak memory 289184 kb
Host smart-0f00cc96-799d-450c-bc10-d8ab8654d034
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050755255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.4050755255
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2072628411
Short name T664
Test name
Test status
Simulation time 160225993 ps
CPU time 10.14 seconds
Started Jan 17 02:51:50 PM PST 24
Finished Jan 17 02:52:02 PM PST 24
Peak memory 248608 kb
Host smart-d7ada960-b4a1-46cd-9eed-d0f19964265d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2072628411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2072628411
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3371130007
Short name T467
Test name
Test status
Simulation time 1125216878 ps
CPU time 98.61 seconds
Started Jan 17 02:51:31 PM PST 24
Finished Jan 17 02:53:12 PM PST 24
Peak memory 255696 kb
Host smart-3050bcb4-972f-4c51-b2b4-5df4d9e5faeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33711
30007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3371130007
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2908331951
Short name T45
Test name
Test status
Simulation time 761543367 ps
CPU time 12.99 seconds
Started Jan 17 02:51:30 PM PST 24
Finished Jan 17 02:51:47 PM PST 24
Peak memory 252076 kb
Host smart-b875805b-a96b-4469-b41c-e2a912bda8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29083
31951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2908331951
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3199851727
Short name T304
Test name
Test status
Simulation time 104800394149 ps
CPU time 2546.17 seconds
Started Jan 17 02:51:40 PM PST 24
Finished Jan 17 03:34:07 PM PST 24
Peak memory 283068 kb
Host smart-13bf5df1-2569-4d2b-89e8-c9ae31c4faaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199851727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3199851727
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3885343336
Short name T343
Test name
Test status
Simulation time 41068544693 ps
CPU time 944.31 seconds
Started Jan 17 02:51:47 PM PST 24
Finished Jan 17 03:07:36 PM PST 24
Peak memory 265096 kb
Host smart-5cd2b42a-8a42-47ce-83d9-4913dedd1d43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885343336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3885343336
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1629472083
Short name T520
Test name
Test status
Simulation time 512295263 ps
CPU time 33.21 seconds
Started Jan 17 02:51:29 PM PST 24
Finished Jan 17 02:52:07 PM PST 24
Peak memory 248812 kb
Host smart-9ad18ce2-0840-457a-b29a-4aa981531543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16294
72083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1629472083
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2856649323
Short name T69
Test name
Test status
Simulation time 4183909699 ps
CPU time 57.19 seconds
Started Jan 17 02:51:30 PM PST 24
Finished Jan 17 02:52:31 PM PST 24
Peak memory 255664 kb
Host smart-2bcafefa-b626-4265-a611-d6d97bf0e58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28566
49323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2856649323
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3971185311
Short name T22
Test name
Test status
Simulation time 1340516529 ps
CPU time 22.25 seconds
Started Jan 17 02:51:41 PM PST 24
Finished Jan 17 02:52:04 PM PST 24
Peak memory 254416 kb
Host smart-fb3496d5-ec29-4191-9c18-62150ff6759c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39711
85311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3971185311
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3713963807
Short name T518
Test name
Test status
Simulation time 2047270196 ps
CPU time 67.94 seconds
Started Jan 17 02:51:30 PM PST 24
Finished Jan 17 02:52:42 PM PST 24
Peak memory 248676 kb
Host smart-ddbc9cfb-d826-48cf-992b-1a083a707cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37139
63807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3713963807
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1776305646
Short name T105
Test name
Test status
Simulation time 50822003761 ps
CPU time 1882.86 seconds
Started Jan 17 02:51:49 PM PST 24
Finished Jan 17 03:23:14 PM PST 24
Peak memory 282912 kb
Host smart-39ac7a52-620c-49a5-9dac-d11976a0abfb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776305646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1776305646
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.884463299
Short name T498
Test name
Test status
Simulation time 48156377458 ps
CPU time 5651.17 seconds
Started Jan 17 02:51:45 PM PST 24
Finished Jan 17 04:25:58 PM PST 24
Peak memory 355092 kb
Host smart-4cd3c6ce-5031-4b00-a911-fbc11444fdd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884463299 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.884463299
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3770171024
Short name T206
Test name
Test status
Simulation time 46929854 ps
CPU time 4.11 seconds
Started Jan 17 02:52:01 PM PST 24
Finished Jan 17 02:52:09 PM PST 24
Peak memory 248828 kb
Host smart-1a24da74-37e0-449b-8dfb-725ffed7294c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3770171024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3770171024
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3228537873
Short name T382
Test name
Test status
Simulation time 233202260077 ps
CPU time 1686.36 seconds
Started Jan 17 02:52:00 PM PST 24
Finished Jan 17 03:20:11 PM PST 24
Peak memory 288684 kb
Host smart-550ac579-b723-400c-b7b1-6ed0ac03bb95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228537873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3228537873
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.4229069266
Short name T538
Test name
Test status
Simulation time 1466199855 ps
CPU time 10.33 seconds
Started Jan 17 02:52:01 PM PST 24
Finished Jan 17 02:52:15 PM PST 24
Peak memory 248544 kb
Host smart-c9f57dfa-0e28-4228-9e71-5dddeea81138
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4229069266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.4229069266
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2982550814
Short name T640
Test name
Test status
Simulation time 435027966 ps
CPU time 15.06 seconds
Started Jan 17 02:51:57 PM PST 24
Finished Jan 17 02:52:20 PM PST 24
Peak memory 248116 kb
Host smart-fbbf656f-0b33-4f62-9fe3-c8a105a89f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29825
50814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2982550814
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.274891668
Short name T460
Test name
Test status
Simulation time 304643567 ps
CPU time 24.02 seconds
Started Jan 17 02:52:00 PM PST 24
Finished Jan 17 02:52:29 PM PST 24
Peak memory 248644 kb
Host smart-d33d5219-918b-4687-9ad9-5f8d9dd55a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27489
1668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.274891668
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2248030433
Short name T101
Test name
Test status
Simulation time 33305628818 ps
CPU time 1390.64 seconds
Started Jan 17 02:51:57 PM PST 24
Finished Jan 17 03:15:16 PM PST 24
Peak memory 284748 kb
Host smart-5c7ceb12-391e-46c6-ac89-f8011b95e36d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248030433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2248030433
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1973495480
Short name T677
Test name
Test status
Simulation time 21644512663 ps
CPU time 1289.29 seconds
Started Jan 17 02:51:58 PM PST 24
Finished Jan 17 03:13:34 PM PST 24
Peak memory 272660 kb
Host smart-6fbd3b5e-5359-48cb-a683-d1bcaca2394c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973495480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1973495480
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.642344775
Short name T302
Test name
Test status
Simulation time 18623036472 ps
CPU time 386.98 seconds
Started Jan 17 02:51:59 PM PST 24
Finished Jan 17 02:58:32 PM PST 24
Peak memory 247604 kb
Host smart-a3d62e1e-2e40-45d5-8c6f-db6209f6ca39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642344775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.642344775
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3238885014
Short name T415
Test name
Test status
Simulation time 926196157 ps
CPU time 53.94 seconds
Started Jan 17 02:51:46 PM PST 24
Finished Jan 17 02:52:40 PM PST 24
Peak memory 248684 kb
Host smart-596a3c21-923d-4c06-963e-3e67c5ce339d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32388
85014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3238885014
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3070025835
Short name T57
Test name
Test status
Simulation time 88329636 ps
CPU time 4.29 seconds
Started Jan 17 02:51:45 PM PST 24
Finished Jan 17 02:51:51 PM PST 24
Peak memory 238724 kb
Host smart-26209522-176c-4999-a073-cc267a3d30f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30700
25835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3070025835
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1664454053
Short name T488
Test name
Test status
Simulation time 560349317 ps
CPU time 40.87 seconds
Started Jan 17 02:52:00 PM PST 24
Finished Jan 17 02:52:46 PM PST 24
Peak memory 254916 kb
Host smart-74e665ec-22f8-4548-99b7-fdf88470115c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16644
54053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1664454053
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2468178025
Short name T257
Test name
Test status
Simulation time 516973253 ps
CPU time 10.21 seconds
Started Jan 17 02:51:45 PM PST 24
Finished Jan 17 02:51:57 PM PST 24
Peak memory 248692 kb
Host smart-16ea369a-33d0-4926-b14a-6710e43ff86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24681
78025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2468178025
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.495665554
Short name T454
Test name
Test status
Simulation time 63148915666 ps
CPU time 3009.1 seconds
Started Jan 17 02:51:59 PM PST 24
Finished Jan 17 03:42:14 PM PST 24
Peak memory 289580 kb
Host smart-76ef895b-f537-48db-89eb-dfed0c100e68
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495665554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.495665554
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2305956909
Short name T190
Test name
Test status
Simulation time 51235763 ps
CPU time 2.63 seconds
Started Jan 17 02:52:09 PM PST 24
Finished Jan 17 02:52:14 PM PST 24
Peak memory 248820 kb
Host smart-6a4af89f-2cf5-4c67-b438-5ebfbdef37b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2305956909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2305956909
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2552464453
Short name T267
Test name
Test status
Simulation time 68752756080 ps
CPU time 1356.67 seconds
Started Jan 17 02:52:10 PM PST 24
Finished Jan 17 03:14:48 PM PST 24
Peak memory 289616 kb
Host smart-cdfe7dcb-6d4a-4b62-a195-f18045f7304b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552464453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2552464453
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.320314997
Short name T694
Test name
Test status
Simulation time 5924928525 ps
CPU time 191.37 seconds
Started Jan 17 02:52:06 PM PST 24
Finished Jan 17 02:55:20 PM PST 24
Peak memory 256924 kb
Host smart-37c2873c-849c-4024-90a2-c4c0206021e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32031
4997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.320314997
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.308103735
Short name T678
Test name
Test status
Simulation time 237333965 ps
CPU time 4.68 seconds
Started Jan 17 02:52:01 PM PST 24
Finished Jan 17 02:52:09 PM PST 24
Peak memory 240200 kb
Host smart-15e1d714-b06c-45d2-8c20-9a068ed3ef8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30810
3735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.308103735
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1350083743
Short name T514
Test name
Test status
Simulation time 13001979149 ps
CPU time 1171.27 seconds
Started Jan 17 02:52:08 PM PST 24
Finished Jan 17 03:11:42 PM PST 24
Peak memory 272848 kb
Host smart-dca9bc2c-90dc-4969-a2fc-b849caf457bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350083743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1350083743
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3759691971
Short name T357
Test name
Test status
Simulation time 631101352216 ps
CPU time 3469.4 seconds
Started Jan 17 02:52:10 PM PST 24
Finished Jan 17 03:50:01 PM PST 24
Peak memory 282488 kb
Host smart-2e0417cd-48a3-40fc-9f59-df9840b9bb07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759691971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3759691971
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2344719801
Short name T281
Test name
Test status
Simulation time 12784633104 ps
CPU time 136.23 seconds
Started Jan 17 02:52:09 PM PST 24
Finished Jan 17 02:54:27 PM PST 24
Peak memory 246588 kb
Host smart-420a02bd-ee01-42a2-be54-3e7d52b94eb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344719801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2344719801
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3902338135
Short name T218
Test name
Test status
Simulation time 44795596 ps
CPU time 4.22 seconds
Started Jan 17 02:51:58 PM PST 24
Finished Jan 17 02:52:09 PM PST 24
Peak memory 240500 kb
Host smart-2e4cb4ab-6e5a-4840-b744-850b6351d0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39023
38135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3902338135
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1418995999
Short name T556
Test name
Test status
Simulation time 1162465303 ps
CPU time 43.34 seconds
Started Jan 17 02:51:58 PM PST 24
Finished Jan 17 02:52:48 PM PST 24
Peak memory 248760 kb
Host smart-1a7d5304-42d1-41ce-b481-a389a7987e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14189
95999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1418995999
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.404359421
Short name T614
Test name
Test status
Simulation time 107136456 ps
CPU time 10.77 seconds
Started Jan 17 02:52:08 PM PST 24
Finished Jan 17 02:52:21 PM PST 24
Peak memory 255212 kb
Host smart-d5103cda-6fef-4a1c-b637-8fd4c6b2b442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40435
9421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.404359421
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2918694849
Short name T519
Test name
Test status
Simulation time 76020690 ps
CPU time 9.11 seconds
Started Jan 17 02:52:01 PM PST 24
Finished Jan 17 02:52:14 PM PST 24
Peak memory 248600 kb
Host smart-eec86e3f-c9c7-4051-9a89-d1786ae69e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29186
94849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2918694849
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2132905850
Short name T37
Test name
Test status
Simulation time 25703372281 ps
CPU time 1085.73 seconds
Started Jan 17 02:52:08 PM PST 24
Finished Jan 17 03:10:16 PM PST 24
Peak memory 289320 kb
Host smart-f3b6040c-2e71-4efd-9b59-6625c01156ad
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132905850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2132905850
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3794297623
Short name T630
Test name
Test status
Simulation time 522356556388 ps
CPU time 4063.32 seconds
Started Jan 17 02:52:12 PM PST 24
Finished Jan 17 03:59:56 PM PST 24
Peak memory 306256 kb
Host smart-b8b792a7-d28a-426d-b3e0-3ebd5114614a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794297623 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3794297623
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.4241388410
Short name T193
Test name
Test status
Simulation time 43106256 ps
CPU time 3.53 seconds
Started Jan 17 02:52:22 PM PST 24
Finished Jan 17 02:52:26 PM PST 24
Peak memory 248864 kb
Host smart-c400c155-6492-4762-8097-9eba99ce9358
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4241388410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.4241388410
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2789404397
Short name T108
Test name
Test status
Simulation time 6445381292 ps
CPU time 567.07 seconds
Started Jan 17 02:52:20 PM PST 24
Finished Jan 17 03:01:48 PM PST 24
Peak memory 265136 kb
Host smart-3dffabbd-840a-4e7d-b3c1-263144dc819f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789404397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2789404397
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.447495670
Short name T353
Test name
Test status
Simulation time 1667123772 ps
CPU time 20.18 seconds
Started Jan 17 02:52:18 PM PST 24
Finished Jan 17 02:52:39 PM PST 24
Peak memory 240368 kb
Host smart-703b1fa5-c804-45e5-b8c8-4b16779bcbb4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=447495670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.447495670
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1374899068
Short name T571
Test name
Test status
Simulation time 7180335389 ps
CPU time 106.43 seconds
Started Jan 17 02:52:18 PM PST 24
Finished Jan 17 02:54:05 PM PST 24
Peak memory 256960 kb
Host smart-5b6f8809-2198-4695-9f00-da3ee94bbc42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13748
99068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1374899068
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.168417417
Short name T74
Test name
Test status
Simulation time 4316816817 ps
CPU time 65.64 seconds
Started Jan 17 02:52:20 PM PST 24
Finished Jan 17 02:53:26 PM PST 24
Peak memory 255680 kb
Host smart-b682ce94-07d7-475d-ab6e-b7c8ed9d59ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16841
7417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.168417417
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2532285139
Short name T328
Test name
Test status
Simulation time 248001307014 ps
CPU time 1383.07 seconds
Started Jan 17 02:52:20 PM PST 24
Finished Jan 17 03:15:23 PM PST 24
Peak memory 289336 kb
Host smart-bcfeeebd-4dae-4aa4-b32d-ec080c0b95e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532285139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2532285139
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3622051684
Short name T256
Test name
Test status
Simulation time 449367800703 ps
CPU time 1951.13 seconds
Started Jan 17 02:52:20 PM PST 24
Finished Jan 17 03:24:52 PM PST 24
Peak memory 281952 kb
Host smart-e03b1ff4-a14f-4bd8-943f-66e743fe57f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622051684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3622051684
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1256276166
Short name T660
Test name
Test status
Simulation time 606103521 ps
CPU time 35.19 seconds
Started Jan 17 02:52:22 PM PST 24
Finished Jan 17 02:52:57 PM PST 24
Peak memory 248448 kb
Host smart-710966f9-4b2c-4da1-8d12-5d10a1b12303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562
76166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1256276166
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2907881482
Short name T579
Test name
Test status
Simulation time 947595954 ps
CPU time 60.46 seconds
Started Jan 17 02:52:21 PM PST 24
Finished Jan 17 02:53:22 PM PST 24
Peak memory 247116 kb
Host smart-1f0eb035-e9dd-4857-a01c-1486e2a7d507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29078
81482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2907881482
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1156293528
Short name T391
Test name
Test status
Simulation time 238401387 ps
CPU time 13.31 seconds
Started Jan 17 02:52:21 PM PST 24
Finished Jan 17 02:52:35 PM PST 24
Peak memory 246688 kb
Host smart-d6e3dfb1-c337-46e9-af0a-0ac8ce04ce34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11562
93528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1156293528
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3034259764
Short name T351
Test name
Test status
Simulation time 1038678687 ps
CPU time 19.72 seconds
Started Jan 17 02:52:22 PM PST 24
Finished Jan 17 02:52:42 PM PST 24
Peak memory 248640 kb
Host smart-c9413d5e-c167-4251-8708-3d441fdfc09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30342
59764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3034259764
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1888435043
Short name T474
Test name
Test status
Simulation time 140360322418 ps
CPU time 2230.75 seconds
Started Jan 17 02:52:20 PM PST 24
Finished Jan 17 03:29:32 PM PST 24
Peak memory 288376 kb
Host smart-7c08d5a6-3b46-4bee-9fe5-40029bd6d6aa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888435043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1888435043
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3594908135
Short name T20
Test name
Test status
Simulation time 155135060274 ps
CPU time 2691.31 seconds
Started Jan 17 02:52:20 PM PST 24
Finished Jan 17 03:37:12 PM PST 24
Peak memory 306172 kb
Host smart-9de96539-d2b2-4e74-bccd-f55bbb46e62c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594908135 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3594908135
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.181745837
Short name T189
Test name
Test status
Simulation time 35877818 ps
CPU time 2.18 seconds
Started Jan 17 02:48:43 PM PST 24
Finished Jan 17 02:48:48 PM PST 24
Peak memory 248732 kb
Host smart-94f75274-6fcd-4bf0-b80f-7f6d4486bcfb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=181745837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.181745837
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2539881199
Short name T99
Test name
Test status
Simulation time 37917885154 ps
CPU time 1708.23 seconds
Started Jan 17 02:48:57 PM PST 24
Finished Jan 17 03:17:27 PM PST 24
Peak memory 289464 kb
Host smart-5ff2f275-0ee3-4200-a17f-c601687356ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539881199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2539881199
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3507411171
Short name T443
Test name
Test status
Simulation time 317784862 ps
CPU time 9.05 seconds
Started Jan 17 02:48:43 PM PST 24
Finished Jan 17 02:48:55 PM PST 24
Peak memory 240228 kb
Host smart-a4faf76a-238d-437e-9542-88cfa8402298
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3507411171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3507411171
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3798812232
Short name T637
Test name
Test status
Simulation time 490085244 ps
CPU time 11.15 seconds
Started Jan 17 02:48:32 PM PST 24
Finished Jan 17 02:48:43 PM PST 24
Peak memory 253188 kb
Host smart-93f2c1f8-b8ef-447e-9fbd-8973c2f01ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37988
12232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3798812232
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2522670896
Short name T679
Test name
Test status
Simulation time 225899785 ps
CPU time 20.35 seconds
Started Jan 17 02:48:30 PM PST 24
Finished Jan 17 02:48:51 PM PST 24
Peak memory 248400 kb
Host smart-6b3ed1d1-ecc5-4247-abcb-c2e8912b0d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25226
70896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2522670896
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.384540960
Short name T709
Test name
Test status
Simulation time 33908870286 ps
CPU time 1886.01 seconds
Started Jan 17 02:48:36 PM PST 24
Finished Jan 17 03:20:03 PM PST 24
Peak memory 272944 kb
Host smart-7eba6430-3fa9-4e48-8d21-dce2c81bc22d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384540960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.384540960
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.276878280
Short name T578
Test name
Test status
Simulation time 47750158 ps
CPU time 3 seconds
Started Jan 17 02:48:29 PM PST 24
Finished Jan 17 02:48:32 PM PST 24
Peak memory 240476 kb
Host smart-3172f8e9-2a1f-4c25-866a-e3c979ddf22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27687
8280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.276878280
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1632817526
Short name T54
Test name
Test status
Simulation time 3097923043 ps
CPU time 52.43 seconds
Started Jan 17 02:48:30 PM PST 24
Finished Jan 17 02:49:23 PM PST 24
Peak memory 255188 kb
Host smart-b54a6646-c3cd-436a-86c6-43f0a802a278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16328
17526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1632817526
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1695243454
Short name T41
Test name
Test status
Simulation time 178132472 ps
CPU time 11.66 seconds
Started Jan 17 02:48:45 PM PST 24
Finished Jan 17 02:48:58 PM PST 24
Peak memory 272352 kb
Host smart-01ef9883-7aa4-473b-b61b-b71e8e6e793a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1695243454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1695243454
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2427952965
Short name T246
Test name
Test status
Simulation time 971171081 ps
CPU time 33.37 seconds
Started Jan 17 02:48:30 PM PST 24
Finished Jan 17 02:49:04 PM PST 24
Peak memory 254880 kb
Host smart-6bd0ecd9-e49f-4bc4-9798-811afe690169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24279
52965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2427952965
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.915345077
Short name T512
Test name
Test status
Simulation time 210690676 ps
CPU time 17.55 seconds
Started Jan 17 02:48:22 PM PST 24
Finished Jan 17 02:48:40 PM PST 24
Peak memory 255812 kb
Host smart-225bc91a-b090-43da-84ea-7f6fdd14708e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91534
5077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.915345077
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3901272199
Short name T587
Test name
Test status
Simulation time 47333766835 ps
CPU time 1592.43 seconds
Started Jan 17 02:52:19 PM PST 24
Finished Jan 17 03:18:52 PM PST 24
Peak memory 273360 kb
Host smart-8cff1973-db1e-453d-a7d2-7511b70e9f74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901272199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3901272199
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.880436857
Short name T622
Test name
Test status
Simulation time 12876689829 ps
CPU time 210.18 seconds
Started Jan 17 02:52:21 PM PST 24
Finished Jan 17 02:55:52 PM PST 24
Peak memory 256848 kb
Host smart-991a4050-6bf8-4147-b0dc-f31bb8b510a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88043
6857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.880436857
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.4268814339
Short name T24
Test name
Test status
Simulation time 442700149 ps
CPU time 14.23 seconds
Started Jan 17 02:52:21 PM PST 24
Finished Jan 17 02:52:36 PM PST 24
Peak memory 248492 kb
Host smart-d596db9a-40be-430b-bb1a-8b78cd365cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42688
14339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.4268814339
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2049615003
Short name T102
Test name
Test status
Simulation time 53746558154 ps
CPU time 1402.33 seconds
Started Jan 17 02:52:26 PM PST 24
Finished Jan 17 03:15:51 PM PST 24
Peak memory 286944 kb
Host smart-8b1e80de-1f5b-4a61-aeeb-37e1d72338cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049615003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2049615003
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.195390824
Short name T270
Test name
Test status
Simulation time 90503245512 ps
CPU time 1475.4 seconds
Started Jan 17 02:52:19 PM PST 24
Finished Jan 17 03:16:55 PM PST 24
Peak memory 272416 kb
Host smart-6dff3d13-eaea-405c-9c54-a6083e45fff9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195390824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.195390824
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.389489644
Short name T308
Test name
Test status
Simulation time 30265331853 ps
CPU time 303.24 seconds
Started Jan 17 02:52:21 PM PST 24
Finished Jan 17 02:57:25 PM PST 24
Peak memory 247600 kb
Host smart-d5b2b7db-ccf1-46e6-8332-21e029277c7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389489644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.389489644
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2502133027
Short name T380
Test name
Test status
Simulation time 3433061545 ps
CPU time 52.82 seconds
Started Jan 17 02:52:21 PM PST 24
Finished Jan 17 02:53:14 PM PST 24
Peak memory 248676 kb
Host smart-9f92d929-b204-479e-99c4-e37a911dd656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25021
33027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2502133027
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2901863198
Short name T634
Test name
Test status
Simulation time 1341347132 ps
CPU time 43.9 seconds
Started Jan 17 02:52:21 PM PST 24
Finished Jan 17 02:53:05 PM PST 24
Peak memory 254872 kb
Host smart-c34e44cf-209a-4180-9618-6513804f5689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29018
63198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2901863198
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.766059992
Short name T390
Test name
Test status
Simulation time 575906986 ps
CPU time 17.66 seconds
Started Jan 17 02:52:19 PM PST 24
Finished Jan 17 02:52:37 PM PST 24
Peak memory 248660 kb
Host smart-6977c79e-f22b-413d-af70-c7a5a8f8b6e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76605
9992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.766059992
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1207344424
Short name T623
Test name
Test status
Simulation time 13455906806 ps
CPU time 1424.75 seconds
Started Jan 17 02:52:29 PM PST 24
Finished Jan 17 03:16:19 PM PST 24
Peak memory 288696 kb
Host smart-ca5bd43b-b700-4bb0-8287-b32f446a8ee5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207344424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1207344424
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2394857002
Short name T507
Test name
Test status
Simulation time 33865565330 ps
CPU time 2201.87 seconds
Started Jan 17 02:52:29 PM PST 24
Finished Jan 17 03:29:17 PM PST 24
Peak memory 290056 kb
Host smart-2b5ee621-0e9f-4876-bcd0-33531b64aad0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394857002 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2394857002
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1589445035
Short name T720
Test name
Test status
Simulation time 263082595567 ps
CPU time 2690.28 seconds
Started Jan 17 02:52:29 PM PST 24
Finished Jan 17 03:37:25 PM PST 24
Peak memory 288960 kb
Host smart-a2b6fcbc-74f1-4786-a25a-4d6dbdff83c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589445035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1589445035
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.626461428
Short name T641
Test name
Test status
Simulation time 1458254098 ps
CPU time 84.45 seconds
Started Jan 17 02:52:26 PM PST 24
Finished Jan 17 02:53:52 PM PST 24
Peak memory 255832 kb
Host smart-fb33ec36-39af-4ba6-ab18-6b671316474c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62646
1428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.626461428
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.4141624202
Short name T378
Test name
Test status
Simulation time 1195728538 ps
CPU time 20.31 seconds
Started Jan 17 02:52:34 PM PST 24
Finished Jan 17 02:52:55 PM PST 24
Peak memory 254840 kb
Host smart-8e923ee9-835a-4171-a4d3-110c4fc0b6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41416
24202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.4141624202
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1741770876
Short name T321
Test name
Test status
Simulation time 218286900767 ps
CPU time 1605.92 seconds
Started Jan 17 02:52:36 PM PST 24
Finished Jan 17 03:19:22 PM PST 24
Peak memory 288600 kb
Host smart-50339003-940c-4094-b105-fe1bce3ff3b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741770876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1741770876
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3227937053
Short name T533
Test name
Test status
Simulation time 18671260246 ps
CPU time 1382.5 seconds
Started Jan 17 02:52:36 PM PST 24
Finished Jan 17 03:15:39 PM PST 24
Peak memory 273552 kb
Host smart-c48647b1-cb58-40c3-8288-7383afa81114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227937053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3227937053
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.240480368
Short name T648
Test name
Test status
Simulation time 10127890024 ps
CPU time 230.08 seconds
Started Jan 17 02:52:37 PM PST 24
Finished Jan 17 02:56:27 PM PST 24
Peak memory 247572 kb
Host smart-156fb63d-2f18-4d0c-9381-3763672686cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240480368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.240480368
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3242220139
Short name T589
Test name
Test status
Simulation time 872140960 ps
CPU time 19.21 seconds
Started Jan 17 02:52:34 PM PST 24
Finished Jan 17 02:52:54 PM PST 24
Peak memory 255116 kb
Host smart-faaf95d4-c0f3-45ea-8cbc-f28408328218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32422
20139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3242220139
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.4054459948
Short name T676
Test name
Test status
Simulation time 931359512 ps
CPU time 53.22 seconds
Started Jan 17 02:52:28 PM PST 24
Finished Jan 17 02:53:27 PM PST 24
Peak memory 255136 kb
Host smart-0e94ab65-c90b-4838-986d-a3878dde1748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40544
59948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.4054459948
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1072321670
Short name T479
Test name
Test status
Simulation time 1776934222 ps
CPU time 29.18 seconds
Started Jan 17 02:52:34 PM PST 24
Finished Jan 17 02:53:04 PM PST 24
Peak memory 254636 kb
Host smart-4e372351-8dd4-453a-9a82-67e60321845c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10723
21670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1072321670
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1732497937
Short name T595
Test name
Test status
Simulation time 4043439031 ps
CPU time 59.36 seconds
Started Jan 17 02:52:29 PM PST 24
Finished Jan 17 02:53:34 PM PST 24
Peak memory 256800 kb
Host smart-7081dc00-ea56-4591-887f-e3275500f755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17324
97937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1732497937
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2438325050
Short name T486
Test name
Test status
Simulation time 1621991536 ps
CPU time 101.55 seconds
Started Jan 17 02:52:37 PM PST 24
Finished Jan 17 02:54:19 PM PST 24
Peak memory 255212 kb
Host smart-8031eec8-cf49-469f-84dc-2429e9634c74
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438325050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2438325050
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2043970361
Short name T67
Test name
Test status
Simulation time 75274934639 ps
CPU time 7362.47 seconds
Started Jan 17 02:52:35 PM PST 24
Finished Jan 17 04:55:18 PM PST 24
Peak memory 371048 kb
Host smart-57e0c10c-03a5-4ce7-80ff-b64607260333
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043970361 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2043970361
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.833529249
Short name T532
Test name
Test status
Simulation time 121105124637 ps
CPU time 1913.28 seconds
Started Jan 17 02:52:53 PM PST 24
Finished Jan 17 03:24:49 PM PST 24
Peak memory 283360 kb
Host smart-3cad3803-dd95-4bfb-b911-7f408f410921
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833529249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.833529249
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2522171798
Short name T655
Test name
Test status
Simulation time 3878855793 ps
CPU time 151.12 seconds
Started Jan 17 02:52:53 PM PST 24
Finished Jan 17 02:55:27 PM PST 24
Peak memory 250880 kb
Host smart-91fb8e7c-49be-42f1-8084-24fa3651ebb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25221
71798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2522171798
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3691438997
Short name T409
Test name
Test status
Simulation time 389173364 ps
CPU time 8.8 seconds
Started Jan 17 02:52:58 PM PST 24
Finished Jan 17 02:53:09 PM PST 24
Peak memory 248288 kb
Host smart-cc3e8f4b-b9bc-4ff8-b1ae-4a358f62a403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36914
38997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3691438997
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2929015119
Short name T671
Test name
Test status
Simulation time 133748870138 ps
CPU time 2035.05 seconds
Started Jan 17 02:52:53 PM PST 24
Finished Jan 17 03:26:51 PM PST 24
Peak memory 283080 kb
Host smart-de8be587-cebc-4737-973f-0edcd4cdb5fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929015119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2929015119
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2161901792
Short name T93
Test name
Test status
Simulation time 16743799814 ps
CPU time 1223.58 seconds
Started Jan 17 02:52:53 PM PST 24
Finished Jan 17 03:13:20 PM PST 24
Peak memory 265100 kb
Host smart-350eb19a-62fe-4271-ae78-46ccb09870fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161901792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2161901792
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1268290634
Short name T23
Test name
Test status
Simulation time 215587640 ps
CPU time 15.76 seconds
Started Jan 17 02:52:52 PM PST 24
Finished Jan 17 02:53:12 PM PST 24
Peak memory 254384 kb
Host smart-f54ec5c0-3152-440d-a09f-64c7ff8c75b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12682
90634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1268290634
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.4235706578
Short name T633
Test name
Test status
Simulation time 3037893321 ps
CPU time 48.25 seconds
Started Jan 17 02:52:53 PM PST 24
Finished Jan 17 02:53:44 PM PST 24
Peak memory 254628 kb
Host smart-fcb80355-b841-4cc3-86ee-c5d1349bd200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42357
06578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.4235706578
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.4240237493
Short name T560
Test name
Test status
Simulation time 70487302 ps
CPU time 2.75 seconds
Started Jan 17 02:52:52 PM PST 24
Finished Jan 17 02:52:59 PM PST 24
Peak memory 240496 kb
Host smart-53aee274-3d2e-424a-8987-08fb17a15098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42402
37493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.4240237493
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2506238569
Short name T26
Test name
Test status
Simulation time 7625943060 ps
CPU time 44.71 seconds
Started Jan 17 02:52:34 PM PST 24
Finished Jan 17 02:53:19 PM PST 24
Peak memory 256904 kb
Host smart-447108b6-a87d-488c-8826-5e359910a7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25062
38569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2506238569
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1675416870
Short name T237
Test name
Test status
Simulation time 72390049708 ps
CPU time 2242.92 seconds
Started Jan 17 02:52:59 PM PST 24
Finished Jan 17 03:30:23 PM PST 24
Peak memory 289296 kb
Host smart-782203cc-3897-49af-85c4-558093fb2008
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675416870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1675416870
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2246100837
Short name T492
Test name
Test status
Simulation time 30829226575 ps
CPU time 976.41 seconds
Started Jan 17 02:52:52 PM PST 24
Finished Jan 17 03:09:12 PM PST 24
Peak memory 282316 kb
Host smart-2870ea50-aec6-410c-95cb-e44c2c02764a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246100837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2246100837
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2692894626
Short name T227
Test name
Test status
Simulation time 1376900811 ps
CPU time 121.33 seconds
Started Jan 17 02:52:54 PM PST 24
Finished Jan 17 02:54:57 PM PST 24
Peak memory 255820 kb
Host smart-f15aee01-5763-4e53-ae65-198abe01cc73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26928
94626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2692894626
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4158632035
Short name T82
Test name
Test status
Simulation time 677991612 ps
CPU time 19.52 seconds
Started Jan 17 02:52:54 PM PST 24
Finished Jan 17 02:53:15 PM PST 24
Peak memory 248784 kb
Host smart-a17a6025-a1e7-469c-b10b-8da9dbd07771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41586
32035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4158632035
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.445403931
Short name T320
Test name
Test status
Simulation time 13313722757 ps
CPU time 1165.17 seconds
Started Jan 17 02:53:00 PM PST 24
Finished Jan 17 03:12:26 PM PST 24
Peak memory 273320 kb
Host smart-88cbca35-265b-4d99-bf8b-6859769614ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445403931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.445403931
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2973038021
Short name T416
Test name
Test status
Simulation time 75377997557 ps
CPU time 1276.54 seconds
Started Jan 17 02:53:01 PM PST 24
Finished Jan 17 03:14:18 PM PST 24
Peak memory 289080 kb
Host smart-9d6c6c0a-cd87-441f-92ad-beb959243b5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973038021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2973038021
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1369793634
Short name T296
Test name
Test status
Simulation time 2348185376 ps
CPU time 102.63 seconds
Started Jan 17 02:52:54 PM PST 24
Finished Jan 17 02:54:39 PM PST 24
Peak memory 247600 kb
Host smart-7853a892-6d8e-49a5-884f-2a978d844bd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369793634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1369793634
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.727104148
Short name T527
Test name
Test status
Simulation time 94871402 ps
CPU time 7.98 seconds
Started Jan 17 02:52:52 PM PST 24
Finished Jan 17 02:53:04 PM PST 24
Peak memory 248600 kb
Host smart-3882e11c-3448-4c34-b8fa-47f2f31443b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72710
4148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.727104148
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1293401790
Short name T66
Test name
Test status
Simulation time 8897633178 ps
CPU time 76.84 seconds
Started Jan 17 02:52:52 PM PST 24
Finished Jan 17 02:54:13 PM PST 24
Peak memory 254944 kb
Host smart-f7d011e6-8b23-4675-9162-4af5c806c9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12934
01790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1293401790
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1947338222
Short name T253
Test name
Test status
Simulation time 275668591 ps
CPU time 19.92 seconds
Started Jan 17 02:52:55 PM PST 24
Finished Jan 17 02:53:16 PM PST 24
Peak memory 252936 kb
Host smart-e70d165f-f24b-4349-b8cb-a588f313acc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19473
38222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1947338222
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.4112766843
Short name T340
Test name
Test status
Simulation time 62013198 ps
CPU time 5.18 seconds
Started Jan 17 02:52:52 PM PST 24
Finished Jan 17 02:53:01 PM PST 24
Peak memory 240476 kb
Host smart-324d7696-e95d-48e9-9130-cc8ec24a9561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41127
66843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.4112766843
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2004015358
Short name T233
Test name
Test status
Simulation time 296734039409 ps
CPU time 4139.37 seconds
Started Jan 17 02:53:02 PM PST 24
Finished Jan 17 04:02:02 PM PST 24
Peak memory 303640 kb
Host smart-edb6c96e-9cb5-45b0-b7d2-ad97a2c5ec39
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004015358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2004015358
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1067102578
Short name T379
Test name
Test status
Simulation time 29769958523 ps
CPU time 1937.76 seconds
Started Jan 17 02:52:59 PM PST 24
Finished Jan 17 03:25:18 PM PST 24
Peak memory 284356 kb
Host smart-1b36c4ce-ea0c-4101-bfca-3bec01dbc57c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067102578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1067102578
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1821888199
Short name T670
Test name
Test status
Simulation time 1680103776 ps
CPU time 76.82 seconds
Started Jan 17 02:53:01 PM PST 24
Finished Jan 17 02:54:18 PM PST 24
Peak memory 255864 kb
Host smart-2ff5df1f-00e4-4529-a0f0-4b9c3d397e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18218
88199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1821888199
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3481546272
Short name T502
Test name
Test status
Simulation time 273692767 ps
CPU time 36.09 seconds
Started Jan 17 02:53:00 PM PST 24
Finished Jan 17 02:53:37 PM PST 24
Peak memory 248592 kb
Host smart-617b6ce8-a936-4efa-8dd3-5423fa400fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34815
46272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3481546272
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1272414487
Short name T628
Test name
Test status
Simulation time 40590747445 ps
CPU time 2384.25 seconds
Started Jan 17 02:53:08 PM PST 24
Finished Jan 17 03:32:53 PM PST 24
Peak memory 273104 kb
Host smart-45a24941-bdbd-43df-b25e-52da072b47b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272414487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1272414487
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.302119478
Short name T283
Test name
Test status
Simulation time 12262847889 ps
CPU time 499.31 seconds
Started Jan 17 02:53:10 PM PST 24
Finished Jan 17 03:01:29 PM PST 24
Peak memory 247344 kb
Host smart-bd5cb677-9255-4414-9c7a-0aab89c09c43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302119478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.302119478
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.44944972
Short name T596
Test name
Test status
Simulation time 2490450700 ps
CPU time 38.75 seconds
Started Jan 17 02:53:00 PM PST 24
Finished Jan 17 02:53:40 PM PST 24
Peak memory 256980 kb
Host smart-1b635c08-08d6-4185-8f9d-085068b8b5c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44944
972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.44944972
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3171792530
Short name T722
Test name
Test status
Simulation time 671726000 ps
CPU time 39.57 seconds
Started Jan 17 02:53:00 PM PST 24
Finished Jan 17 02:53:41 PM PST 24
Peak memory 255568 kb
Host smart-b5bc65e6-ccff-409a-8b7f-2ce312a29375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31717
92530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3171792530
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2934521216
Short name T525
Test name
Test status
Simulation time 666865093 ps
CPU time 20.15 seconds
Started Jan 17 02:53:00 PM PST 24
Finished Jan 17 02:53:21 PM PST 24
Peak memory 248632 kb
Host smart-7c9ccff8-3793-4c2b-b1be-28d6b328726f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29345
21216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2934521216
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.455981003
Short name T273
Test name
Test status
Simulation time 677603407 ps
CPU time 15.46 seconds
Started Jan 17 02:53:20 PM PST 24
Finished Jan 17 02:53:37 PM PST 24
Peak memory 253500 kb
Host smart-b47417d6-4685-4d1f-84ea-21adf86f905e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455981003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.455981003
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.4231620931
Short name T65
Test name
Test status
Simulation time 202322393905 ps
CPU time 2017.86 seconds
Started Jan 17 02:53:10 PM PST 24
Finished Jan 17 03:26:49 PM PST 24
Peak memory 281140 kb
Host smart-527a58d9-943e-4f67-a2cd-06f8e10d67f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231620931 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.4231620931
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1157764910
Short name T96
Test name
Test status
Simulation time 13850097293 ps
CPU time 1364.33 seconds
Started Jan 17 02:53:26 PM PST 24
Finished Jan 17 03:16:11 PM PST 24
Peak memory 289516 kb
Host smart-3594aa2a-e067-48cd-b2c1-3deaa80f9bce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157764910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1157764910
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.935281966
Short name T531
Test name
Test status
Simulation time 445849903 ps
CPU time 26.9 seconds
Started Jan 17 02:53:18 PM PST 24
Finished Jan 17 02:53:48 PM PST 24
Peak memory 247972 kb
Host smart-7ea56a26-6e7b-4953-9841-b535375d769e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93528
1966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.935281966
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.28906255
Short name T484
Test name
Test status
Simulation time 180707070 ps
CPU time 6.35 seconds
Started Jan 17 02:53:21 PM PST 24
Finished Jan 17 02:53:28 PM PST 24
Peak memory 238680 kb
Host smart-49955d12-cd0f-4253-9a4d-dd6e7dcb8455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28906
255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.28906255
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3845652938
Short name T77
Test name
Test status
Simulation time 59827463474 ps
CPU time 1602.45 seconds
Started Jan 17 02:53:27 PM PST 24
Finished Jan 17 03:20:11 PM PST 24
Peak memory 289064 kb
Host smart-87e88105-2314-4d0b-a8e5-11f443eed4ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845652938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3845652938
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.649368427
Short name T574
Test name
Test status
Simulation time 10596112220 ps
CPU time 427.03 seconds
Started Jan 17 02:53:30 PM PST 24
Finished Jan 17 03:00:37 PM PST 24
Peak memory 248460 kb
Host smart-b1f2f271-d327-489a-a96f-95bccc4a32d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649368427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.649368427
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3452017455
Short name T423
Test name
Test status
Simulation time 2060911109 ps
CPU time 57.93 seconds
Started Jan 17 02:53:14 PM PST 24
Finished Jan 17 02:54:13 PM PST 24
Peak memory 248684 kb
Host smart-cd98f857-4df8-4434-920f-8fa5364bd2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34520
17455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3452017455
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.597361459
Short name T259
Test name
Test status
Simulation time 4039635969 ps
CPU time 64.17 seconds
Started Jan 17 02:53:21 PM PST 24
Finished Jan 17 02:54:26 PM PST 24
Peak memory 248692 kb
Host smart-8c1ecea3-de79-48f8-96ac-267c4edab388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59736
1459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.597361459
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2009928214
Short name T592
Test name
Test status
Simulation time 3160009376 ps
CPU time 49.55 seconds
Started Jan 17 02:53:26 PM PST 24
Finished Jan 17 02:54:16 PM PST 24
Peak memory 256848 kb
Host smart-1e4b2c0d-4ab9-4714-b738-19d129975df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20099
28214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2009928214
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2316903919
Short name T575
Test name
Test status
Simulation time 3562738293 ps
CPU time 29.93 seconds
Started Jan 17 02:53:10 PM PST 24
Finished Jan 17 02:53:40 PM PST 24
Peak memory 248684 kb
Host smart-fe0be9a1-d9cb-4cd7-a20d-830d6c04c8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23169
03919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2316903919
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2423206985
Short name T116
Test name
Test status
Simulation time 31025926501 ps
CPU time 3310.37 seconds
Started Jan 17 02:53:29 PM PST 24
Finished Jan 17 03:48:40 PM PST 24
Peak memory 322356 kb
Host smart-0ed305d7-1dd1-4555-a07d-4b5064517db1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423206985 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2423206985
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1249964380
Short name T16
Test name
Test status
Simulation time 13437813605 ps
CPU time 841.58 seconds
Started Jan 17 02:53:34 PM PST 24
Finished Jan 17 03:07:36 PM PST 24
Peak memory 272920 kb
Host smart-c3008491-d914-4f72-8e09-92c5b876a489
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249964380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1249964380
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3568932688
Short name T495
Test name
Test status
Simulation time 15901533389 ps
CPU time 225.99 seconds
Started Jan 17 02:53:26 PM PST 24
Finished Jan 17 02:57:13 PM PST 24
Peak memory 256376 kb
Host smart-5f74b9ed-ebe8-4035-bb05-eb9d01f28ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35689
32688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3568932688
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1365394414
Short name T80
Test name
Test status
Simulation time 1425272182 ps
CPU time 8.05 seconds
Started Jan 17 02:53:28 PM PST 24
Finished Jan 17 02:53:37 PM PST 24
Peak memory 252360 kb
Host smart-aedc723a-bfb3-4d07-857c-055060f64931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13653
94414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1365394414
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3342527345
Short name T317
Test name
Test status
Simulation time 25927197252 ps
CPU time 1627.07 seconds
Started Jan 17 02:53:33 PM PST 24
Finished Jan 17 03:20:41 PM PST 24
Peak memory 272048 kb
Host smart-cfddabe2-50b0-4c5c-bc17-d39fbab03403
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342527345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3342527345
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.4067622842
Short name T432
Test name
Test status
Simulation time 30481909213 ps
CPU time 1883.64 seconds
Started Jan 17 02:53:32 PM PST 24
Finished Jan 17 03:24:57 PM PST 24
Peak memory 285248 kb
Host smart-815913ff-4744-4050-a579-ce54000088a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067622842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.4067622842
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.4071397608
Short name T666
Test name
Test status
Simulation time 20730692973 ps
CPU time 326.6 seconds
Started Jan 17 02:53:36 PM PST 24
Finished Jan 17 02:59:03 PM PST 24
Peak memory 247312 kb
Host smart-490c64c4-9e43-4a15-97cc-863da4e866c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071397608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.4071397608
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2360822148
Short name T399
Test name
Test status
Simulation time 2483302056 ps
CPU time 39.63 seconds
Started Jan 17 02:53:28 PM PST 24
Finished Jan 17 02:54:08 PM PST 24
Peak memory 255380 kb
Host smart-c8b95490-3983-456c-a090-f677673b92b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23608
22148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2360822148
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3555146269
Short name T360
Test name
Test status
Simulation time 11951601350 ps
CPU time 54.13 seconds
Started Jan 17 02:53:26 PM PST 24
Finished Jan 17 02:54:20 PM PST 24
Peak memory 256864 kb
Host smart-29c9ef08-acf8-4c2b-a577-a2a24518723e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35551
46269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3555146269
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.714277534
Short name T269
Test name
Test status
Simulation time 187177197 ps
CPU time 21.03 seconds
Started Jan 17 02:53:28 PM PST 24
Finished Jan 17 02:53:50 PM PST 24
Peak memory 246564 kb
Host smart-a2d511fb-eeb3-4ac7-ac47-7edcc4f58e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71427
7534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.714277534
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2748322485
Short name T704
Test name
Test status
Simulation time 2022692349 ps
CPU time 56.83 seconds
Started Jan 17 02:53:28 PM PST 24
Finished Jan 17 02:54:25 PM PST 24
Peak memory 255316 kb
Host smart-64fd31ca-4f91-4125-b9c6-87adb7a76827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27483
22485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2748322485
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.668284073
Short name T375
Test name
Test status
Simulation time 27964736557 ps
CPU time 174.89 seconds
Started Jan 17 02:53:42 PM PST 24
Finished Jan 17 02:56:38 PM PST 24
Peak memory 250920 kb
Host smart-79445fdf-67d2-4e3e-9a60-0767910e8112
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668284073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.668284073
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2375638626
Short name T643
Test name
Test status
Simulation time 85936348867 ps
CPU time 5424.66 seconds
Started Jan 17 02:53:42 PM PST 24
Finished Jan 17 04:24:08 PM PST 24
Peak memory 322016 kb
Host smart-a8d0273e-fabd-4240-8230-c735459c5d6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375638626 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2375638626
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2198339699
Short name T446
Test name
Test status
Simulation time 39462105859 ps
CPU time 1090.99 seconds
Started Jan 17 02:53:51 PM PST 24
Finished Jan 17 03:12:03 PM PST 24
Peak memory 289196 kb
Host smart-7b92c45c-e585-4bb0-a904-c1a26c425054
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198339699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2198339699
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1184545917
Short name T650
Test name
Test status
Simulation time 1684732288 ps
CPU time 99.62 seconds
Started Jan 17 02:54:00 PM PST 24
Finished Jan 17 02:55:40 PM PST 24
Peak memory 255900 kb
Host smart-510d0bd8-3bf8-47de-a6da-45b1424f42a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11845
45917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1184545917
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2848611892
Short name T663
Test name
Test status
Simulation time 721487962 ps
CPU time 44.78 seconds
Started Jan 17 02:53:43 PM PST 24
Finished Jan 17 02:54:30 PM PST 24
Peak memory 247976 kb
Host smart-83c8e7f1-7c2a-421f-a958-fd8d45d7d78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28486
11892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2848611892
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2638902283
Short name T698
Test name
Test status
Simulation time 9364331482 ps
CPU time 956.89 seconds
Started Jan 17 02:54:04 PM PST 24
Finished Jan 17 03:10:01 PM PST 24
Peak memory 272616 kb
Host smart-f9d16837-ef4d-4c43-ae0a-cbd26f9510fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638902283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2638902283
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1972958382
Short name T386
Test name
Test status
Simulation time 27215577814 ps
CPU time 1561.14 seconds
Started Jan 17 02:53:49 PM PST 24
Finished Jan 17 03:19:53 PM PST 24
Peak memory 282768 kb
Host smart-4160522d-88ca-43d7-bf79-92ed60fd33b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972958382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1972958382
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2466947425
Short name T306
Test name
Test status
Simulation time 19433768306 ps
CPU time 430.59 seconds
Started Jan 17 02:54:04 PM PST 24
Finished Jan 17 03:01:15 PM PST 24
Peak memory 247612 kb
Host smart-e8f554fd-682a-495e-853b-4f2cda7c11d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466947425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2466947425
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3458587490
Short name T448
Test name
Test status
Simulation time 709931243 ps
CPU time 13.53 seconds
Started Jan 17 02:53:41 PM PST 24
Finished Jan 17 02:53:56 PM PST 24
Peak memory 248672 kb
Host smart-6c64fcea-7dcc-49ac-be7b-c797bd5931f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34585
87490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3458587490
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1838195891
Short name T410
Test name
Test status
Simulation time 416299651 ps
CPU time 35.87 seconds
Started Jan 17 02:53:41 PM PST 24
Finished Jan 17 02:54:18 PM PST 24
Peak memory 248196 kb
Host smart-49ccb8e7-cc92-41b0-be07-4041543bd430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18381
95891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1838195891
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1679098698
Short name T39
Test name
Test status
Simulation time 1505440439 ps
CPU time 32.35 seconds
Started Jan 17 02:53:59 PM PST 24
Finished Jan 17 02:54:32 PM PST 24
Peak memory 254756 kb
Host smart-f244d897-55f2-45da-a848-1b13eeaab7c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16790
98698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1679098698
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.400283852
Short name T577
Test name
Test status
Simulation time 1961698241 ps
CPU time 33.31 seconds
Started Jan 17 02:53:41 PM PST 24
Finished Jan 17 02:54:16 PM PST 24
Peak memory 248744 kb
Host smart-cab11981-ed6e-4b4d-9160-5e44f8a3d081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40028
3852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.400283852
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1502737590
Short name T89
Test name
Test status
Simulation time 2553975419 ps
CPU time 82.26 seconds
Started Jan 17 02:53:53 PM PST 24
Finished Jan 17 02:55:16 PM PST 24
Peak memory 256888 kb
Host smart-455ae69b-7a37-45fe-bbb5-d2cb5957018a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502737590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1502737590
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1077921647
Short name T83
Test name
Test status
Simulation time 83405440312 ps
CPU time 2705.76 seconds
Started Jan 17 02:53:51 PM PST 24
Finished Jan 17 03:38:58 PM PST 24
Peak memory 305536 kb
Host smart-a851b0a2-0f6d-4ebe-ac62-a821b6a0ea7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077921647 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1077921647
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2173002077
Short name T48
Test name
Test status
Simulation time 115699903099 ps
CPU time 1734.66 seconds
Started Jan 17 02:53:59 PM PST 24
Finished Jan 17 03:22:54 PM PST 24
Peak memory 272292 kb
Host smart-996c7c63-2e3b-47c8-bb98-4bd8f2a8b4ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173002077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2173002077
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3379794969
Short name T394
Test name
Test status
Simulation time 1598547260 ps
CPU time 29.13 seconds
Started Jan 17 02:53:53 PM PST 24
Finished Jan 17 02:54:23 PM PST 24
Peak memory 248580 kb
Host smart-20f37ec9-9cff-4849-b086-197922544743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33797
94969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3379794969
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.4120798263
Short name T73
Test name
Test status
Simulation time 292554747 ps
CPU time 17.73 seconds
Started Jan 17 02:53:59 PM PST 24
Finished Jan 17 02:54:17 PM PST 24
Peak memory 253720 kb
Host smart-28c84b60-5e78-4096-940a-4d9034f758b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41207
98263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.4120798263
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.53909402
Short name T374
Test name
Test status
Simulation time 62003607567 ps
CPU time 1625.11 seconds
Started Jan 17 02:53:56 PM PST 24
Finished Jan 17 03:21:02 PM PST 24
Peak memory 289228 kb
Host smart-5718db2f-352c-4417-972a-c15b4fe1e7cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53909402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.53909402
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.4052679893
Short name T526
Test name
Test status
Simulation time 3758226423 ps
CPU time 57.72 seconds
Started Jan 17 02:53:50 PM PST 24
Finished Jan 17 02:54:50 PM PST 24
Peak memory 255524 kb
Host smart-f8d7ea19-0804-44dd-a194-acd5f09bc090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40526
79893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.4052679893
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2147628958
Short name T509
Test name
Test status
Simulation time 211743021 ps
CPU time 24.41 seconds
Started Jan 17 02:53:49 PM PST 24
Finished Jan 17 02:54:16 PM PST 24
Peak memory 248196 kb
Host smart-8449ed78-a2c4-4de9-b6db-2f694b1d91c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21476
28958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2147628958
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1798182064
Short name T555
Test name
Test status
Simulation time 1771600091 ps
CPU time 21.74 seconds
Started Jan 17 02:53:56 PM PST 24
Finished Jan 17 02:54:19 PM PST 24
Peak memory 254368 kb
Host smart-49019a3e-b392-4d86-8a26-47a81ce972b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17981
82064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1798182064
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.4281340026
Short name T457
Test name
Test status
Simulation time 572789362 ps
CPU time 12.52 seconds
Started Jan 17 02:53:59 PM PST 24
Finished Jan 17 02:54:12 PM PST 24
Peak memory 248832 kb
Host smart-53522721-8945-416c-ac69-cd453039a06e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42813
40026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.4281340026
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.4214322687
Short name T473
Test name
Test status
Simulation time 4170199549 ps
CPU time 248.73 seconds
Started Jan 17 02:53:56 PM PST 24
Finished Jan 17 02:58:06 PM PST 24
Peak memory 256868 kb
Host smart-663c48b7-319f-4f33-8c5f-0a42c4b9eed8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214322687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.4214322687
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2195364211
Short name T393
Test name
Test status
Simulation time 18495456206 ps
CPU time 1002.36 seconds
Started Jan 17 02:54:11 PM PST 24
Finished Jan 17 03:10:58 PM PST 24
Peak memory 289488 kb
Host smart-4e7c1c0f-d04f-41d1-9e2f-818a735737f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195364211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2195364211
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2744224314
Short name T485
Test name
Test status
Simulation time 1252657964 ps
CPU time 26.37 seconds
Started Jan 17 02:54:10 PM PST 24
Finished Jan 17 02:54:37 PM PST 24
Peak memory 256332 kb
Host smart-6d27ac7b-731d-4044-ace1-56375932cc57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27442
24314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2744224314
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3456922112
Short name T558
Test name
Test status
Simulation time 155055755 ps
CPU time 9.6 seconds
Started Jan 17 02:54:11 PM PST 24
Finished Jan 17 02:54:25 PM PST 24
Peak memory 248840 kb
Host smart-70b0a4b3-f8ac-409f-b76d-c7792be3b6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34569
22112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3456922112
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.415970065
Short name T701
Test name
Test status
Simulation time 10595099935 ps
CPU time 1137.97 seconds
Started Jan 17 02:54:11 PM PST 24
Finished Jan 17 03:13:14 PM PST 24
Peak memory 272904 kb
Host smart-5847cecd-b178-4b53-be3f-0eb27945c9a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415970065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.415970065
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2728056988
Short name T530
Test name
Test status
Simulation time 114554122417 ps
CPU time 1610.35 seconds
Started Jan 17 02:54:11 PM PST 24
Finished Jan 17 03:21:06 PM PST 24
Peak memory 272600 kb
Host smart-f445b6bc-35bf-495c-a3f5-351787da23bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728056988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2728056988
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.387720799
Short name T289
Test name
Test status
Simulation time 83738404621 ps
CPU time 660.88 seconds
Started Jan 17 02:54:13 PM PST 24
Finished Jan 17 03:05:17 PM PST 24
Peak memory 247488 kb
Host smart-2e2c9916-c6c0-4122-965e-8e6470ffb4cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387720799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.387720799
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.103176994
Short name T646
Test name
Test status
Simulation time 401760209 ps
CPU time 13.59 seconds
Started Jan 17 02:54:05 PM PST 24
Finished Jan 17 02:54:19 PM PST 24
Peak memory 256824 kb
Host smart-26aab204-ae31-42b9-92c4-80ae31d94406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10317
6994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.103176994
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1735710159
Short name T588
Test name
Test status
Simulation time 5305850130 ps
CPU time 41.03 seconds
Started Jan 17 02:54:03 PM PST 24
Finished Jan 17 02:54:44 PM PST 24
Peak memory 248772 kb
Host smart-bc8ff9eb-68a3-493e-91ac-6ed6aac3fc0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17357
10159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1735710159
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.944506569
Short name T562
Test name
Test status
Simulation time 796773659 ps
CPU time 47.1 seconds
Started Jan 17 02:54:10 PM PST 24
Finished Jan 17 02:54:58 PM PST 24
Peak memory 254956 kb
Host smart-a4833967-9325-4ed8-9d78-102e629d09c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94450
6569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.944506569
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2020910785
Short name T392
Test name
Test status
Simulation time 1542052872 ps
CPU time 30.35 seconds
Started Jan 17 02:54:06 PM PST 24
Finished Jan 17 02:54:37 PM PST 24
Peak memory 248856 kb
Host smart-8b043c4e-c928-4f6f-bebc-90bf28823d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20209
10785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2020910785
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3665525784
Short name T92
Test name
Test status
Simulation time 67912367777 ps
CPU time 986.15 seconds
Started Jan 17 02:54:10 PM PST 24
Finished Jan 17 03:10:37 PM PST 24
Peak memory 273312 kb
Host smart-011fd635-2912-4d6b-b173-db4418c39fa5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665525784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3665525784
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.177775942
Short name T200
Test name
Test status
Simulation time 86635205 ps
CPU time 2.6 seconds
Started Jan 17 02:48:49 PM PST 24
Finished Jan 17 02:48:52 PM PST 24
Peak memory 248912 kb
Host smart-3cf356ba-1a58-45a8-aaa0-5aa683e7455b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=177775942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.177775942
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1025243534
Short name T437
Test name
Test status
Simulation time 34185579291 ps
CPU time 811.62 seconds
Started Jan 17 02:48:48 PM PST 24
Finished Jan 17 03:02:21 PM PST 24
Peak memory 271372 kb
Host smart-25208f47-bfea-450d-8d3b-a5f54e14e77d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025243534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1025243534
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1784548531
Short name T221
Test name
Test status
Simulation time 937903446 ps
CPU time 38.37 seconds
Started Jan 17 02:48:48 PM PST 24
Finished Jan 17 02:49:27 PM PST 24
Peak memory 240448 kb
Host smart-fc71c1b3-1638-476a-a051-d38c9b53aa93
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1784548531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1784548531
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3175992438
Short name T86
Test name
Test status
Simulation time 20609410166 ps
CPU time 306.01 seconds
Started Jan 17 02:48:49 PM PST 24
Finished Jan 17 02:53:56 PM PST 24
Peak memory 250748 kb
Host smart-1b6e75d8-abf1-4501-b090-ce2b7754e626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31759
92438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3175992438
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2252831447
Short name T718
Test name
Test status
Simulation time 321097154 ps
CPU time 24.95 seconds
Started Jan 17 02:48:49 PM PST 24
Finished Jan 17 02:49:14 PM PST 24
Peak memory 254880 kb
Host smart-daa972ae-277d-45db-87e0-3532b6af2019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22528
31447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2252831447
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1640841469
Short name T346
Test name
Test status
Simulation time 32070854454 ps
CPU time 1322.82 seconds
Started Jan 17 02:48:52 PM PST 24
Finished Jan 17 03:10:56 PM PST 24
Peak memory 288024 kb
Host smart-2d0d07b0-58f4-4710-9ff5-c4fc8425ce6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640841469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1640841469
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2073246191
Short name T282
Test name
Test status
Simulation time 56706802688 ps
CPU time 582.2 seconds
Started Jan 17 02:48:49 PM PST 24
Finished Jan 17 02:58:32 PM PST 24
Peak memory 248720 kb
Host smart-33824ae2-f052-496d-9b48-fa450404db39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073246191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2073246191
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2412196694
Short name T447
Test name
Test status
Simulation time 363557722 ps
CPU time 24.1 seconds
Started Jan 17 02:48:43 PM PST 24
Finished Jan 17 02:49:10 PM PST 24
Peak memory 254132 kb
Host smart-4548b61b-a8e6-45e0-9ddc-bb71d31197d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24121
96694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2412196694
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1663609584
Short name T425
Test name
Test status
Simulation time 7750794392 ps
CPU time 25.95 seconds
Started Jan 17 02:48:49 PM PST 24
Finished Jan 17 02:49:16 PM PST 24
Peak memory 255428 kb
Host smart-dfb4425d-3bca-4119-9113-6895bbf24139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16636
09584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1663609584
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3812946271
Short name T505
Test name
Test status
Simulation time 163418651 ps
CPU time 10.74 seconds
Started Jan 17 02:48:51 PM PST 24
Finished Jan 17 02:49:02 PM PST 24
Peak memory 253772 kb
Host smart-e2e97d93-1088-4403-a806-e95b38c61a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38129
46271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3812946271
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1346842098
Short name T501
Test name
Test status
Simulation time 618629802 ps
CPU time 11.08 seconds
Started Jan 17 02:48:43 PM PST 24
Finished Jan 17 02:48:57 PM PST 24
Peak memory 248624 kb
Host smart-1e36b233-1f3d-487c-bb13-ee2e5026cff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13468
42098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1346842098
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.57199916
Short name T100
Test name
Test status
Simulation time 66092405529 ps
CPU time 2219.96 seconds
Started Jan 17 02:48:49 PM PST 24
Finished Jan 17 03:25:50 PM PST 24
Peak memory 289028 kb
Host smart-3df7d094-c320-4eab-8ec8-10082dff4886
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57199916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handl
er_stress_all.57199916
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3589393336
Short name T424
Test name
Test status
Simulation time 77159103332 ps
CPU time 3028.82 seconds
Started Jan 17 02:48:49 PM PST 24
Finished Jan 17 03:39:18 PM PST 24
Peak memory 281568 kb
Host smart-94c1d9ed-9aa4-480b-a8e2-ea3669ebe961
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589393336 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3589393336
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3512770105
Short name T686
Test name
Test status
Simulation time 22265798137 ps
CPU time 825.65 seconds
Started Jan 17 02:54:28 PM PST 24
Finished Jan 17 03:08:14 PM PST 24
Peak memory 272764 kb
Host smart-4104756e-4309-4724-880d-bc9ca7eec4e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512770105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3512770105
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2811822845
Short name T667
Test name
Test status
Simulation time 3966151780 ps
CPU time 205.74 seconds
Started Jan 17 02:54:31 PM PST 24
Finished Jan 17 02:57:58 PM PST 24
Peak memory 255832 kb
Host smart-3c562871-92e8-4c6b-8c1f-2d117f237943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28118
22845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2811822845
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2214639514
Short name T359
Test name
Test status
Simulation time 1950739736 ps
CPU time 28.13 seconds
Started Jan 17 02:54:17 PM PST 24
Finished Jan 17 02:54:46 PM PST 24
Peak memory 254644 kb
Host smart-571500ab-a0ba-438d-b96c-d1a1972fd5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22146
39514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2214639514
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3749847707
Short name T439
Test name
Test status
Simulation time 27966413715 ps
CPU time 1252.38 seconds
Started Jan 17 02:54:30 PM PST 24
Finished Jan 17 03:15:23 PM PST 24
Peak memory 281524 kb
Host smart-a3176ea0-dfa6-47a0-be04-02dcb280b8ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749847707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3749847707
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1800601651
Short name T725
Test name
Test status
Simulation time 55222848891 ps
CPU time 612.08 seconds
Started Jan 17 02:54:29 PM PST 24
Finished Jan 17 03:04:42 PM PST 24
Peak memory 247564 kb
Host smart-57b20fa3-8051-4fb1-9936-3f01664cd602
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800601651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1800601651
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2070759120
Short name T371
Test name
Test status
Simulation time 277133019 ps
CPU time 23.73 seconds
Started Jan 17 02:54:17 PM PST 24
Finished Jan 17 02:54:42 PM PST 24
Peak memory 248560 kb
Host smart-eeeba33f-da4c-440a-9c28-63d01f855345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20707
59120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2070759120
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1094975951
Short name T551
Test name
Test status
Simulation time 198811440 ps
CPU time 24.43 seconds
Started Jan 17 02:54:31 PM PST 24
Finished Jan 17 02:54:56 PM PST 24
Peak memory 253984 kb
Host smart-cc5003cb-dfd7-410e-99a6-22ab4b1d1fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10949
75951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1094975951
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.4090746990
Short name T710
Test name
Test status
Simulation time 48178636 ps
CPU time 4.48 seconds
Started Jan 17 02:54:31 PM PST 24
Finished Jan 17 02:54:36 PM PST 24
Peak memory 238076 kb
Host smart-099fc657-e216-47ed-80b3-847181dbfb87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40907
46990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.4090746990
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.578787317
Short name T341
Test name
Test status
Simulation time 628026424 ps
CPU time 26.91 seconds
Started Jan 17 02:54:18 PM PST 24
Finished Jan 17 02:54:45 PM PST 24
Peak memory 248664 kb
Host smart-38f8a314-a075-42c7-b344-5ce5db944c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57878
7317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.578787317
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2202526399
Short name T539
Test name
Test status
Simulation time 22933143599 ps
CPU time 1070.4 seconds
Started Jan 17 02:54:47 PM PST 24
Finished Jan 17 03:12:38 PM PST 24
Peak memory 284180 kb
Host smart-cce7d659-96c3-4eb1-a075-3103bb141f03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202526399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2202526399
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2373825543
Short name T373
Test name
Test status
Simulation time 2964913196 ps
CPU time 144.81 seconds
Started Jan 17 02:54:38 PM PST 24
Finished Jan 17 02:57:08 PM PST 24
Peak memory 250952 kb
Host smart-a627c37c-2f0e-4a27-9dee-87072e73638b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23738
25543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2373825543
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1702808482
Short name T636
Test name
Test status
Simulation time 719218179 ps
CPU time 31.77 seconds
Started Jan 17 02:54:38 PM PST 24
Finished Jan 17 02:55:15 PM PST 24
Peak memory 255080 kb
Host smart-1bbdd48f-3c0e-41b2-afc6-02715e50a1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17028
08482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1702808482
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.715791089
Short name T545
Test name
Test status
Simulation time 27080864030 ps
CPU time 1825.44 seconds
Started Jan 17 02:54:46 PM PST 24
Finished Jan 17 03:25:12 PM PST 24
Peak memory 272852 kb
Host smart-0f622fb5-2f15-4271-aedb-6459427f2cb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715791089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.715791089
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2366569164
Short name T300
Test name
Test status
Simulation time 34600350733 ps
CPU time 309.04 seconds
Started Jan 17 02:54:47 PM PST 24
Finished Jan 17 02:59:56 PM PST 24
Peak memory 247524 kb
Host smart-ae508e73-b2cf-4fbc-8f1e-b611e2d3c8f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366569164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2366569164
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1469590115
Short name T350
Test name
Test status
Simulation time 1074128610 ps
CPU time 38.7 seconds
Started Jan 17 02:54:38 PM PST 24
Finished Jan 17 02:55:23 PM PST 24
Peak memory 248508 kb
Host smart-2ea5a0f3-234e-4887-a9f1-03218b5ff853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14695
90115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1469590115
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3756482437
Short name T605
Test name
Test status
Simulation time 325627531 ps
CPU time 10.82 seconds
Started Jan 17 02:54:38 PM PST 24
Finished Jan 17 02:54:54 PM PST 24
Peak memory 254176 kb
Host smart-15c71854-0dc3-4f66-aea8-e6da4d7eb7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37564
82437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3756482437
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2341399455
Short name T88
Test name
Test status
Simulation time 130501845 ps
CPU time 9.29 seconds
Started Jan 17 02:54:40 PM PST 24
Finished Jan 17 02:54:53 PM PST 24
Peak memory 250288 kb
Host smart-b0e8f7c6-8ea8-4520-befc-a666254eaaf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23413
99455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2341399455
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3612187124
Short name T347
Test name
Test status
Simulation time 421967431 ps
CPU time 29.08 seconds
Started Jan 17 02:54:31 PM PST 24
Finished Jan 17 02:55:00 PM PST 24
Peak memory 248692 kb
Host smart-1f33b8f3-8296-4161-b930-ff67e51cecef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36121
87124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3612187124
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.632247443
Short name T396
Test name
Test status
Simulation time 210994523611 ps
CPU time 2798.3 seconds
Started Jan 17 02:54:45 PM PST 24
Finished Jan 17 03:41:24 PM PST 24
Peak memory 287552 kb
Host smart-7a930520-4cc2-4c9b-9cac-f4323b467b54
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632247443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.632247443
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2462406993
Short name T529
Test name
Test status
Simulation time 42285891706 ps
CPU time 1006.52 seconds
Started Jan 17 02:54:58 PM PST 24
Finished Jan 17 03:11:46 PM PST 24
Peak memory 268288 kb
Host smart-9d6ac5fd-af4a-4e0a-8844-9eea70a2d5a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462406993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2462406993
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2654758867
Short name T354
Test name
Test status
Simulation time 3930541624 ps
CPU time 72.88 seconds
Started Jan 17 02:54:59 PM PST 24
Finished Jan 17 02:56:13 PM PST 24
Peak memory 249756 kb
Host smart-bd235da6-5aea-42ee-85b2-c42b6b47c449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26547
58867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2654758867
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1570034925
Short name T412
Test name
Test status
Simulation time 796002615 ps
CPU time 45.18 seconds
Started Jan 17 02:55:01 PM PST 24
Finished Jan 17 02:55:47 PM PST 24
Peak memory 255084 kb
Host smart-1d977333-0212-42dd-abec-1cfddc0e477f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15700
34925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1570034925
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2531085928
Short name T276
Test name
Test status
Simulation time 95257570768 ps
CPU time 2573.24 seconds
Started Jan 17 02:54:59 PM PST 24
Finished Jan 17 03:37:53 PM PST 24
Peak memory 285560 kb
Host smart-8ab57112-39ca-425d-9300-f536d1d81643
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531085928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2531085928
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2302428963
Short name T565
Test name
Test status
Simulation time 12390286651 ps
CPU time 960.92 seconds
Started Jan 17 02:54:55 PM PST 24
Finished Jan 17 03:11:00 PM PST 24
Peak memory 269616 kb
Host smart-1980a9f8-4428-4c3e-99dd-f78ae9a6ec69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302428963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2302428963
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.883181383
Short name T301
Test name
Test status
Simulation time 8888077174 ps
CPU time 197.06 seconds
Started Jan 17 02:54:58 PM PST 24
Finished Jan 17 02:58:16 PM PST 24
Peak memory 246316 kb
Host smart-763271dc-a246-45e2-bbcb-e6b2b3058f44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883181383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.883181383
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.637791999
Short name T593
Test name
Test status
Simulation time 941447263 ps
CPU time 55.68 seconds
Started Jan 17 02:54:56 PM PST 24
Finished Jan 17 02:55:55 PM PST 24
Peak memory 255404 kb
Host smart-8728e4d4-25de-472e-ab89-4d60fc4b83a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63779
1999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.637791999
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3370073406
Short name T362
Test name
Test status
Simulation time 1186734819 ps
CPU time 24.49 seconds
Started Jan 17 02:54:52 PM PST 24
Finished Jan 17 02:55:18 PM PST 24
Peak memory 254704 kb
Host smart-28f602da-eb3b-4ccc-85d5-60be14a99048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33700
73406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3370073406
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3111486061
Short name T59
Test name
Test status
Simulation time 401146026 ps
CPU time 30.06 seconds
Started Jan 17 02:55:00 PM PST 24
Finished Jan 17 02:55:31 PM PST 24
Peak memory 254128 kb
Host smart-032bd5cf-6a91-4b91-97a3-2aaef2cb4feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31114
86061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3111486061
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.898864106
Short name T504
Test name
Test status
Simulation time 962124043 ps
CPU time 55.44 seconds
Started Jan 17 02:54:55 PM PST 24
Finished Jan 17 02:55:55 PM PST 24
Peak memory 248624 kb
Host smart-5c70c95e-cb1a-4e4f-918f-1ea391fad073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89886
4106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.898864106
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.741587010
Short name T243
Test name
Test status
Simulation time 194188438988 ps
CPU time 2111.3 seconds
Started Jan 17 02:55:05 PM PST 24
Finished Jan 17 03:30:17 PM PST 24
Peak memory 281524 kb
Host smart-8a23eafa-e97f-4be9-971d-1eee7277b8f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741587010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.741587010
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3021042205
Short name T517
Test name
Test status
Simulation time 13476799620 ps
CPU time 1190.58 seconds
Started Jan 17 02:55:07 PM PST 24
Finished Jan 17 03:14:59 PM PST 24
Peak memory 287240 kb
Host smart-7d0060e1-e9d1-4a87-a7f4-6ab313a5a16d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021042205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3021042205
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2901841386
Short name T569
Test name
Test status
Simulation time 1697352422 ps
CPU time 135.79 seconds
Started Jan 17 02:55:08 PM PST 24
Finished Jan 17 02:57:25 PM PST 24
Peak memory 256304 kb
Host smart-a0133bd7-65c3-4c12-9c45-dd005a3d5c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29018
41386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2901841386
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1401926870
Short name T606
Test name
Test status
Simulation time 2342547733 ps
CPU time 38.14 seconds
Started Jan 17 02:55:09 PM PST 24
Finished Jan 17 02:55:48 PM PST 24
Peak memory 254992 kb
Host smart-0c10cba3-de43-4caf-a363-c910f5fb4868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14019
26870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1401926870
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.597589876
Short name T649
Test name
Test status
Simulation time 41723549189 ps
CPU time 2414.27 seconds
Started Jan 17 02:55:12 PM PST 24
Finished Jan 17 03:35:27 PM PST 24
Peak memory 289148 kb
Host smart-6882f100-5d47-4e8e-a2e5-cc1804eba30d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597589876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.597589876
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2077294672
Short name T726
Test name
Test status
Simulation time 87637872085 ps
CPU time 1467.36 seconds
Started Jan 17 02:55:13 PM PST 24
Finished Jan 17 03:19:41 PM PST 24
Peak memory 272556 kb
Host smart-b257f347-d74c-441c-9b12-a9da72171091
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077294672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2077294672
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1000511372
Short name T314
Test name
Test status
Simulation time 20819687826 ps
CPU time 222.15 seconds
Started Jan 17 02:55:12 PM PST 24
Finished Jan 17 02:58:54 PM PST 24
Peak memory 247600 kb
Host smart-e2b3942c-a4d4-4cb5-8512-1a1cb85b14c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000511372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1000511372
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3033769211
Short name T476
Test name
Test status
Simulation time 599973581 ps
CPU time 36.19 seconds
Started Jan 17 02:55:05 PM PST 24
Finished Jan 17 02:55:42 PM PST 24
Peak memory 255660 kb
Host smart-e3e105f2-4566-435a-a10c-eb15347132e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30337
69211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3033769211
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.558412811
Short name T418
Test name
Test status
Simulation time 283385714 ps
CPU time 9.42 seconds
Started Jan 17 02:55:06 PM PST 24
Finished Jan 17 02:55:17 PM PST 24
Peak memory 248932 kb
Host smart-ae6d16ad-d09a-4633-942e-698a82ff526c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55841
2811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.558412811
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1450919844
Short name T706
Test name
Test status
Simulation time 234178401 ps
CPU time 16.87 seconds
Started Jan 17 02:55:06 PM PST 24
Finished Jan 17 02:55:24 PM PST 24
Peak memory 246920 kb
Host smart-6fb9e5e7-ea8e-4a20-9b26-36e7b0a405bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14509
19844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1450919844
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2577191492
Short name T684
Test name
Test status
Simulation time 1869986252 ps
CPU time 31.31 seconds
Started Jan 17 02:55:05 PM PST 24
Finished Jan 17 02:55:38 PM PST 24
Peak memory 256676 kb
Host smart-9639dec0-52d3-4ae9-9c03-0bb300aceb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25771
91492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2577191492
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2936338869
Short name T242
Test name
Test status
Simulation time 13641183354 ps
CPU time 1537.98 seconds
Started Jan 17 02:55:12 PM PST 24
Finished Jan 17 03:20:51 PM PST 24
Peak memory 289576 kb
Host smart-d0be4bdf-7dbf-4c80-831b-c72f15bfa3a4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936338869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2936338869
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3766912952
Short name T559
Test name
Test status
Simulation time 36119734110 ps
CPU time 2317.01 seconds
Started Jan 17 02:55:11 PM PST 24
Finished Jan 17 03:33:49 PM PST 24
Peak memory 320884 kb
Host smart-66941cce-9519-49fb-adee-b83cb0390cc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766912952 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3766912952
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.645900985
Short name T511
Test name
Test status
Simulation time 34404896899 ps
CPU time 1297.4 seconds
Started Jan 17 02:55:32 PM PST 24
Finished Jan 17 03:17:10 PM PST 24
Peak memory 288696 kb
Host smart-06916ce4-d0ee-41c7-b647-6ec46c070fb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645900985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.645900985
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.29319348
Short name T216
Test name
Test status
Simulation time 1976204327 ps
CPU time 161.89 seconds
Started Jan 17 02:55:36 PM PST 24
Finished Jan 17 02:58:18 PM PST 24
Peak memory 255856 kb
Host smart-33ca6677-c036-4546-8f0f-93ea14f15f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29319
348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.29319348
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3313593829
Short name T702
Test name
Test status
Simulation time 1243231690 ps
CPU time 25.68 seconds
Started Jan 17 02:55:17 PM PST 24
Finished Jan 17 02:55:44 PM PST 24
Peak memory 255320 kb
Host smart-e2fe3d54-f66f-4c6e-a8e3-a2722edbbf25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33135
93829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3313593829
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1349345532
Short name T642
Test name
Test status
Simulation time 53913530228 ps
CPU time 2868.13 seconds
Started Jan 17 02:55:32 PM PST 24
Finished Jan 17 03:43:21 PM PST 24
Peak memory 288484 kb
Host smart-08785962-c0b2-4faf-9cec-bac403d59393
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349345532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1349345532
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2495539514
Short name T395
Test name
Test status
Simulation time 9039045116 ps
CPU time 867.08 seconds
Started Jan 17 02:55:35 PM PST 24
Finished Jan 17 03:10:03 PM PST 24
Peak memory 272972 kb
Host smart-f5b6fa68-01ab-44fb-b855-2479c01163ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495539514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2495539514
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1155491529
Short name T604
Test name
Test status
Simulation time 6195951421 ps
CPU time 255.11 seconds
Started Jan 17 02:55:33 PM PST 24
Finished Jan 17 02:59:48 PM PST 24
Peak memory 248664 kb
Host smart-3bc4eb27-dd81-473c-97a2-10918dab9256
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155491529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1155491529
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2977573865
Short name T703
Test name
Test status
Simulation time 1192818856 ps
CPU time 21.51 seconds
Started Jan 17 02:55:12 PM PST 24
Finished Jan 17 02:55:34 PM PST 24
Peak memory 254192 kb
Host smart-a2316bfe-600e-4fb2-9134-c4e2e719b35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29775
73865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2977573865
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1876270475
Short name T431
Test name
Test status
Simulation time 3359532880 ps
CPU time 53.59 seconds
Started Jan 17 02:55:13 PM PST 24
Finished Jan 17 02:56:07 PM PST 24
Peak memory 256172 kb
Host smart-291c5f7c-fdef-404b-8597-9c777c2426a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18762
70475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1876270475
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2487581802
Short name T470
Test name
Test status
Simulation time 560441084 ps
CPU time 30.98 seconds
Started Jan 17 02:55:26 PM PST 24
Finished Jan 17 02:55:58 PM PST 24
Peak memory 248664 kb
Host smart-1e82bc09-b2c8-4004-980a-8eb4f1ca41c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24875
81802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2487581802
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1481497132
Short name T557
Test name
Test status
Simulation time 3227703587 ps
CPU time 51.5 seconds
Started Jan 17 02:55:12 PM PST 24
Finished Jan 17 02:56:03 PM PST 24
Peak memory 248732 kb
Host smart-cd37bd74-3b58-4c38-bd84-4320b3a41b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14814
97132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1481497132
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.861393265
Short name T441
Test name
Test status
Simulation time 30404091404 ps
CPU time 424.58 seconds
Started Jan 17 02:55:36 PM PST 24
Finished Jan 17 03:02:41 PM PST 24
Peak memory 256884 kb
Host smart-4b0821e9-e2bb-42e7-8c3a-089cc90db3eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861393265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.861393265
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1112820589
Short name T114
Test name
Test status
Simulation time 165609665470 ps
CPU time 2514.47 seconds
Started Jan 17 02:55:33 PM PST 24
Finished Jan 17 03:37:28 PM PST 24
Peak memory 281500 kb
Host smart-d28fb24c-6d8d-41c0-b36d-18d8fc8b58fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112820589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1112820589
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3004875594
Short name T658
Test name
Test status
Simulation time 9958834675 ps
CPU time 128.47 seconds
Started Jan 17 02:55:35 PM PST 24
Finished Jan 17 02:57:44 PM PST 24
Peak memory 256212 kb
Host smart-08f340b5-f434-46f9-9d71-78f119bbf7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30048
75594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3004875594
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3350118341
Short name T617
Test name
Test status
Simulation time 505938085 ps
CPU time 31.31 seconds
Started Jan 17 02:55:35 PM PST 24
Finished Jan 17 02:56:07 PM PST 24
Peak memory 254256 kb
Host smart-d41362f6-c77c-4208-9381-437e4c780e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33501
18341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3350118341
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2358229740
Short name T549
Test name
Test status
Simulation time 65931873496 ps
CPU time 1899.09 seconds
Started Jan 17 02:55:36 PM PST 24
Finished Jan 17 03:27:15 PM PST 24
Peak memory 272944 kb
Host smart-598619ef-d3e1-49af-9527-fa50eaa27c90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358229740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2358229740
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1602277873
Short name T522
Test name
Test status
Simulation time 159743583889 ps
CPU time 2305.64 seconds
Started Jan 17 02:56:20 PM PST 24
Finished Jan 17 03:34:47 PM PST 24
Peak memory 282752 kb
Host smart-8b28bfee-f0b0-4c71-8f32-a12ca2d120f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602277873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1602277873
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.868644463
Short name T287
Test name
Test status
Simulation time 168383394861 ps
CPU time 494.5 seconds
Started Jan 17 02:55:34 PM PST 24
Finished Jan 17 03:03:49 PM PST 24
Peak memory 247428 kb
Host smart-4cd42e3c-f2ea-4db6-a4ee-1081630009e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868644463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.868644463
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3234290132
Short name T524
Test name
Test status
Simulation time 2708998748 ps
CPU time 43.48 seconds
Started Jan 17 02:55:36 PM PST 24
Finished Jan 17 02:56:19 PM PST 24
Peak memory 255400 kb
Host smart-9c58c366-8868-4361-8042-7e9ae321e6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32342
90132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3234290132
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2904101066
Short name T68
Test name
Test status
Simulation time 2333230977 ps
CPU time 38.73 seconds
Started Jan 17 02:55:33 PM PST 24
Finished Jan 17 02:56:12 PM PST 24
Peak memory 254980 kb
Host smart-eb4bef5b-2120-4895-8bd3-5cb23842246b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29041
01066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2904101066
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2490263276
Short name T540
Test name
Test status
Simulation time 2466051484 ps
CPU time 30.87 seconds
Started Jan 17 02:55:34 PM PST 24
Finished Jan 17 02:56:05 PM PST 24
Peak memory 255836 kb
Host smart-537102b8-7c0d-4c38-862e-f5e16e31f688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24902
63276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2490263276
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2047327235
Short name T452
Test name
Test status
Simulation time 1725847290 ps
CPU time 31.01 seconds
Started Jan 17 02:55:34 PM PST 24
Finished Jan 17 02:56:05 PM PST 24
Peak memory 248604 kb
Host smart-73348649-2125-4029-92de-15525d054a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20473
27235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2047327235
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.4096778193
Short name T602
Test name
Test status
Simulation time 140528024393 ps
CPU time 2367.87 seconds
Started Jan 17 02:55:44 PM PST 24
Finished Jan 17 03:35:15 PM PST 24
Peak memory 289756 kb
Host smart-558b8e64-3e31-49d4-908f-c78d44615890
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096778193 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.4096778193
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.470922096
Short name T358
Test name
Test status
Simulation time 2553367397 ps
CPU time 134.49 seconds
Started Jan 17 02:55:47 PM PST 24
Finished Jan 17 02:58:02 PM PST 24
Peak memory 256296 kb
Host smart-1f69fd9d-6687-42d9-bfc3-9e1541811e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47092
2096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.470922096
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3850432719
Short name T445
Test name
Test status
Simulation time 39826639 ps
CPU time 5.83 seconds
Started Jan 17 02:55:45 PM PST 24
Finished Jan 17 02:55:53 PM PST 24
Peak memory 248184 kb
Host smart-bffd981c-5c8f-4820-a332-a4cd351aebe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38504
32719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3850432719
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.5993815
Short name T583
Test name
Test status
Simulation time 24214305195 ps
CPU time 895.72 seconds
Started Jan 17 02:55:46 PM PST 24
Finished Jan 17 03:10:43 PM PST 24
Peak memory 272732 kb
Host smart-08013731-c887-4a7e-948a-5a1fce4df722
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5993815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.5993815
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.4078094235
Short name T668
Test name
Test status
Simulation time 101048529150 ps
CPU time 1640.95 seconds
Started Jan 17 02:56:20 PM PST 24
Finished Jan 17 03:23:42 PM PST 24
Peak memory 272724 kb
Host smart-12506646-0ba4-4f75-aea1-775a6bc2bf60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078094235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.4078094235
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1833524225
Short name T10
Test name
Test status
Simulation time 78003522292 ps
CPU time 687.82 seconds
Started Jan 17 02:55:47 PM PST 24
Finished Jan 17 03:07:16 PM PST 24
Peak memory 247616 kb
Host smart-d307efdc-550e-43f7-94bc-f559bd99cbf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833524225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1833524225
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.567069800
Short name T365
Test name
Test status
Simulation time 108185081 ps
CPU time 11.21 seconds
Started Jan 17 02:55:47 PM PST 24
Finished Jan 17 02:55:59 PM PST 24
Peak memory 248664 kb
Host smart-25ba5700-294d-4939-b3a0-ac1abefa6fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56706
9800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.567069800
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.489559557
Short name T721
Test name
Test status
Simulation time 2870912194 ps
CPU time 46.95 seconds
Started Jan 17 02:55:44 PM PST 24
Finished Jan 17 02:56:34 PM PST 24
Peak memory 255520 kb
Host smart-1d561193-547a-4bbc-8c46-a33a2e42fa36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48955
9557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.489559557
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1360273819
Short name T654
Test name
Test status
Simulation time 2243369227 ps
CPU time 43.67 seconds
Started Jan 17 02:55:47 PM PST 24
Finished Jan 17 02:56:31 PM PST 24
Peak memory 247568 kb
Host smart-02729f1a-0e51-4cf5-8dfd-18fb43de12b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13602
73819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1360273819
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1442237640
Short name T482
Test name
Test status
Simulation time 218999568 ps
CPU time 16.54 seconds
Started Jan 17 02:55:44 PM PST 24
Finished Jan 17 02:56:04 PM PST 24
Peak memory 256840 kb
Host smart-b3eaafea-4571-4a38-96c6-a060dfdb2716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14422
37640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1442237640
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.568985654
Short name T708
Test name
Test status
Simulation time 6833566099 ps
CPU time 729.79 seconds
Started Jan 17 02:56:19 PM PST 24
Finished Jan 17 03:08:29 PM PST 24
Peak memory 269220 kb
Host smart-5964e7b1-5ff6-40bd-8f2b-1e6f3546c7e6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568985654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.568985654
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.106940451
Short name T107
Test name
Test status
Simulation time 225365106703 ps
CPU time 5015.52 seconds
Started Jan 17 02:56:20 PM PST 24
Finished Jan 17 04:19:56 PM PST 24
Peak memory 322356 kb
Host smart-6d839cd2-b967-4a36-a77b-19c32cd6a79c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106940451 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.106940451
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.4045406255
Short name T493
Test name
Test status
Simulation time 62368889828 ps
CPU time 1875.28 seconds
Started Jan 17 02:56:23 PM PST 24
Finished Jan 17 03:27:39 PM PST 24
Peak memory 268268 kb
Host smart-78c28129-d7c6-4a42-8dd1-241c1e1b7bfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045406255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.4045406255
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3003605340
Short name T653
Test name
Test status
Simulation time 10288036238 ps
CPU time 289.56 seconds
Started Jan 17 02:56:20 PM PST 24
Finished Jan 17 03:01:10 PM PST 24
Peak memory 256256 kb
Host smart-61ab6eec-11bc-4584-bc9c-0a4f163431ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30036
05340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3003605340
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.670213214
Short name T627
Test name
Test status
Simulation time 250638554 ps
CPU time 21.72 seconds
Started Jan 17 02:56:19 PM PST 24
Finished Jan 17 02:56:42 PM PST 24
Peak memory 254960 kb
Host smart-8589de2e-7b43-4751-883f-2b334d7d758e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67021
3214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.670213214
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.622052471
Short name T471
Test name
Test status
Simulation time 181169650202 ps
CPU time 2467.17 seconds
Started Jan 17 02:56:19 PM PST 24
Finished Jan 17 03:37:27 PM PST 24
Peak memory 284856 kb
Host smart-c26c71a1-0bec-49c3-9e56-edcdf89c07e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622052471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.622052471
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1687194498
Short name T313
Test name
Test status
Simulation time 3857465855 ps
CPU time 155.51 seconds
Started Jan 17 02:56:21 PM PST 24
Finished Jan 17 02:58:57 PM PST 24
Peak memory 247140 kb
Host smart-582b2ccc-51b7-426f-ae92-78de30a6a506
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687194498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1687194498
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2620745782
Short name T405
Test name
Test status
Simulation time 1125907394 ps
CPU time 65.29 seconds
Started Jan 17 02:56:20 PM PST 24
Finished Jan 17 02:57:26 PM PST 24
Peak memory 255436 kb
Host smart-eec2d853-909d-472c-a347-967b5c7e0460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26207
45782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2620745782
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.234415072
Short name T87
Test name
Test status
Simulation time 726849318 ps
CPU time 51.47 seconds
Started Jan 17 02:56:20 PM PST 24
Finished Jan 17 02:57:12 PM PST 24
Peak memory 254996 kb
Host smart-13e5802d-3bac-4ae9-a4ef-953f9f880600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23441
5072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.234415072
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1603070274
Short name T52
Test name
Test status
Simulation time 148751200 ps
CPU time 21.16 seconds
Started Jan 17 02:56:20 PM PST 24
Finished Jan 17 02:56:42 PM PST 24
Peak memory 248624 kb
Host smart-e99cf2df-e082-4264-b57b-9e0a456b5877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16030
70274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1603070274
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3308164442
Short name T458
Test name
Test status
Simulation time 6820515160 ps
CPU time 49.16 seconds
Started Jan 17 02:56:21 PM PST 24
Finished Jan 17 02:57:11 PM PST 24
Peak memory 248732 kb
Host smart-c1b4e322-113c-416b-bdc6-4b3b9868804d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33081
64442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3308164442
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1100189299
Short name T226
Test name
Test status
Simulation time 700666781830 ps
CPU time 3668.7 seconds
Started Jan 17 02:56:14 PM PST 24
Finished Jan 17 03:57:24 PM PST 24
Peak memory 297864 kb
Host smart-b6c044ae-4e7b-4e99-9a3e-41831066677d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100189299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1100189299
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.1320416366
Short name T601
Test name
Test status
Simulation time 51983870476 ps
CPU time 5266.14 seconds
Started Jan 17 02:56:13 PM PST 24
Finished Jan 17 04:24:00 PM PST 24
Peak memory 333224 kb
Host smart-e5e125b4-1d39-499e-a005-c066725c1a71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320416366 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.1320416366
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.117009614
Short name T56
Test name
Test status
Simulation time 112339090991 ps
CPU time 1082.81 seconds
Started Jan 17 02:56:27 PM PST 24
Finished Jan 17 03:14:30 PM PST 24
Peak memory 289004 kb
Host smart-4655a4a4-12b9-4bd1-8cc4-cedb8f866373
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117009614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.117009614
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1617907074
Short name T426
Test name
Test status
Simulation time 2263552662 ps
CPU time 134.5 seconds
Started Jan 17 02:56:18 PM PST 24
Finished Jan 17 02:58:33 PM PST 24
Peak memory 256204 kb
Host smart-c0520abb-185f-492f-9d1e-bf728b03d8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16179
07074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1617907074
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2018656135
Short name T79
Test name
Test status
Simulation time 2614570571 ps
CPU time 29.07 seconds
Started Jan 17 02:56:19 PM PST 24
Finished Jan 17 02:56:49 PM PST 24
Peak memory 254380 kb
Host smart-d51a72c1-dfe9-4163-b442-1f7341913ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20186
56135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2018656135
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3261228254
Short name T294
Test name
Test status
Simulation time 47571598896 ps
CPU time 2548.32 seconds
Started Jan 17 02:56:28 PM PST 24
Finished Jan 17 03:38:57 PM PST 24
Peak memory 289352 kb
Host smart-5f350386-1c20-4f04-93d3-c658319393c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261228254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3261228254
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.4109457522
Short name T5
Test name
Test status
Simulation time 212913483132 ps
CPU time 1910.82 seconds
Started Jan 17 02:56:27 PM PST 24
Finished Jan 17 03:28:19 PM PST 24
Peak memory 273352 kb
Host smart-e6f6b50f-ab61-4209-bdae-50d927e0ba9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109457522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.4109457522
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1275109081
Short name T566
Test name
Test status
Simulation time 12259320943 ps
CPU time 481.73 seconds
Started Jan 17 02:56:25 PM PST 24
Finished Jan 17 03:04:27 PM PST 24
Peak memory 247584 kb
Host smart-e98e2af3-bcd1-4f25-aa29-8818ebd66876
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275109081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1275109081
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3557334274
Short name T535
Test name
Test status
Simulation time 2233412898 ps
CPU time 36.08 seconds
Started Jan 17 02:56:17 PM PST 24
Finished Jan 17 02:56:54 PM PST 24
Peak memory 248616 kb
Host smart-a6ed623d-d98e-4e8c-8e1e-aeb687c98164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35573
34274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3557334274
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3588606308
Short name T472
Test name
Test status
Simulation time 543167705 ps
CPU time 35.88 seconds
Started Jan 17 02:56:17 PM PST 24
Finished Jan 17 02:56:54 PM PST 24
Peak memory 255208 kb
Host smart-f7ae1669-37ae-43e0-9c6d-65b4f9e1671e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35886
06308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3588606308
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3312221330
Short name T600
Test name
Test status
Simulation time 471501532 ps
CPU time 29.5 seconds
Started Jan 17 02:56:25 PM PST 24
Finished Jan 17 02:56:55 PM PST 24
Peak memory 248128 kb
Host smart-6952ce45-b50b-4d76-ba13-615ffc48fb97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33122
21330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3312221330
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3373311767
Short name T656
Test name
Test status
Simulation time 1857087163 ps
CPU time 30.99 seconds
Started Jan 17 02:56:14 PM PST 24
Finished Jan 17 02:56:45 PM PST 24
Peak memory 248696 kb
Host smart-102da5a3-dac9-4702-9f94-1620649190b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33733
11767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3373311767
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2823366233
Short name T461
Test name
Test status
Simulation time 110602850139 ps
CPU time 1891.74 seconds
Started Jan 17 02:56:26 PM PST 24
Finished Jan 17 03:27:59 PM PST 24
Peak memory 301224 kb
Host smart-dc218155-de1d-4301-991c-d7d763adf3d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823366233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2823366233
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.945155480
Short name T618
Test name
Test status
Simulation time 71586811092 ps
CPU time 1780.13 seconds
Started Jan 17 02:56:37 PM PST 24
Finished Jan 17 03:26:20 PM PST 24
Peak memory 289704 kb
Host smart-793560d8-f6ab-4283-95bb-00a2e7e81d0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945155480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.945155480
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2901854508
Short name T510
Test name
Test status
Simulation time 678137650 ps
CPU time 50.79 seconds
Started Jan 17 02:56:38 PM PST 24
Finished Jan 17 02:57:31 PM PST 24
Peak memory 256140 kb
Host smart-bdd5298b-bab5-47fe-a94e-b06cb47ac9d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29018
54508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2901854508
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3112811646
Short name T401
Test name
Test status
Simulation time 122654105 ps
CPU time 8.32 seconds
Started Jan 17 02:56:49 PM PST 24
Finished Jan 17 02:56:58 PM PST 24
Peak memory 240396 kb
Host smart-4b7b717b-03d2-4269-8194-97876c7f967d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31128
11646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3112811646
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.606870260
Short name T329
Test name
Test status
Simulation time 36707918009 ps
CPU time 1980.35 seconds
Started Jan 17 02:56:38 PM PST 24
Finished Jan 17 03:29:40 PM PST 24
Peak memory 282500 kb
Host smart-393801d1-bf96-47da-8e9b-1ae069e3bbf2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606870260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.606870260
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.419694726
Short name T326
Test name
Test status
Simulation time 22131018157 ps
CPU time 1349.03 seconds
Started Jan 17 02:56:38 PM PST 24
Finished Jan 17 03:19:09 PM PST 24
Peak memory 273316 kb
Host smart-24cf966e-658e-425c-8a8a-6600d045cfd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419694726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.419694726
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3473319738
Short name T284
Test name
Test status
Simulation time 67281382889 ps
CPU time 516.65 seconds
Started Jan 17 02:56:44 PM PST 24
Finished Jan 17 03:05:21 PM PST 24
Peak memory 247324 kb
Host smart-3baaeab8-9845-4b1b-a188-af6ff18393c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473319738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3473319738
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1980003800
Short name T490
Test name
Test status
Simulation time 2261922753 ps
CPU time 38.06 seconds
Started Jan 17 02:56:51 PM PST 24
Finished Jan 17 02:57:30 PM PST 24
Peak memory 255696 kb
Host smart-55fe5e84-b682-439e-b7ac-c606763ff17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19800
03800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1980003800
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2325054021
Short name T612
Test name
Test status
Simulation time 7431869613 ps
CPU time 21.76 seconds
Started Jan 17 02:56:49 PM PST 24
Finished Jan 17 02:57:12 PM PST 24
Peak memory 255048 kb
Host smart-d5aa5733-c981-46cd-861a-4b65ec55645d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23250
54021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2325054021
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1003681553
Short name T723
Test name
Test status
Simulation time 175482281 ps
CPU time 14.63 seconds
Started Jan 17 02:56:44 PM PST 24
Finished Jan 17 02:56:59 PM PST 24
Peak memory 253724 kb
Host smart-c76b119d-afcd-4c72-9e2b-1207b524b732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10036
81553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1003681553
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1347246287
Short name T368
Test name
Test status
Simulation time 8715278809 ps
CPU time 56.53 seconds
Started Jan 17 02:56:49 PM PST 24
Finished Jan 17 02:57:47 PM PST 24
Peak memory 255656 kb
Host smart-14e29187-0fe3-4f8f-8016-d1fbf4cca87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13472
46287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1347246287
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1502301008
Short name T254
Test name
Test status
Simulation time 238275079410 ps
CPU time 2492.51 seconds
Started Jan 17 02:56:49 PM PST 24
Finished Jan 17 03:38:23 PM PST 24
Peak memory 289472 kb
Host smart-59006323-b5e4-40be-ba1c-ecae73523345
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502301008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1502301008
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1106845027
Short name T202
Test name
Test status
Simulation time 53242595 ps
CPU time 2.54 seconds
Started Jan 17 02:49:03 PM PST 24
Finished Jan 17 02:49:12 PM PST 24
Peak memory 248844 kb
Host smart-337d21f2-8652-4c41-b552-121d0e81e0bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1106845027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1106845027
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2347429863
Short name T456
Test name
Test status
Simulation time 79088205515 ps
CPU time 961.47 seconds
Started Jan 17 02:49:03 PM PST 24
Finished Jan 17 03:05:11 PM PST 24
Peak memory 273008 kb
Host smart-635eeed8-1103-4d2b-9ed8-23b0d8fed94e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347429863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2347429863
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3456416683
Short name T18
Test name
Test status
Simulation time 460145191 ps
CPU time 22.89 seconds
Started Jan 17 02:49:07 PM PST 24
Finished Jan 17 02:49:33 PM PST 24
Peak memory 240452 kb
Host smart-a119f0c1-aa17-4f34-8110-7e7ee4608e32
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3456416683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3456416683
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1673963338
Short name T355
Test name
Test status
Simulation time 5868261779 ps
CPU time 90.34 seconds
Started Jan 17 02:49:05 PM PST 24
Finished Jan 17 02:50:40 PM PST 24
Peak memory 248932 kb
Host smart-7e52eca7-cf99-4d6c-9d0f-36ff49aabc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16739
63338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1673963338
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1850134763
Short name T428
Test name
Test status
Simulation time 452637892 ps
CPU time 7.22 seconds
Started Jan 17 02:48:58 PM PST 24
Finished Jan 17 02:49:08 PM PST 24
Peak memory 252256 kb
Host smart-fb3c10ee-963c-4101-bdfa-19e24eb053dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18501
34763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1850134763
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.767669322
Short name T576
Test name
Test status
Simulation time 76880684788 ps
CPU time 2451.48 seconds
Started Jan 17 02:49:04 PM PST 24
Finished Jan 17 03:30:01 PM PST 24
Peak memory 289684 kb
Host smart-2a3aeff2-95d1-4506-a0b4-cfc678ba79c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767669322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.767669322
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1706927781
Short name T398
Test name
Test status
Simulation time 14442112611 ps
CPU time 760.5 seconds
Started Jan 17 02:49:03 PM PST 24
Finished Jan 17 03:01:50 PM PST 24
Peak memory 272888 kb
Host smart-41b7299d-c36d-46cb-9eef-91ca04a337c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706927781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1706927781
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2526628231
Short name T705
Test name
Test status
Simulation time 14136521479 ps
CPU time 153.7 seconds
Started Jan 17 02:49:04 PM PST 24
Finished Jan 17 02:51:43 PM PST 24
Peak memory 248652 kb
Host smart-9cf2db8c-8bac-4fb6-93b2-321e7a2e3793
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526628231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2526628231
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1168005457
Short name T713
Test name
Test status
Simulation time 10620465838 ps
CPU time 57.69 seconds
Started Jan 17 02:48:58 PM PST 24
Finished Jan 17 02:49:57 PM PST 24
Peak memory 248752 kb
Host smart-3fb60da6-e965-47a2-b919-11223abd4ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11680
05457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1168005457
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1480101461
Short name T494
Test name
Test status
Simulation time 3253995297 ps
CPU time 54.7 seconds
Started Jan 17 02:48:57 PM PST 24
Finished Jan 17 02:49:53 PM PST 24
Peak memory 248360 kb
Host smart-1ddab637-189e-4141-8ecf-818cefb52047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14801
01461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1480101461
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1380183812
Short name T42
Test name
Test status
Simulation time 1122308649 ps
CPU time 47.43 seconds
Started Jan 17 02:49:04 PM PST 24
Finished Jan 17 02:49:57 PM PST 24
Peak memory 277140 kb
Host smart-ddb84ecd-032e-445a-b7ea-708d35b0839d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1380183812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1380183812
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2773223676
Short name T478
Test name
Test status
Simulation time 210881447 ps
CPU time 22.65 seconds
Started Jan 17 02:49:06 PM PST 24
Finished Jan 17 02:49:32 PM PST 24
Peak memory 255020 kb
Host smart-32e35e06-7edc-41c1-a0bd-ce93ce40dd07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27732
23676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2773223676
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2118357320
Short name T683
Test name
Test status
Simulation time 4933456044 ps
CPU time 58.45 seconds
Started Jan 17 02:48:50 PM PST 24
Finished Jan 17 02:49:49 PM PST 24
Peak memory 248792 kb
Host smart-b80bd310-24fb-4f1f-97e8-295965fcd3fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21183
57320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2118357320
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3981017069
Short name T682
Test name
Test status
Simulation time 9540070825 ps
CPU time 246.7 seconds
Started Jan 17 02:49:03 PM PST 24
Finished Jan 17 02:53:16 PM PST 24
Peak memory 256856 kb
Host smart-ddebf49f-ad4f-4fca-b37c-685da58c12a4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981017069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3981017069
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.145358800
Short name T700
Test name
Test status
Simulation time 378077931787 ps
CPU time 1559.94 seconds
Started Jan 17 02:56:59 PM PST 24
Finished Jan 17 03:23:02 PM PST 24
Peak memory 272236 kb
Host smart-9a7b7dc5-7a6c-40fc-b33e-b7d627090143
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145358800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.145358800
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2345207410
Short name T573
Test name
Test status
Simulation time 1167231539 ps
CPU time 105.25 seconds
Started Jan 17 02:56:57 PM PST 24
Finished Jan 17 02:58:48 PM PST 24
Peak memory 248568 kb
Host smart-b8860e75-69b3-489d-8dba-2e42f8ea24b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23452
07410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2345207410
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.177966767
Short name T72
Test name
Test status
Simulation time 256232991 ps
CPU time 15.77 seconds
Started Jan 17 02:56:53 PM PST 24
Finished Jan 17 02:57:11 PM PST 24
Peak memory 252516 kb
Host smart-c09ccbd3-44a9-49f1-ace5-83b6bbbe52bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17796
6767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.177966767
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3596889356
Short name T327
Test name
Test status
Simulation time 75671402206 ps
CPU time 2147.48 seconds
Started Jan 17 02:56:59 PM PST 24
Finished Jan 17 03:32:50 PM PST 24
Peak memory 280792 kb
Host smart-1dc68c22-7788-4c14-85b0-bf7878a3b029
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596889356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3596889356
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1635791235
Short name T481
Test name
Test status
Simulation time 17440023707 ps
CPU time 1227.37 seconds
Started Jan 17 02:57:00 PM PST 24
Finished Jan 17 03:17:30 PM PST 24
Peak memory 265056 kb
Host smart-52cc4e1f-5c2a-4eac-9dc1-6876b8312fe9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635791235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1635791235
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.15323396
Short name T603
Test name
Test status
Simulation time 11547372541 ps
CPU time 489.41 seconds
Started Jan 17 02:57:01 PM PST 24
Finished Jan 17 03:05:12 PM PST 24
Peak memory 254072 kb
Host smart-9bcaebc6-56b9-48a3-80df-019c5ca91915
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15323396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.15323396
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1908840323
Short name T414
Test name
Test status
Simulation time 21530288 ps
CPU time 3.22 seconds
Started Jan 17 02:56:53 PM PST 24
Finished Jan 17 02:56:58 PM PST 24
Peak memory 240412 kb
Host smart-95efdab5-29ce-4a48-a461-8c5a14c85cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19088
40323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1908840323
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3094765992
Short name T76
Test name
Test status
Simulation time 621453366 ps
CPU time 16.02 seconds
Started Jan 17 02:56:52 PM PST 24
Finished Jan 17 02:57:09 PM PST 24
Peak memory 248672 kb
Host smart-0b8d3922-4abe-4f3e-9e66-b4de47292423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30947
65992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3094765992
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1836986203
Short name T544
Test name
Test status
Simulation time 486272174 ps
CPU time 34.97 seconds
Started Jan 17 02:56:54 PM PST 24
Finished Jan 17 02:57:30 PM PST 24
Peak memory 248616 kb
Host smart-d22dc274-61f5-48e4-8588-c205e014671f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18369
86203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1836986203
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2062071367
Short name T521
Test name
Test status
Simulation time 2839282155 ps
CPU time 42.53 seconds
Started Jan 17 02:56:56 PM PST 24
Finished Jan 17 02:57:45 PM PST 24
Peak memory 248784 kb
Host smart-d8667798-5603-4d46-8c10-651835fcda8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20620
71367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2062071367
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1591223290
Short name T238
Test name
Test status
Simulation time 114366040352 ps
CPU time 3285.2 seconds
Started Jan 17 02:57:00 PM PST 24
Finished Jan 17 03:51:48 PM PST 24
Peak memory 289620 kb
Host smart-0d4cde51-5250-43fa-9351-0af0c32e245e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591223290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1591223290
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3082804273
Short name T113
Test name
Test status
Simulation time 16990525916 ps
CPU time 994.05 seconds
Started Jan 17 02:56:59 PM PST 24
Finished Jan 17 03:13:37 PM PST 24
Peak memory 268240 kb
Host smart-f46f7021-bd60-46ed-8a4c-99b5edd1a537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082804273 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3082804273
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.325078781
Short name T594
Test name
Test status
Simulation time 17373006067 ps
CPU time 1559.51 seconds
Started Jan 17 02:57:08 PM PST 24
Finished Jan 17 03:23:08 PM PST 24
Peak memory 281224 kb
Host smart-d4aee0d7-927e-47c8-b79a-e390c58ddbb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325078781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.325078781
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.346061014
Short name T483
Test name
Test status
Simulation time 12265689990 ps
CPU time 179.33 seconds
Started Jan 17 02:57:11 PM PST 24
Finished Jan 17 03:00:11 PM PST 24
Peak memory 249704 kb
Host smart-4e71e346-d646-41dc-b427-6660cb870c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34606
1014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.346061014
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1892782352
Short name T536
Test name
Test status
Simulation time 328547182 ps
CPU time 14.73 seconds
Started Jan 17 02:57:00 PM PST 24
Finished Jan 17 02:57:17 PM PST 24
Peak memory 248616 kb
Host smart-f0461146-4505-491c-9589-c5f2a0b2fdfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18927
82352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1892782352
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3424878683
Short name T319
Test name
Test status
Simulation time 257925782545 ps
CPU time 1267.09 seconds
Started Jan 17 02:57:13 PM PST 24
Finished Jan 17 03:18:21 PM PST 24
Peak memory 289300 kb
Host smart-416fe1c8-4e2b-4a32-b9cd-86ca8c1a1eff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424878683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3424878683
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1783008213
Short name T688
Test name
Test status
Simulation time 30151271733 ps
CPU time 670.98 seconds
Started Jan 17 02:57:13 PM PST 24
Finished Jan 17 03:08:25 PM PST 24
Peak memory 272184 kb
Host smart-46a6e8f8-7150-40c6-8824-e7ad9411a180
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783008213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1783008213
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.907916554
Short name T295
Test name
Test status
Simulation time 3834596888 ps
CPU time 161.43 seconds
Started Jan 17 02:57:09 PM PST 24
Finished Jan 17 02:59:51 PM PST 24
Peak memory 246564 kb
Host smart-e79de36a-b225-47f6-b9c5-f49d616da0cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907916554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.907916554
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2223825139
Short name T591
Test name
Test status
Simulation time 4969600541 ps
CPU time 30.65 seconds
Started Jan 17 02:56:59 PM PST 24
Finished Jan 17 02:57:33 PM PST 24
Peak memory 254888 kb
Host smart-e76ac147-ff13-47e4-9069-297a9aed0c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22238
25139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2223825139
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.124604978
Short name T639
Test name
Test status
Simulation time 1316264295 ps
CPU time 33.31 seconds
Started Jan 17 02:56:58 PM PST 24
Finished Jan 17 02:57:36 PM PST 24
Peak memory 248024 kb
Host smart-c713a520-fba3-4314-a7bb-f1833f933049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12460
4978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.124604978
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3342648790
Short name T629
Test name
Test status
Simulation time 64080762 ps
CPU time 8.04 seconds
Started Jan 17 02:57:08 PM PST 24
Finished Jan 17 02:57:16 PM PST 24
Peak memory 246664 kb
Host smart-cd6877e9-f67d-4964-8c2b-f614a3eb2259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33426
48790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3342648790
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3275403647
Short name T568
Test name
Test status
Simulation time 211106959 ps
CPU time 19.69 seconds
Started Jan 17 02:57:02 PM PST 24
Finished Jan 17 02:57:24 PM PST 24
Peak memory 255328 kb
Host smart-1c4aa2a0-fd78-4b77-bbbc-dc7efb96372d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32754
03647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3275403647
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1577934058
Short name T55
Test name
Test status
Simulation time 45274126212 ps
CPU time 2154.58 seconds
Started Jan 17 02:57:13 PM PST 24
Finished Jan 17 03:33:09 PM PST 24
Peak memory 297820 kb
Host smart-d3ae6b2c-ef6a-4e40-b620-e89f2422bc1b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577934058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1577934058
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1971578158
Short name T681
Test name
Test status
Simulation time 89056795666 ps
CPU time 9394.76 seconds
Started Jan 17 02:57:14 PM PST 24
Finished Jan 17 05:33:50 PM PST 24
Peak memory 394568 kb
Host smart-9429a62f-cb5b-4080-9cd7-4df9837f7064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971578158 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1971578158
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1981904687
Short name T609
Test name
Test status
Simulation time 107262409127 ps
CPU time 3115.51 seconds
Started Jan 17 02:57:26 PM PST 24
Finished Jan 17 03:49:22 PM PST 24
Peak memory 289148 kb
Host smart-9ddaeb4c-1abb-4d89-b88e-a627541c76b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981904687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1981904687
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3458175728
Short name T348
Test name
Test status
Simulation time 3112394527 ps
CPU time 196.24 seconds
Started Jan 17 02:57:26 PM PST 24
Finished Jan 17 03:00:44 PM PST 24
Peak memory 256344 kb
Host smart-2768ca73-b7ea-4c5f-944a-b9b32f299ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34581
75728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3458175728
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3072363563
Short name T344
Test name
Test status
Simulation time 147442142 ps
CPU time 5.53 seconds
Started Jan 17 02:57:20 PM PST 24
Finished Jan 17 02:57:26 PM PST 24
Peak memory 238824 kb
Host smart-3b4c0551-3e56-457d-8361-3e120918d0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30723
63563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3072363563
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1488434305
Short name T293
Test name
Test status
Simulation time 34024418108 ps
CPU time 2117.54 seconds
Started Jan 17 02:57:28 PM PST 24
Finished Jan 17 03:32:47 PM PST 24
Peak memory 287988 kb
Host smart-5101f9f9-6660-4572-bd9e-45d75d9e51d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488434305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1488434305
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.4041088219
Short name T689
Test name
Test status
Simulation time 107944743198 ps
CPU time 3249.04 seconds
Started Jan 17 02:57:26 PM PST 24
Finished Jan 17 03:51:36 PM PST 24
Peak memory 289620 kb
Host smart-4926b0d5-7e79-4a40-a07c-2b475ac2fff3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041088219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.4041088219
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.181755229
Short name T307
Test name
Test status
Simulation time 4848135676 ps
CPU time 204.73 seconds
Started Jan 17 02:57:26 PM PST 24
Finished Jan 17 03:00:51 PM PST 24
Peak memory 247312 kb
Host smart-b6f4c003-5eb4-4d13-8428-6d5b3da7b249
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181755229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.181755229
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.851321455
Short name T516
Test name
Test status
Simulation time 414570050 ps
CPU time 26.6 seconds
Started Jan 17 02:57:20 PM PST 24
Finished Jan 17 02:57:47 PM PST 24
Peak memory 248648 kb
Host smart-66a12bae-eaae-4573-8a17-8a370b0d2c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85132
1455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.851321455
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3370237702
Short name T581
Test name
Test status
Simulation time 605469530 ps
CPU time 33.96 seconds
Started Jan 17 02:57:23 PM PST 24
Finished Jan 17 02:57:57 PM PST 24
Peak memory 256056 kb
Host smart-86aaba40-3c5f-43af-a530-89e13b994fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33702
37702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3370237702
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2443005092
Short name T567
Test name
Test status
Simulation time 2330929250 ps
CPU time 45.51 seconds
Started Jan 17 02:57:26 PM PST 24
Finished Jan 17 02:58:13 PM PST 24
Peak memory 254864 kb
Host smart-df9a605e-38ab-401e-a043-bb69c4b850a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24430
05092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2443005092
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2499760939
Short name T632
Test name
Test status
Simulation time 181998533 ps
CPU time 7.84 seconds
Started Jan 17 02:57:19 PM PST 24
Finished Jan 17 02:57:27 PM PST 24
Peak memory 253572 kb
Host smart-5fc84c40-857d-4669-81a0-20b05b1ff90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24997
60939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2499760939
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.4121207474
Short name T729
Test name
Test status
Simulation time 40998524937 ps
CPU time 1399.61 seconds
Started Jan 17 02:57:27 PM PST 24
Finished Jan 17 03:20:48 PM PST 24
Peak memory 289616 kb
Host smart-1037f12e-a6a8-4e2e-81de-769c2447fa26
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121207474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.4121207474
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3194094023
Short name T106
Test name
Test status
Simulation time 119870790657 ps
CPU time 6706.23 seconds
Started Jan 17 02:57:33 PM PST 24
Finished Jan 17 04:49:23 PM PST 24
Peak memory 366932 kb
Host smart-d081a2ea-ec4c-4ccf-827f-37fb0a59d524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194094023 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3194094023
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1030441290
Short name T440
Test name
Test status
Simulation time 195682884961 ps
CPU time 1613.85 seconds
Started Jan 17 02:57:38 PM PST 24
Finished Jan 17 03:24:32 PM PST 24
Peak memory 288964 kb
Host smart-8a3a1404-b489-4e9b-8df5-be00a2c58cbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030441290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1030441290
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1180114899
Short name T675
Test name
Test status
Simulation time 913713962 ps
CPU time 78.64 seconds
Started Jan 17 02:57:38 PM PST 24
Finished Jan 17 02:58:57 PM PST 24
Peak memory 255952 kb
Host smart-5edf0643-4e95-4cfb-a48a-8552ca0c1f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11801
14899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1180114899
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3622431631
Short name T85
Test name
Test status
Simulation time 1780482013 ps
CPU time 59.48 seconds
Started Jan 17 02:57:33 PM PST 24
Finished Jan 17 02:58:35 PM PST 24
Peak memory 255020 kb
Host smart-d2fb330c-d331-4e07-bace-41f2f34eabe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36224
31631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3622431631
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3452867207
Short name T325
Test name
Test status
Simulation time 66120547362 ps
CPU time 1397.35 seconds
Started Jan 17 02:57:37 PM PST 24
Finished Jan 17 03:20:55 PM PST 24
Peak memory 281500 kb
Host smart-580d425f-cb4f-44ab-a827-2dd5742c3d31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452867207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3452867207
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3053281581
Short name T427
Test name
Test status
Simulation time 26548845046 ps
CPU time 1052.6 seconds
Started Jan 17 02:57:39 PM PST 24
Finished Jan 17 03:15:12 PM PST 24
Peak memory 281444 kb
Host smart-eb71a613-a5cf-4b59-8f20-d13b30201581
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053281581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3053281581
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3194171181
Short name T11
Test name
Test status
Simulation time 2071276424 ps
CPU time 91.28 seconds
Started Jan 17 02:57:38 PM PST 24
Finished Jan 17 02:59:10 PM PST 24
Peak memory 247208 kb
Host smart-4125a4b1-f4d5-4a16-8fe4-7b5fa9422fb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194171181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3194171181
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3119789926
Short name T506
Test name
Test status
Simulation time 232952358 ps
CPU time 17.29 seconds
Started Jan 17 02:57:35 PM PST 24
Finished Jan 17 02:57:53 PM PST 24
Peak memory 255268 kb
Host smart-ef7630e4-ed3c-4161-88db-6224d96717e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31197
89926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3119789926
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3955327282
Short name T491
Test name
Test status
Simulation time 2843957259 ps
CPU time 40.38 seconds
Started Jan 17 02:57:35 PM PST 24
Finished Jan 17 02:58:16 PM PST 24
Peak memory 248236 kb
Host smart-4346b0fd-6155-43f0-bcb6-80ee80b998c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39553
27282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3955327282
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.152354148
Short name T109
Test name
Test status
Simulation time 153000175 ps
CPU time 18.26 seconds
Started Jan 17 02:57:37 PM PST 24
Finished Jan 17 02:57:56 PM PST 24
Peak memory 255356 kb
Host smart-fb885106-8874-4276-bf84-cf37c95a0de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15235
4148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.152354148
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.661479102
Short name T477
Test name
Test status
Simulation time 18953321418 ps
CPU time 65.18 seconds
Started Jan 17 02:57:35 PM PST 24
Finished Jan 17 02:58:41 PM PST 24
Peak memory 248784 kb
Host smart-00811dc3-5714-40e2-b7d2-462554a39d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66147
9102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.661479102
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3672433614
Short name T235
Test name
Test status
Simulation time 766263242247 ps
CPU time 10092.1 seconds
Started Jan 17 02:57:45 PM PST 24
Finished Jan 17 05:45:59 PM PST 24
Peak memory 392384 kb
Host smart-1fe2944f-dff6-4529-8d4f-71c8f6f5af2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672433614 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3672433614
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.70848477
Short name T6
Test name
Test status
Simulation time 36927692590 ps
CPU time 872.54 seconds
Started Jan 17 02:57:53 PM PST 24
Finished Jan 17 03:12:28 PM PST 24
Peak memory 273108 kb
Host smart-a90a39a1-9976-45dd-a2ad-f1cb36230ff8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70848477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.70848477
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3488090581
Short name T376
Test name
Test status
Simulation time 16523348682 ps
CPU time 298.6 seconds
Started Jan 17 02:57:53 PM PST 24
Finished Jan 17 03:02:54 PM PST 24
Peak memory 256828 kb
Host smart-e63af044-dc98-4950-bd22-aba16e0a2325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34880
90581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3488090581
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3672986887
Short name T469
Test name
Test status
Simulation time 428837104 ps
CPU time 22.52 seconds
Started Jan 17 02:57:45 PM PST 24
Finished Jan 17 02:58:09 PM PST 24
Peak memory 254396 kb
Host smart-b8e61935-11fb-405d-b58d-f186cce53654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36729
86887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3672986887
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1934498478
Short name T625
Test name
Test status
Simulation time 13322078737 ps
CPU time 944.42 seconds
Started Jan 17 02:58:00 PM PST 24
Finished Jan 17 03:13:47 PM PST 24
Peak memory 283012 kb
Host smart-76719b97-58c2-4348-8377-9b5f9abf38ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934498478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1934498478
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2872044204
Short name T475
Test name
Test status
Simulation time 180670506636 ps
CPU time 2278.39 seconds
Started Jan 17 02:58:00 PM PST 24
Finished Jan 17 03:36:01 PM PST 24
Peak memory 283252 kb
Host smart-445b94fa-d473-4f43-9bea-75b41d84186b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872044204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2872044204
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2160314700
Short name T716
Test name
Test status
Simulation time 7979289350 ps
CPU time 344.67 seconds
Started Jan 17 02:57:54 PM PST 24
Finished Jan 17 03:03:40 PM PST 24
Peak memory 248692 kb
Host smart-4de5a513-a478-4a18-bfa0-02958dae5b83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160314700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2160314700
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2792669048
Short name T523
Test name
Test status
Simulation time 2724014147 ps
CPU time 43.29 seconds
Started Jan 17 02:57:44 PM PST 24
Finished Jan 17 02:58:28 PM PST 24
Peak memory 249144 kb
Host smart-8cda80b3-30b7-4c3b-95c7-5108fc4dea33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27926
69048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2792669048
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2704111333
Short name T95
Test name
Test status
Simulation time 1249245399 ps
CPU time 30.09 seconds
Started Jan 17 02:57:45 PM PST 24
Finished Jan 17 02:58:16 PM PST 24
Peak memory 254976 kb
Host smart-759a7d2c-069b-4571-b6a7-720fc312379d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27041
11333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2704111333
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.429944666
Short name T453
Test name
Test status
Simulation time 1153198552 ps
CPU time 25.86 seconds
Started Jan 17 02:57:51 PM PST 24
Finished Jan 17 02:58:21 PM PST 24
Peak memory 255476 kb
Host smart-8ac89b1f-2086-46e4-8d72-48aced66d5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42994
4666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.429944666
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2657661516
Short name T665
Test name
Test status
Simulation time 568425777 ps
CPU time 37.67 seconds
Started Jan 17 02:57:45 PM PST 24
Finished Jan 17 02:58:24 PM PST 24
Peak memory 248564 kb
Host smart-63ed40cc-2994-4fd4-b575-1700d2cf63bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26576
61516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2657661516
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2078030109
Short name T572
Test name
Test status
Simulation time 1122644833 ps
CPU time 69.27 seconds
Started Jan 17 02:58:00 PM PST 24
Finished Jan 17 02:59:11 PM PST 24
Peak memory 256748 kb
Host smart-1b03d83e-c4ae-48d1-9499-74e5ccad00d5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078030109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2078030109
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2132900197
Short name T542
Test name
Test status
Simulation time 337442292431 ps
CPU time 5997.45 seconds
Started Jan 17 02:57:59 PM PST 24
Finished Jan 17 04:37:58 PM PST 24
Peak memory 319652 kb
Host smart-dfb71308-1d0f-4505-ae22-24c7ed9b922a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132900197 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2132900197
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1640393116
Short name T584
Test name
Test status
Simulation time 7466398954 ps
CPU time 747.42 seconds
Started Jan 17 02:58:04 PM PST 24
Finished Jan 17 03:10:36 PM PST 24
Peak memory 273256 kb
Host smart-dd23e01d-b8a1-423a-b900-236e661bd61a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640393116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1640393116
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3016483892
Short name T429
Test name
Test status
Simulation time 1399883773 ps
CPU time 81.67 seconds
Started Jan 17 02:58:05 PM PST 24
Finished Jan 17 02:59:30 PM PST 24
Peak memory 256136 kb
Host smart-10e55694-4acf-46a5-aa6e-62846fc45d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30164
83892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3016483892
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3961152968
Short name T388
Test name
Test status
Simulation time 389218707 ps
CPU time 11.55 seconds
Started Jan 17 02:58:05 PM PST 24
Finished Jan 17 02:58:20 PM PST 24
Peak memory 253100 kb
Host smart-02fb103d-da83-4d1d-95c9-83eac042d622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39611
52968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3961152968
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2015555871
Short name T570
Test name
Test status
Simulation time 38232017543 ps
CPU time 2686.6 seconds
Started Jan 17 02:58:10 PM PST 24
Finished Jan 17 03:42:57 PM PST 24
Peak memory 289000 kb
Host smart-7f0810c3-8d31-4f04-b3ad-3e2c8a667722
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015555871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2015555871
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1813894497
Short name T717
Test name
Test status
Simulation time 18562600296 ps
CPU time 1239.74 seconds
Started Jan 17 02:58:12 PM PST 24
Finished Jan 17 03:18:52 PM PST 24
Peak memory 272940 kb
Host smart-3efb8a58-bdaa-443c-b361-5098c298cdb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813894497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1813894497
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2374005095
Short name T279
Test name
Test status
Simulation time 51221712848 ps
CPU time 246.51 seconds
Started Jan 17 02:58:10 PM PST 24
Finished Jan 17 03:02:17 PM PST 24
Peak memory 248684 kb
Host smart-137cd339-607b-4f84-825a-e89cb53ecbb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374005095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2374005095
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3123425253
Short name T730
Test name
Test status
Simulation time 579749846 ps
CPU time 9.92 seconds
Started Jan 17 02:58:01 PM PST 24
Finished Jan 17 02:58:13 PM PST 24
Peak memory 248632 kb
Host smart-3d20c435-c5f9-4223-9197-e9391dcd7cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31234
25253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3123425253
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1194788992
Short name T272
Test name
Test status
Simulation time 349726672 ps
CPU time 33.88 seconds
Started Jan 17 02:58:04 PM PST 24
Finished Jan 17 02:58:42 PM PST 24
Peak memory 247092 kb
Host smart-faf1d7e8-c4cd-4ca7-a16d-a213b027304a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11947
88992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1194788992
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2801408681
Short name T252
Test name
Test status
Simulation time 2479888865 ps
CPU time 46.68 seconds
Started Jan 17 02:58:05 PM PST 24
Finished Jan 17 02:58:55 PM PST 24
Peak memory 255764 kb
Host smart-bee6a2a2-332f-4a54-b992-01b578422811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28014
08681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2801408681
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2764343790
Short name T384
Test name
Test status
Simulation time 474440507 ps
CPU time 32.7 seconds
Started Jan 17 02:58:00 PM PST 24
Finished Jan 17 02:58:35 PM PST 24
Peak memory 248720 kb
Host smart-5dbf92ff-380d-48f2-89bc-cf2413d266d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27643
43790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2764343790
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.7376601
Short name T624
Test name
Test status
Simulation time 4597483643 ps
CPU time 315.66 seconds
Started Jan 17 02:58:10 PM PST 24
Finished Jan 17 03:03:26 PM PST 24
Peak memory 257024 kb
Host smart-6b0ade24-6fb6-4d98-945f-1df9e5ef0cc3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7376601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handl
er_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handl
er_stress_all.7376601
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2391611300
Short name T543
Test name
Test status
Simulation time 298124412771 ps
CPU time 6491.53 seconds
Started Jan 17 02:58:11 PM PST 24
Finished Jan 17 04:46:24 PM PST 24
Peak memory 347056 kb
Host smart-81bf75e9-b67f-4ef1-9094-19517b497c64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391611300 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2391611300
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.770254854
Short name T728
Test name
Test status
Simulation time 22661605369 ps
CPU time 1444.56 seconds
Started Jan 17 02:58:27 PM PST 24
Finished Jan 17 03:22:33 PM PST 24
Peak memory 273060 kb
Host smart-31e3d98d-d997-48e7-ba29-069fc2e31a1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770254854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.770254854
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3774887331
Short name T46
Test name
Test status
Simulation time 19681313283 ps
CPU time 221.34 seconds
Started Jan 17 02:58:15 PM PST 24
Finished Jan 17 03:01:57 PM PST 24
Peak memory 256456 kb
Host smart-d397be6b-3aff-47fc-bb3b-7e338c44a556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37748
87331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3774887331
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1181628665
Short name T207
Test name
Test status
Simulation time 1596176479 ps
CPU time 18.36 seconds
Started Jan 17 02:58:16 PM PST 24
Finished Jan 17 02:58:36 PM PST 24
Peak memory 254280 kb
Host smart-526354d7-6bab-4bc2-89c7-3d618fca2dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11816
28665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1181628665
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.4003909804
Short name T322
Test name
Test status
Simulation time 75995789615 ps
CPU time 1196.75 seconds
Started Jan 17 02:58:25 PM PST 24
Finished Jan 17 03:18:22 PM PST 24
Peak memory 265028 kb
Host smart-aacc1fe1-ea5d-4f7b-a94b-5e7336baad57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003909804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.4003909804
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3945821204
Short name T554
Test name
Test status
Simulation time 8825216651 ps
CPU time 789.22 seconds
Started Jan 17 02:58:25 PM PST 24
Finished Jan 17 03:11:35 PM PST 24
Peak memory 269164 kb
Host smart-e80baa16-18bb-44d8-ac67-b8d973cbc6c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945821204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3945821204
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.89256188
Short name T727
Test name
Test status
Simulation time 42521882158 ps
CPU time 405.79 seconds
Started Jan 17 02:58:27 PM PST 24
Finished Jan 17 03:05:14 PM PST 24
Peak memory 247340 kb
Host smart-e0188095-6946-4889-aeec-31bdb2c001be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89256188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.89256188
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1870517744
Short name T652
Test name
Test status
Simulation time 1196712544 ps
CPU time 63.29 seconds
Started Jan 17 02:58:10 PM PST 24
Finished Jan 17 02:59:14 PM PST 24
Peak memory 248668 kb
Host smart-e332c5a7-4269-47a1-a9dd-6c6c9171113a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18705
17744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1870517744
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4227778003
Short name T370
Test name
Test status
Simulation time 891357428 ps
CPU time 16.44 seconds
Started Jan 17 02:58:11 PM PST 24
Finished Jan 17 02:58:28 PM PST 24
Peak memory 253700 kb
Host smart-65a8cabe-4b7e-4cd3-9c69-cea8dd9789b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42277
78003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4227778003
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.490191306
Short name T499
Test name
Test status
Simulation time 518296826 ps
CPU time 28.56 seconds
Started Jan 17 02:58:25 PM PST 24
Finished Jan 17 02:58:55 PM PST 24
Peak memory 247260 kb
Host smart-c33602ba-9352-4806-9f7e-585381c1e38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49019
1306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.490191306
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2044279749
Short name T274
Test name
Test status
Simulation time 1963395269 ps
CPU time 51.68 seconds
Started Jan 17 02:58:10 PM PST 24
Finished Jan 17 02:59:02 PM PST 24
Peak memory 256864 kb
Host smart-8c57ba5c-cd69-4222-aa8c-97576d36c5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20442
79749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2044279749
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3042242855
Short name T580
Test name
Test status
Simulation time 53127605146 ps
CPU time 1576.38 seconds
Started Jan 17 02:58:25 PM PST 24
Finished Jan 17 03:24:43 PM PST 24
Peak memory 289404 kb
Host smart-742b593e-414c-4f9d-a048-bab22c6a81d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042242855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3042242855
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.821138810
Short name T693
Test name
Test status
Simulation time 29813238349 ps
CPU time 2457.2 seconds
Started Jan 17 02:58:26 PM PST 24
Finished Jan 17 03:39:24 PM PST 24
Peak memory 300364 kb
Host smart-f87c40e1-ad6a-4975-bbb1-9226075ea563
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821138810 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.821138810
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2017206968
Short name T724
Test name
Test status
Simulation time 9978086912 ps
CPU time 1039.04 seconds
Started Jan 17 02:58:37 PM PST 24
Finished Jan 17 03:15:56 PM PST 24
Peak memory 287008 kb
Host smart-4b81ea20-9714-4287-817b-45758678c1e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017206968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2017206968
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1817789090
Short name T546
Test name
Test status
Simulation time 3843304502 ps
CPU time 209.18 seconds
Started Jan 17 02:58:30 PM PST 24
Finished Jan 17 03:01:59 PM PST 24
Peak memory 256356 kb
Host smart-3e32135a-d6ad-42b5-9d33-7aa332a630ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18177
89090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1817789090
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3164080703
Short name T497
Test name
Test status
Simulation time 320910824 ps
CPU time 14.59 seconds
Started Jan 17 02:58:31 PM PST 24
Finished Jan 17 02:58:50 PM PST 24
Peak memory 248076 kb
Host smart-39cbb52a-5d54-4d70-b601-80417e07bf2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31640
80703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3164080703
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.551816925
Short name T275
Test name
Test status
Simulation time 22593358882 ps
CPU time 1246.3 seconds
Started Jan 17 02:58:44 PM PST 24
Finished Jan 17 03:19:31 PM PST 24
Peak memory 265108 kb
Host smart-f61cb1ed-d991-4717-a7e9-c5576c303a01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551816925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.551816925
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.702532479
Short name T268
Test name
Test status
Simulation time 149040372938 ps
CPU time 2073.07 seconds
Started Jan 17 02:58:45 PM PST 24
Finished Jan 17 03:33:19 PM PST 24
Peak memory 282460 kb
Host smart-a84fbec0-30fb-4651-8e69-fd7600f849e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702532479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.702532479
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1884216009
Short name T607
Test name
Test status
Simulation time 8417107838 ps
CPU time 345.22 seconds
Started Jan 17 02:58:37 PM PST 24
Finished Jan 17 03:04:22 PM PST 24
Peak memory 248728 kb
Host smart-ffc934f8-4b53-4a8e-aeba-7ba61493ae57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884216009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1884216009
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2653245643
Short name T266
Test name
Test status
Simulation time 500762222 ps
CPU time 29.17 seconds
Started Jan 17 02:58:31 PM PST 24
Finished Jan 17 02:59:04 PM PST 24
Peak memory 255504 kb
Host smart-cde68aa4-d335-43a6-9876-6c1a2c180342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26532
45643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2653245643
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.4240111721
Short name T62
Test name
Test status
Simulation time 644518319 ps
CPU time 15.95 seconds
Started Jan 17 02:58:32 PM PST 24
Finished Jan 17 02:58:51 PM PST 24
Peak memory 247048 kb
Host smart-0e8bc187-5aa2-463b-836a-bc7970f80c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42401
11721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.4240111721
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1985914889
Short name T400
Test name
Test status
Simulation time 110682857 ps
CPU time 11.92 seconds
Started Jan 17 02:58:26 PM PST 24
Finished Jan 17 02:58:39 PM PST 24
Peak memory 248676 kb
Host smart-7010617a-72e9-4035-a111-aa9adaa02e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19859
14889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1985914889
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3735693852
Short name T260
Test name
Test status
Simulation time 143517198287 ps
CPU time 1345.95 seconds
Started Jan 17 02:58:45 PM PST 24
Finished Jan 17 03:21:12 PM PST 24
Peak memory 289072 kb
Host smart-ef7f5a14-5b6e-48cc-b3c6-9d46a66a1c61
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735693852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3735693852
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3493516608
Short name T466
Test name
Test status
Simulation time 172018723183 ps
CPU time 2213.4 seconds
Started Jan 17 02:59:02 PM PST 24
Finished Jan 17 03:35:57 PM PST 24
Peak memory 272944 kb
Host smart-754d3a40-dff9-411f-90a5-3fadc01b8c0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493516608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3493516608
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3844538465
Short name T547
Test name
Test status
Simulation time 3359134190 ps
CPU time 215.12 seconds
Started Jan 17 02:58:56 PM PST 24
Finished Jan 17 03:02:32 PM PST 24
Peak memory 249756 kb
Host smart-2be308ba-8eee-489f-8070-8e42795ee8e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38445
38465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3844538465
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.134366102
Short name T696
Test name
Test status
Simulation time 754714223 ps
CPU time 17.15 seconds
Started Jan 17 02:58:57 PM PST 24
Finished Jan 17 02:59:15 PM PST 24
Peak memory 253796 kb
Host smart-8bb0a884-f77f-46b8-8fac-42f40c16af00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13436
6102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.134366102
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2640240205
Short name T70
Test name
Test status
Simulation time 24113484451 ps
CPU time 1599.35 seconds
Started Jan 17 02:59:07 PM PST 24
Finished Jan 17 03:25:48 PM PST 24
Peak memory 269388 kb
Host smart-a4de0364-42fc-449d-99e3-1874bbd67046
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640240205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2640240205
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.685775775
Short name T43
Test name
Test status
Simulation time 267459536741 ps
CPU time 2537.86 seconds
Started Jan 17 02:59:04 PM PST 24
Finished Jan 17 03:41:26 PM PST 24
Peak memory 288756 kb
Host smart-a2f89b81-cfa2-4f6e-af02-4e5ef6dd7a08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685775775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.685775775
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1870039235
Short name T397
Test name
Test status
Simulation time 688396935 ps
CPU time 50.97 seconds
Started Jan 17 02:58:50 PM PST 24
Finished Jan 17 02:59:42 PM PST 24
Peak memory 248684 kb
Host smart-cb1a545d-b705-4fdb-95a9-693abb6a590a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18700
39235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1870039235
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2356914278
Short name T49
Test name
Test status
Simulation time 1060446995 ps
CPU time 17.99 seconds
Started Jan 17 02:58:56 PM PST 24
Finished Jan 17 02:59:14 PM PST 24
Peak memory 254644 kb
Host smart-55aae300-80a7-4c32-838c-2d63a0ecde06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23569
14278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2356914278
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2977497664
Short name T44
Test name
Test status
Simulation time 2237427593 ps
CPU time 77.17 seconds
Started Jan 17 02:58:56 PM PST 24
Finished Jan 17 03:00:14 PM PST 24
Peak memory 255740 kb
Host smart-f8de40e2-0007-4d21-b276-98f3e6e1256c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29774
97664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2977497664
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2043740311
Short name T419
Test name
Test status
Simulation time 1847940998 ps
CPU time 32.91 seconds
Started Jan 17 02:58:51 PM PST 24
Finished Jan 17 02:59:24 PM PST 24
Peak memory 248640 kb
Host smart-b5d4e241-c30d-4e45-b210-9b5612ce4a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20437
40311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2043740311
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.4118139483
Short name T249
Test name
Test status
Simulation time 23444738676 ps
CPU time 1324.9 seconds
Started Jan 17 02:59:05 PM PST 24
Finished Jan 17 03:21:13 PM PST 24
Peak memory 270204 kb
Host smart-738087cb-af07-40da-9eb0-126962445d0d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118139483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.4118139483
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1608924915
Short name T503
Test name
Test status
Simulation time 72886754379 ps
CPU time 1442.83 seconds
Started Jan 17 02:59:19 PM PST 24
Finished Jan 17 03:23:23 PM PST 24
Peak memory 288812 kb
Host smart-6e7967e0-cf04-49d0-855b-8314379c2846
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608924915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1608924915
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3232197218
Short name T408
Test name
Test status
Simulation time 7851970474 ps
CPU time 102.58 seconds
Started Jan 17 02:59:11 PM PST 24
Finished Jan 17 03:00:54 PM PST 24
Peak memory 256896 kb
Host smart-01dcc9e9-4c6c-43ff-b387-ff9b7290050e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32321
97218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3232197218
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.239995647
Short name T563
Test name
Test status
Simulation time 360433195 ps
CPU time 24.64 seconds
Started Jan 17 02:59:14 PM PST 24
Finished Jan 17 02:59:39 PM PST 24
Peak memory 254000 kb
Host smart-d197cc3a-4bc1-42e6-a55b-0436698dc8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23999
5647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.239995647
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3273918610
Short name T586
Test name
Test status
Simulation time 57068192661 ps
CPU time 1526.9 seconds
Started Jan 17 02:59:19 PM PST 24
Finished Jan 17 03:24:47 PM PST 24
Peak memory 272724 kb
Host smart-3116869f-0fe4-47fe-9960-4afc18ea7c94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273918610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3273918610
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2123576577
Short name T330
Test name
Test status
Simulation time 14416432597 ps
CPU time 713.06 seconds
Started Jan 17 02:59:21 PM PST 24
Finished Jan 17 03:11:14 PM PST 24
Peak memory 273192 kb
Host smart-5dbe8928-8deb-404a-bc99-4191c5ddaffa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123576577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2123576577
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1643595722
Short name T280
Test name
Test status
Simulation time 10844088779 ps
CPU time 458.76 seconds
Started Jan 17 02:59:19 PM PST 24
Finished Jan 17 03:06:59 PM PST 24
Peak memory 247596 kb
Host smart-762774e5-64cd-402d-9108-c14453b37119
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643595722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1643595722
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3169472283
Short name T537
Test name
Test status
Simulation time 98272210 ps
CPU time 7.96 seconds
Started Jan 17 02:59:06 PM PST 24
Finished Jan 17 02:59:16 PM PST 24
Peak memory 248676 kb
Host smart-e41ead8c-7f21-448b-a44e-aed64b7ebcd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31694
72283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3169472283
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.258856583
Short name T91
Test name
Test status
Simulation time 1635112708 ps
CPU time 30.82 seconds
Started Jan 17 02:59:14 PM PST 24
Finished Jan 17 02:59:45 PM PST 24
Peak memory 248104 kb
Host smart-f61c4c69-16a2-4ea7-a571-dfa7edc75014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25885
6583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.258856583
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.502127507
Short name T352
Test name
Test status
Simulation time 552466992 ps
CPU time 29.52 seconds
Started Jan 17 02:59:17 PM PST 24
Finished Jan 17 02:59:47 PM PST 24
Peak memory 248612 kb
Host smart-eb91cf62-e716-4964-ab0d-3abf1968bb05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50212
7507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.502127507
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1508873401
Short name T496
Test name
Test status
Simulation time 292227440 ps
CPU time 24.53 seconds
Started Jan 17 02:59:07 PM PST 24
Finished Jan 17 02:59:33 PM PST 24
Peak memory 248664 kb
Host smart-b78b91e0-17ae-4d1a-a56b-653a99f827c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15088
73401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1508873401
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3039545975
Short name T610
Test name
Test status
Simulation time 140719981032 ps
CPU time 2077.93 seconds
Started Jan 17 02:59:21 PM PST 24
Finished Jan 17 03:33:59 PM PST 24
Peak memory 273308 kb
Host smart-77841828-d671-4493-af20-1a0c3449fc93
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039545975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3039545975
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1801398420
Short name T462
Test name
Test status
Simulation time 71701506578 ps
CPU time 6101.6 seconds
Started Jan 17 02:59:21 PM PST 24
Finished Jan 17 04:41:04 PM PST 24
Peak memory 349556 kb
Host smart-185fd477-d24a-4f73-bc43-872526f5df51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801398420 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1801398420
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.403234174
Short name T197
Test name
Test status
Simulation time 242768412 ps
CPU time 2.81 seconds
Started Jan 17 02:49:21 PM PST 24
Finished Jan 17 02:49:24 PM PST 24
Peak memory 248868 kb
Host smart-8b9aa38e-fe55-4d37-94bb-23c886ac3aff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=403234174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.403234174
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3532319152
Short name T263
Test name
Test status
Simulation time 73904258476 ps
CPU time 1344.65 seconds
Started Jan 17 02:49:06 PM PST 24
Finished Jan 17 03:11:34 PM PST 24
Peak memory 288472 kb
Host smart-07f0b692-4306-419f-84ba-1b83e1572f11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532319152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3532319152
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1813425338
Short name T213
Test name
Test status
Simulation time 121003520 ps
CPU time 7.69 seconds
Started Jan 17 02:49:14 PM PST 24
Finished Jan 17 02:49:23 PM PST 24
Peak memory 240488 kb
Host smart-24bf5953-9b32-4aba-94dc-848099081f52
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1813425338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1813425338
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.974712534
Short name T644
Test name
Test status
Simulation time 11877632605 ps
CPU time 166.48 seconds
Started Jan 17 02:49:04 PM PST 24
Finished Jan 17 02:51:56 PM PST 24
Peak memory 256316 kb
Host smart-b83f85fe-e12f-47b1-8b9c-705a97053be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97471
2534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.974712534
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2254747008
Short name T620
Test name
Test status
Simulation time 136221538 ps
CPU time 10.34 seconds
Started Jan 17 02:49:05 PM PST 24
Finished Jan 17 02:49:20 PM PST 24
Peak memory 252108 kb
Host smart-dc4e33a6-c270-487c-a2b4-4f382e921f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22547
47008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2254747008
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.347774788
Short name T324
Test name
Test status
Simulation time 82329129447 ps
CPU time 918.05 seconds
Started Jan 17 02:49:15 PM PST 24
Finished Jan 17 03:04:33 PM PST 24
Peak memory 272332 kb
Host smart-859e2d98-0141-455b-a6ec-1d0b5d2f2157
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347774788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.347774788
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.631896240
Short name T215
Test name
Test status
Simulation time 23147643233 ps
CPU time 1257.81 seconds
Started Jan 17 02:49:14 PM PST 24
Finished Jan 17 03:10:12 PM PST 24
Peak memory 288816 kb
Host smart-93062d7e-71c4-43a8-b22f-39dccf901997
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631896240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.631896240
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2363701891
Short name T291
Test name
Test status
Simulation time 16754102207 ps
CPU time 348.61 seconds
Started Jan 17 02:49:13 PM PST 24
Finished Jan 17 02:55:02 PM PST 24
Peak memory 247300 kb
Host smart-2a0a1dd4-e36d-4587-864b-4630d23c9d05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363701891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2363701891
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2943320300
Short name T404
Test name
Test status
Simulation time 843641020 ps
CPU time 52.17 seconds
Started Jan 17 02:49:08 PM PST 24
Finished Jan 17 02:50:02 PM PST 24
Peak memory 256660 kb
Host smart-3e69c6f3-71cf-48c3-97bf-f6f92452553f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29433
20300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2943320300
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.718280368
Short name T1
Test name
Test status
Simulation time 473896308 ps
CPU time 13.49 seconds
Started Jan 17 02:49:02 PM PST 24
Finished Jan 17 02:49:23 PM PST 24
Peak memory 247908 kb
Host smart-c956043b-8959-47eb-a4b3-65c1b8296543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71828
0368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.718280368
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.304755740
Short name T372
Test name
Test status
Simulation time 1980545366 ps
CPU time 32.45 seconds
Started Jan 17 02:49:04 PM PST 24
Finished Jan 17 02:49:42 PM PST 24
Peak memory 255660 kb
Host smart-1cb722ce-0166-40fb-8a62-efbf2eeb8f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30475
5740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.304755740
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.4075380989
Short name T219
Test name
Test status
Simulation time 159156974 ps
CPU time 10.12 seconds
Started Jan 17 02:49:06 PM PST 24
Finished Jan 17 02:49:20 PM PST 24
Peak memory 248624 kb
Host smart-f9c41763-712b-4c26-8acf-ec8f88fb93fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40753
80989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.4075380989
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2299625301
Short name T455
Test name
Test status
Simulation time 1022864746 ps
CPU time 43.24 seconds
Started Jan 17 02:49:15 PM PST 24
Finished Jan 17 02:49:59 PM PST 24
Peak memory 248688 kb
Host smart-13b9d10d-be8f-44be-a729-cab189408433
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299625301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2299625301
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.324993332
Short name T187
Test name
Test status
Simulation time 41877699 ps
CPU time 3.52 seconds
Started Jan 17 02:49:36 PM PST 24
Finished Jan 17 02:49:43 PM PST 24
Peak memory 248976 kb
Host smart-8839f44f-4627-484a-af4a-23ea11f9ce04
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=324993332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.324993332
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3995370062
Short name T64
Test name
Test status
Simulation time 7756084508 ps
CPU time 787.18 seconds
Started Jan 17 02:49:28 PM PST 24
Finished Jan 17 03:02:35 PM PST 24
Peak memory 265056 kb
Host smart-1803e95c-8a0d-455f-90fd-dc7bfd58af42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995370062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3995370062
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.434593753
Short name T459
Test name
Test status
Simulation time 266612424 ps
CPU time 8.19 seconds
Started Jan 17 02:49:36 PM PST 24
Finished Jan 17 02:49:47 PM PST 24
Peak memory 240436 kb
Host smart-ec94b423-c1fe-48d0-bd9b-e6dad21489da
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=434593753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.434593753
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.602374942
Short name T691
Test name
Test status
Simulation time 3050823489 ps
CPU time 86.44 seconds
Started Jan 17 02:49:27 PM PST 24
Finished Jan 17 02:50:54 PM PST 24
Peak memory 248892 kb
Host smart-f7f6bc2b-77d0-4caa-9a41-7fb4c56aa81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60237
4942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.602374942
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2998802284
Short name T413
Test name
Test status
Simulation time 1602205194 ps
CPU time 31.01 seconds
Started Jan 17 02:49:19 PM PST 24
Finished Jan 17 02:49:50 PM PST 24
Peak memory 254896 kb
Host smart-4994ce6e-e9d8-493f-b823-7aa6d372e6b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29988
02284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2998802284
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1020671158
Short name T312
Test name
Test status
Simulation time 170597896959 ps
CPU time 2478.27 seconds
Started Jan 17 02:49:34 PM PST 24
Finished Jan 17 03:30:58 PM PST 24
Peak memory 289192 kb
Host smart-caeb2a4a-aa4f-43f5-81ff-ff9aeb982d81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020671158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1020671158
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1420297520
Short name T669
Test name
Test status
Simulation time 31474390121 ps
CPU time 1828.95 seconds
Started Jan 17 02:49:36 PM PST 24
Finished Jan 17 03:20:08 PM PST 24
Peak memory 272316 kb
Host smart-5c81ba99-5d07-478f-9f97-63b5d5784df2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420297520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1420297520
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1199270816
Short name T299
Test name
Test status
Simulation time 39033791646 ps
CPU time 136.14 seconds
Started Jan 17 02:49:36 PM PST 24
Finished Jan 17 02:51:55 PM PST 24
Peak memory 247708 kb
Host smart-3c0f0855-b4a7-47b1-8698-8f9fe48be5d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199270816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1199270816
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.236631222
Short name T417
Test name
Test status
Simulation time 1566510337 ps
CPU time 15.07 seconds
Started Jan 17 02:49:19 PM PST 24
Finished Jan 17 02:49:35 PM PST 24
Peak memory 248680 kb
Host smart-f4fa5105-1d76-4116-bd59-4fe5a2fba4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23663
1222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.236631222
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2572583430
Short name T731
Test name
Test status
Simulation time 864184104 ps
CPU time 24.99 seconds
Started Jan 17 02:49:19 PM PST 24
Finished Jan 17 02:49:45 PM PST 24
Peak memory 254152 kb
Host smart-ad45654c-fe2f-4185-a24f-e2a1d63e419e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25725
83430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2572583430
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.7198184
Short name T434
Test name
Test status
Simulation time 103241625 ps
CPU time 7.84 seconds
Started Jan 17 02:49:25 PM PST 24
Finished Jan 17 02:49:33 PM PST 24
Peak memory 248680 kb
Host smart-fedd43a7-9db3-4656-964d-a34975685c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71981
84 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.7198184
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1954568875
Short name T626
Test name
Test status
Simulation time 5089132127 ps
CPU time 78.95 seconds
Started Jan 17 02:49:25 PM PST 24
Finished Jan 17 02:50:45 PM PST 24
Peak memory 248596 kb
Host smart-c7ede145-6fc9-4663-bab5-e722a60c0f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19545
68875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1954568875
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1526684459
Short name T236
Test name
Test status
Simulation time 48905633167 ps
CPU time 1721.42 seconds
Started Jan 17 02:49:34 PM PST 24
Finished Jan 17 03:18:21 PM PST 24
Peak memory 273220 kb
Host smart-60ec1753-ffa8-4b75-bcd2-95e20529e596
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526684459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1526684459
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1180050736
Short name T205
Test name
Test status
Simulation time 43301881 ps
CPU time 3.7 seconds
Started Jan 17 02:49:42 PM PST 24
Finished Jan 17 02:49:46 PM PST 24
Peak memory 248944 kb
Host smart-498a9d30-4b5b-4f9a-bbd6-17f18a651962
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1180050736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1180050736
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3266744488
Short name T657
Test name
Test status
Simulation time 41373235117 ps
CPU time 908.74 seconds
Started Jan 17 02:49:41 PM PST 24
Finished Jan 17 03:04:50 PM PST 24
Peak memory 273304 kb
Host smart-43719cf0-75d0-4f79-92ac-f684a6ddd6f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266744488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3266744488
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1424234530
Short name T421
Test name
Test status
Simulation time 136904696 ps
CPU time 8.2 seconds
Started Jan 17 02:49:40 PM PST 24
Finished Jan 17 02:49:48 PM PST 24
Peak memory 240228 kb
Host smart-a507ffd0-de31-4033-b8f0-c8198646126d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1424234530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1424234530
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.137977162
Short name T366
Test name
Test status
Simulation time 2686905710 ps
CPU time 96.95 seconds
Started Jan 17 02:49:41 PM PST 24
Finished Jan 17 02:51:18 PM PST 24
Peak memory 256352 kb
Host smart-eb4f0427-74aa-4b74-adaf-ce3d0aa1aa08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13797
7162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.137977162
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.180944431
Short name T220
Test name
Test status
Simulation time 354614718 ps
CPU time 19.84 seconds
Started Jan 17 02:49:33 PM PST 24
Finished Jan 17 02:49:58 PM PST 24
Peak memory 254844 kb
Host smart-dae70f97-82e2-47e5-8d94-3738511a4af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18094
4431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.180944431
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3980712816
Short name T214
Test name
Test status
Simulation time 55864180706 ps
CPU time 1289.12 seconds
Started Jan 17 02:49:42 PM PST 24
Finished Jan 17 03:11:12 PM PST 24
Peak memory 288976 kb
Host smart-30addc04-de4f-4e0a-af16-1fb9f5f50610
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980712816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3980712816
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3906253203
Short name T406
Test name
Test status
Simulation time 77007406423 ps
CPU time 1537.89 seconds
Started Jan 17 02:49:43 PM PST 24
Finished Jan 17 03:15:22 PM PST 24
Peak memory 289240 kb
Host smart-2abadf6b-bab4-4c21-ac23-8377f17a1c35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906253203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3906253203
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3929742227
Short name T285
Test name
Test status
Simulation time 52385563022 ps
CPU time 298.38 seconds
Started Jan 17 02:49:46 PM PST 24
Finished Jan 17 02:54:45 PM PST 24
Peak memory 247588 kb
Host smart-09d6d73b-bed5-4814-b2f8-0ee767b0eb6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929742227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3929742227
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1490014573
Short name T407
Test name
Test status
Simulation time 1352231335 ps
CPU time 26.09 seconds
Started Jan 17 02:49:33 PM PST 24
Finished Jan 17 02:49:59 PM PST 24
Peak memory 254920 kb
Host smart-aa57b264-0e91-4a54-9233-b7c379622d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14900
14573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1490014573
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.211042104
Short name T712
Test name
Test status
Simulation time 216668485 ps
CPU time 15.51 seconds
Started Jan 17 02:49:42 PM PST 24
Finished Jan 17 02:49:58 PM PST 24
Peak memory 254588 kb
Host smart-e6278d24-1398-4e5c-9d9c-c417832b6057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21104
2104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.211042104
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.4222385244
Short name T51
Test name
Test status
Simulation time 2631144483 ps
CPU time 47.27 seconds
Started Jan 17 02:49:36 PM PST 24
Finished Jan 17 02:50:26 PM PST 24
Peak memory 248748 kb
Host smart-3fdb4b09-bc0f-4e76-ad40-5639b183a87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42223
85244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.4222385244
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1409759107
Short name T513
Test name
Test status
Simulation time 14973419302 ps
CPU time 1723.16 seconds
Started Jan 17 02:49:41 PM PST 24
Finished Jan 17 03:18:24 PM PST 24
Peak memory 304756 kb
Host smart-d0547f93-e09b-4404-8f7f-b8361a73d11d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409759107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1409759107
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.958179500
Short name T60
Test name
Test status
Simulation time 188219622790 ps
CPU time 5776.11 seconds
Started Jan 17 02:49:41 PM PST 24
Finished Jan 17 04:25:58 PM PST 24
Peak memory 305900 kb
Host smart-a0a8436a-346c-4281-aa56-cbd2941a7a4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958179500 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.958179500
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1024301692
Short name T199
Test name
Test status
Simulation time 36652483 ps
CPU time 3.62 seconds
Started Jan 17 02:50:05 PM PST 24
Finished Jan 17 02:50:09 PM PST 24
Peak memory 248832 kb
Host smart-469dd5ea-cf52-4964-8783-b33bd9e8ece5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1024301692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1024301692
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1186873131
Short name T645
Test name
Test status
Simulation time 31121141873 ps
CPU time 2121.56 seconds
Started Jan 17 02:49:55 PM PST 24
Finished Jan 17 03:25:17 PM PST 24
Peak memory 288564 kb
Host smart-a23a2022-5fd5-4dc2-845f-a0772793c9d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186873131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1186873131
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2499490079
Short name T585
Test name
Test status
Simulation time 518585322 ps
CPU time 8.32 seconds
Started Jan 17 02:49:58 PM PST 24
Finished Jan 17 02:50:09 PM PST 24
Peak memory 240452 kb
Host smart-2b67be9a-22ea-4698-8c0f-4fe1174f0fdd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2499490079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2499490079
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1341290231
Short name T438
Test name
Test status
Simulation time 3235140675 ps
CPU time 172.59 seconds
Started Jan 17 02:49:50 PM PST 24
Finished Jan 17 02:52:44 PM PST 24
Peak memory 256544 kb
Host smart-6b15ff10-c49d-4683-be2b-858d2f87729a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13412
90231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1341290231
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3629340542
Short name T608
Test name
Test status
Simulation time 1401686077 ps
CPU time 14.95 seconds
Started Jan 17 02:49:50 PM PST 24
Finished Jan 17 02:50:07 PM PST 24
Peak memory 255348 kb
Host smart-20e96b59-8d97-4e9a-ac52-834e234efdad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36293
40542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3629340542
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.658066837
Short name T323
Test name
Test status
Simulation time 240421940087 ps
CPU time 1339.13 seconds
Started Jan 17 02:50:05 PM PST 24
Finished Jan 17 03:12:25 PM PST 24
Peak memory 288604 kb
Host smart-8e4ba230-6fe1-4360-ae5f-45939691ea6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658066837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.658066837
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.328225141
Short name T264
Test name
Test status
Simulation time 11944122296 ps
CPU time 1190.75 seconds
Started Jan 17 02:50:05 PM PST 24
Finished Jan 17 03:09:56 PM PST 24
Peak memory 287420 kb
Host smart-ba92aeee-c755-4d83-9e9e-a9331d4981b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328225141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.328225141
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1452686173
Short name T635
Test name
Test status
Simulation time 19256985324 ps
CPU time 382.8 seconds
Started Jan 17 02:50:06 PM PST 24
Finished Jan 17 02:56:29 PM PST 24
Peak memory 247604 kb
Host smart-48107e8d-24dc-4b09-a0d6-ccf66836042e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452686173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1452686173
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3401891696
Short name T613
Test name
Test status
Simulation time 852393364 ps
CPU time 51.92 seconds
Started Jan 17 02:49:49 PM PST 24
Finished Jan 17 02:50:42 PM PST 24
Peak memory 248664 kb
Host smart-ccea7243-1507-4745-b960-f735da0b1a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34018
91696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3401891696
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3514435684
Short name T422
Test name
Test status
Simulation time 379097761 ps
CPU time 33.12 seconds
Started Jan 17 02:49:48 PM PST 24
Finished Jan 17 02:50:21 PM PST 24
Peak memory 254004 kb
Host smart-89248d71-69f7-4d5a-a0e3-5f906ecfb261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35144
35684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3514435684
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1368941376
Short name T387
Test name
Test status
Simulation time 561628960 ps
CPU time 9.65 seconds
Started Jan 17 02:49:58 PM PST 24
Finished Jan 17 02:50:11 PM PST 24
Peak memory 251336 kb
Host smart-26577743-447f-4b11-89bb-686a3ae06fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13689
41376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1368941376
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1160798152
Short name T692
Test name
Test status
Simulation time 376452012 ps
CPU time 5.97 seconds
Started Jan 17 02:49:41 PM PST 24
Finished Jan 17 02:49:47 PM PST 24
Peak memory 240496 kb
Host smart-b0d192a3-8e27-470f-9283-fd2ad83a9967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11607
98152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1160798152
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.957879687
Short name T211
Test name
Test status
Simulation time 13899081170 ps
CPU time 1472.98 seconds
Started Jan 17 02:49:59 PM PST 24
Finished Jan 17 03:14:34 PM PST 24
Peak memory 288860 kb
Host smart-bd211fce-a77e-4089-b395-7a3ac6216d30
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957879687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.957879687
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1916400217
Short name T715
Test name
Test status
Simulation time 179636933830 ps
CPU time 3528.8 seconds
Started Jan 17 02:50:01 PM PST 24
Finished Jan 17 03:48:52 PM PST 24
Peak memory 297752 kb
Host smart-6e3c049f-38f3-469b-a546-375a303a75f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916400217 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1916400217
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3265897015
Short name T194
Test name
Test status
Simulation time 42639430 ps
CPU time 3.58 seconds
Started Jan 17 02:50:10 PM PST 24
Finished Jan 17 02:50:14 PM PST 24
Peak memory 248908 kb
Host smart-f385631a-daa5-4bd7-a242-f37e564b5e65
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3265897015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3265897015
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2792682409
Short name T90
Test name
Test status
Simulation time 73868968263 ps
CPU time 1746.39 seconds
Started Jan 17 02:50:06 PM PST 24
Finished Jan 17 03:19:13 PM PST 24
Peak memory 289536 kb
Host smart-125e55d2-f6f9-45d5-93cd-a9b7657cbfff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792682409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2792682409
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1381599181
Short name T403
Test name
Test status
Simulation time 167879644 ps
CPU time 10.11 seconds
Started Jan 17 02:50:12 PM PST 24
Finished Jan 17 02:50:22 PM PST 24
Peak memory 240476 kb
Host smart-4e77341c-8340-4b6a-87c8-4ca8fc565c01
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1381599181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1381599181
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4073499169
Short name T442
Test name
Test status
Simulation time 470302559 ps
CPU time 22.01 seconds
Started Jan 17 02:50:01 PM PST 24
Finished Jan 17 02:50:24 PM PST 24
Peak memory 248656 kb
Host smart-09620213-d0c2-4582-95df-853f816c93ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40734
99169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4073499169
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.4139018548
Short name T81
Test name
Test status
Simulation time 2098225659 ps
CPU time 47.15 seconds
Started Jan 17 02:50:02 PM PST 24
Finished Jan 17 02:50:51 PM PST 24
Peak memory 248228 kb
Host smart-ec67e1f8-dafa-4bed-9432-0d06a71238f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41390
18548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.4139018548
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1199509556
Short name T318
Test name
Test status
Simulation time 21839503293 ps
CPU time 1385.96 seconds
Started Jan 17 02:50:02 PM PST 24
Finished Jan 17 03:13:10 PM PST 24
Peak memory 265068 kb
Host smart-04a2febe-bb9c-4a2f-b898-1858f0ea2fc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199509556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1199509556
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2313033656
Short name T356
Test name
Test status
Simulation time 52538387705 ps
CPU time 3101.03 seconds
Started Jan 17 02:50:12 PM PST 24
Finished Jan 17 03:41:54 PM PST 24
Peak memory 289344 kb
Host smart-c85a606a-b8a8-4562-8e38-f7d1946ee3e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313033656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2313033656
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2712437156
Short name T719
Test name
Test status
Simulation time 59483378318 ps
CPU time 279.31 seconds
Started Jan 17 02:50:01 PM PST 24
Finished Jan 17 02:54:41 PM PST 24
Peak memory 247588 kb
Host smart-585ce855-f05b-499e-adb2-eba08ca8a843
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712437156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2712437156
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3050318381
Short name T342
Test name
Test status
Simulation time 1126623745 ps
CPU time 64.25 seconds
Started Jan 17 02:50:06 PM PST 24
Finished Jan 17 02:51:10 PM PST 24
Peak memory 248604 kb
Host smart-6df14424-3dd7-4ac7-b35f-c362f427a4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30503
18381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3050318381
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2367021206
Short name T674
Test name
Test status
Simulation time 391489498 ps
CPU time 16.76 seconds
Started Jan 17 02:50:01 PM PST 24
Finished Jan 17 02:50:19 PM PST 24
Peak memory 254136 kb
Host smart-3a8d1628-80b4-4755-a5c6-637daddf8991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23670
21206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2367021206
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.472485161
Short name T230
Test name
Test status
Simulation time 522136223 ps
CPU time 15.16 seconds
Started Jan 17 02:50:01 PM PST 24
Finished Jan 17 02:50:18 PM PST 24
Peak memory 246936 kb
Host smart-1768fe3a-0911-41c9-af4f-0d242f8b6ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47248
5161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.472485161
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.4195077035
Short name T271
Test name
Test status
Simulation time 533579141 ps
CPU time 31.12 seconds
Started Jan 17 02:50:05 PM PST 24
Finished Jan 17 02:50:37 PM PST 24
Peak memory 248680 kb
Host smart-0cfb39d3-318f-4ba3-9661-b98d1bd29e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41950
77035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.4195077035
Directory /workspace/9.alert_handler_smoke/latest
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