Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	72650164	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

35537753

1

T14

13467

T21

16490

T22

7992

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	16206254	1			T14	27109		T21	16641		T22	3574
values[0x0]	44504362	1			T14	209		T21	12134		T22	2267
values[0x1]	47477301	1			T14	200		T21	11994		T22	2151

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61615088	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

46572829

1

T14

17709

T21

19791

T22

7992

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	358138	1			T21	152		T22	32		T23	4
valid_sources[0x01]	347391	1			T21	276		T22	35		T23	7
valid_sources[0x02]	358485	1			T21	118		T22	35		T23	9
valid_sources[0x03]	351652	1			T21	68		T22	31		T23	3
valid_sources[0x04]	346164	1			T21	194		T22	38		T23	3
valid_sources[0x05]	345877	1			T14	174		T21	172		T22	38
valid_sources[0x06]	351079	1			T14	174		T21	170		T22	41
valid_sources[0x07]	344078	1			T14	174		T21	165		T22	26
valid_sources[0x08]	356441	1			T14	174		T21	94		T22	43
valid_sources[0x09]	341951	1			T21	230		T22	32		T23	12
valid_sources[0x0a]	341515	1			T21	131		T22	34		T23	18
valid_sources[0x0b]	716528	1			T21	169		T22	43		T23	5
valid_sources[0x0c]	575677	1			T14	174		T21	120		T22	40
valid_sources[0x0d]	352119	1			T21	209		T22	24		T23	2
valid_sources[0x0e]	622783	1			T21	203		T22	28		T23	10
valid_sources[0x0f]	356517	1			T21	138		T22	43		T23	4
valid_sources[0x10]	852826	1			T21	252		T22	26		T23	7
valid_sources[0x11]	382461	1			T21	128		T22	31		T23	8
valid_sources[0x12]	352600	1			T14	174		T21	82		T22	38
valid_sources[0x13]	349635	1			T21	123		T22	23		T23	8
valid_sources[0x14]	350340	1			T21	194		T22	31		T23	7
valid_sources[0x15]	706770	1			T14	174		T21	204		T22	31
valid_sources[0x16]	345076	1			T21	133		T22	25		T23	3
valid_sources[0x17]	360565	1			T21	139		T22	31		T23	2
valid_sources[0x18]	345190	1			T21	130		T22	31		T25	10
valid_sources[0x19]	343900	1			T21	131		T22	33		T23	4
valid_sources[0x1a]	348890	1			T21	180		T22	29		T23	16
valid_sources[0x1b]	366087	1			T21	146		T22	28		T23	4
valid_sources[0x1c]	355033	1			T14	174		T21	176		T22	33
valid_sources[0x1d]	365203	1			T21	122		T22	24		T23	5
valid_sources[0x1e]	356408	1			T21	310		T22	34		T23	9
valid_sources[0x1f]	367918	1			T14	174		T21	256		T22	36
valid_sources[0x20]	545148	1			T21	147		T22	29		T23	5
valid_sources[0x21]	354950	1			T14	174		T21	161		T22	39
valid_sources[0x22]	430687	1			T21	117		T22	26		T23	5
valid_sources[0x23]	727737	1			T21	264		T22	26		T25	14
valid_sources[0x24]	353917	1			T21	162		T22	20		T23	12
valid_sources[0x25]	353674	1			T14	174		T21	246		T22	28
valid_sources[0x26]	663294	1			T21	198		T22	36		T23	6
valid_sources[0x27]	345895	1			T14	348		T21	161		T22	30
valid_sources[0x28]	353340	1			T21	95		T22	32		T23	1
valid_sources[0x29]	345126	1			T21	174		T22	29		T23	1
valid_sources[0x2a]	357369	1			T21	170		T22	36		T23	9
valid_sources[0x2b]	376681	1			T14	348		T21	146		T22	36
valid_sources[0x2c]	363832	1			T21	146		T22	30		T23	6
valid_sources[0x2d]	771308	1			T21	119		T22	19		T23	7
valid_sources[0x2e]	349014	1			T21	184		T22	22		T23	2
valid_sources[0x2f]	345170	1			T21	160		T22	23		T25	19
valid_sources[0x30]	351051	1			T14	174		T21	184		T22	35
valid_sources[0x31]	340097	1			T21	162		T22	27		T23	4
valid_sources[0x32]	371303	1			T14	14294		T21	162		T22	35
valid_sources[0x33]	354722	1			T14	174		T21	214		T22	28
valid_sources[0x34]	732606	1			T21	181		T22	37		T23	2
valid_sources[0x35]	352613	1			T21	231		T22	28		T23	9
valid_sources[0x36]	354297	1			T14	174		T21	241		T22	29
valid_sources[0x37]	706150	1			T21	100		T22	25		T23	4
valid_sources[0x38]	358614	1			T21	169		T22	37		T23	9
valid_sources[0x39]	824084	1			T21	216		T22	36		T23	2
valid_sources[0x3a]	365294	1			T14	174		T21	216		T22	28
valid_sources[0x3b]	346729	1			T14	174		T21	236		T22	32
valid_sources[0x3c]	363303	1			T21	95		T22	33		T24	4
valid_sources[0x3d]	357388	1			T21	154		T22	22		T23	2
valid_sources[0x3e]	344649	1			T14	174		T21	256		T22	26
valid_sources[0x3f]	355677	1			T14	174		T21	135		T22	32
valid_sources[0x40]	350415	1			T14	174		T21	148		T22	36
valid_sources[0x41]	644827	1			T14	174		T21	85		T22	29
valid_sources[0x42]	357632	1			T21	116		T22	38		T23	6
valid_sources[0x43]	351288	1			T21	142		T22	37		T23	8
valid_sources[0x44]	815164	1			T14	174		T21	220		T22	20
valid_sources[0x45]	346311	1			T21	37		T22	24		T23	3
valid_sources[0x46]	350171	1			T21	225		T22	27		T23	5
valid_sources[0x47]	348643	1			T14	174		T21	179		T22	39
valid_sources[0x48]	339812	1			T21	152		T22	36		T23	1
valid_sources[0x49]	339026	1			T21	172		T22	39		T23	7
valid_sources[0x4a]	354633	1			T21	160		T22	31		T23	5
valid_sources[0x4b]	345580	1			T21	96		T22	30		T23	6
valid_sources[0x4c]	367652	1			T21	101		T22	35		T23	5
valid_sources[0x4d]	991600	1			T21	196		T22	47		T23	7
valid_sources[0x4e]	805289	1			T21	193		T22	32		T23	5
valid_sources[0x4f]	349270	1			T14	174		T21	152		T22	30
valid_sources[0x50]	360592	1			T21	118		T22	25		T23	2
valid_sources[0x51]	431040	1			T21	334		T22	31		T23	4
valid_sources[0x52]	356542	1			T21	194		T22	29		T23	1
valid_sources[0x53]	348313	1			T21	118		T22	27		T23	24
valid_sources[0x54]	342687	1			T21	196		T22	33		T23	10
valid_sources[0x55]	346861	1			T21	102		T22	31		T23	3
valid_sources[0x56]	369566	1			T14	174		T21	140		T22	42
valid_sources[0x57]	690977	1			T14	174		T21	125		T22	33
valid_sources[0x58]	715364	1			T21	150		T22	30		T23	11
valid_sources[0x59]	355911	1			T21	103		T22	35		T23	3
valid_sources[0x5a]	629094	1			T21	164		T22	26		T23	1
valid_sources[0x5b]	356249	1			T14	174		T21	179		T22	40
valid_sources[0x5c]	345982	1			T14	174		T21	197		T22	36
valid_sources[0x5d]	350820	1			T21	149		T22	19		T23	3
valid_sources[0x5e]	351099	1			T14	174		T21	170		T22	41
valid_sources[0x5f]	390887	1			T14	348		T21	113		T22	23
valid_sources[0x60]	358972	1			T21	194		T22	28		T23	12
valid_sources[0x61]	1125573	1			T21	152		T22	34		T23	10
valid_sources[0x62]	347177	1			T14	174		T21	113		T22	34
valid_sources[0x63]	349943	1			T14	348		T21	162		T22	40
valid_sources[0x64]	350160	1			T21	157		T22	29		T23	1
valid_sources[0x65]	376091	1			T21	138		T22	34		T23	4
valid_sources[0x66]	348588	1			T21	134		T22	35		T23	9
valid_sources[0x67]	355884	1			T21	208		T22	35		T23	8
valid_sources[0x68]	353506	1			T21	78		T22	36		T23	10
valid_sources[0x69]	354876	1			T21	261		T22	24		T23	4
valid_sources[0x6a]	354151	1			T21	78		T22	38		T23	6
valid_sources[0x6b]	361040	1			T21	143		T22	36		T23	6
valid_sources[0x6c]	580750	1			T21	167		T22	32		T23	6
valid_sources[0x6d]	840390	1			T21	173		T22	26		T23	1
valid_sources[0x6e]	346838	1			T21	179		T22	31		T23	6
valid_sources[0x6f]	348834	1			T21	125		T22	29		T23	7
valid_sources[0x70]	349443	1			T21	143		T22	40		T23	6
valid_sources[0x71]	360998	1			T14	174		T21	159		T22	28
valid_sources[0x72]	347095	1			T21	117		T22	32		T23	10
valid_sources[0x73]	348868	1			T21	100		T22	23		T23	9
valid_sources[0x74]	374701	1			T21	230		T22	26		T23	2
valid_sources[0x75]	344476	1			T14	174		T21	171		T22	28
valid_sources[0x76]	385002	1			T21	188		T22	33		T23	1
valid_sources[0x77]	371160	1			T21	223		T22	27		T23	1
valid_sources[0x78]	354155	1			T21	150		T22	33		T23	3
valid_sources[0x79]	362273	1			T21	136		T22	36		T23	4
valid_sources[0x7a]	643963	1			T21	223		T22	27		T23	5
valid_sources[0x7b]	363981	1			T14	174		T21	384		T22	25
valid_sources[0x7c]	373743	1			T21	237		T22	32		T23	10
valid_sources[0x7d]	351331	1			T21	153		T22	34		T23	8
valid_sources[0x7e]	358212	1			T14	174		T21	134		T22	22
valid_sources[0x7f]	352399	1			T21	222		T22	27		T23	4
valid_sources[0x80]	352222	1			T21	197		T22	37		T23	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8143812

1

T14

13327

T21

8297

T22

3574

values[0x0]

all_enables

biggest_size

17220759

1

T14

92

T21

5084

T22

2267

values[0x1]

all_enables

biggest_size

10173182

1

T14

48

T21

3109

T22

2151